[MachineVerifier] Verify that a DBG_VALUE has a debug location

[vsk]

Summary

Verify that each DBG_VALUE has a debug location. This is required by
LiveDebugValues, and perhaps by other late passes.

There's an exception for tests: lots of tests use a two-operand form of
DBG_VALUE for convenience. There's no reason to prevent that.

This is an extension of D80665, but there's no dependency.

[jmorse]

LGTM

llvm/lib/CodeGen/MachineVerifier.cpp

if (FirstNonPHI)
       report("Found PHI instruction after non-PHI", MI);
   } else if (FirstNonPHI == nullptr)
     FirstNonPHI = MI;
 
   // Check the tied operands.
   if (MI->isInlineAsm())
     verifyInlineAsm(MI);
 
+  // A fully-formed DBG_VALUE must have a location. Ignore partially formed
+  // DBG_VALUEs: these are convenient to use in tests, but should never get
+  // generated.
+  if (MI->isDebugValue() && MI->getNumOperands() == 4)
+    if (!MI->getDebugLoc())
+      report("Missing DebugLoc for debug instruction", MI);
+
   // Check the MachineMemOperands for basic consistency.
   for (MachineMemOperand *Op : MI->memoperands()) {
     if (Op->isLoad() && !MI->mayLoad())
       report("Missing mayLoad flag", MI);
     if (Op->isStore() && !MI->mayStore())
       report("Missing mayStore flag", MI);
   }
 

llvm/test/CodeGen/Hexagon/early-if-debug.mir

 # CHECK: DBG_VALUE %0, $noreg
 # CHECK: %3:intregs = A2_tfrsi 321
 # CHECK: %5:intregs = C2_mux %1, %2, %3
 
 --- |
   define void @foo() {
     ret void
   }
-  !1 = !DIExpression()
 ...
 ---
 name: foo
 tracksRegLiveness: true
 registers:
   - { id: 0, class: intregs }
   - { id: 1, class: predregs }
   - { id: 2, class: intregs }
   - { id: 3, class: intregs }
   - { id: 4, class: intregs }
 body:             |
   bb.0:
     liveins: $r0
 
     %0 = COPY $r0
     %1 = C2_cmpeqi %0, 0
     %2 = A2_tfrsi 123
     J2_jumpt %1, %bb.2, implicit-def dead $pc
     J2_jump %bb.1, implicit-def dead $pc
 
   bb.1:
-    DBG_VALUE %0, $noreg, !1, !1
-    DBG_VALUE %0, $noreg, !1, !1
-    DBG_VALUE %0, $noreg, !1, !1
-    DBG_VALUE %0, $noreg, !1, !1
-    DBG_VALUE %0, $noreg, !1, !1
+    DBG_VALUE %0, $noreg
+    DBG_VALUE %0, $noreg
+    DBG_VALUE %0, $noreg
+    DBG_VALUE %0, $noreg
+    DBG_VALUE %0, $noreg
     %3 = A2_tfrsi 321
 
   bb.2:
     %4 = PHI %2, %bb.0, %3, %bb.1
 
 ...

llvm/test/CodeGen/MIR/Generic/dbg-value-missing-loc.mir

+# RUN: not --crash llc -run-pass machineverifier -o - %s 2>&1 | FileCheck %s
+
+# CHECK: Bad machine code: Missing DebugLoc for debug instruction
+# CHECK: - instruction: DBG_VALUE 1, 2, 3, 4
+
+--- |
+
+  define i32 @foo() {
+  entry:
+    ret i32 0
+  }
+
+...
+---
+name:            foo
+body: |
+  bb.0.entry:
+    DBG_VALUE 1, 2, 3, 4
+...

llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir

frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
 body: |
   bb.0.entry:
     liveins: $edi
 
     %0 = COPY $edi
-  ; CHECK:      DBG_VALUE $noreg, i32 0, !DIExpression(), !12
-  ; CHECK-NEXT: DBG_VALUE $noreg, i64 -22, !DIExpression(), !12
-  ; CHECK-NEXT: DBG_VALUE $noreg, i128 123492148938512984928424384934328985928, !DIExpression(), !12
-    DBG_VALUE _, i32 0, !DIExpression(), !13
-    DBG_VALUE _, i64 -22, !DIExpression(), !13
-    DBG_VALUE _, i128 123492148938512984928424384934328985928, !DIExpression(), !13
+  ; CHECK:      DBG_VALUE $noreg, i32 0, !11, !DIExpression()
+  ; CHECK-NEXT: DBG_VALUE $noreg, i64 -22, !11, !DIExpression()
+  ; CHECK-NEXT: DBG_VALUE $noreg, i128 123492148938512984928424384934328985928, !11, !DIExpression()
+    DBG_VALUE _, i32 0, !12, !DIExpression(), debug-location !13
+    DBG_VALUE _, i64 -22, !12, !DIExpression(), debug-location !13
+    DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !DIExpression(), debug-location !13
     MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
     $eax = COPY %0
     RETQ $eax
 ...
 ---
 name:            test_mir_created
 tracksRegLiveness: true
 registers:

llvm/test/CodeGen/MIR/X86/metadata-operands.mir

 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
 body: |
   bb.0.entry:
     liveins: $edi
     ; CHECK:      %0:gr32 = COPY $edi
     ; CHECK-NEXT: DBG_VALUE $noreg, 0, !11, !DIExpression()
     %0 = COPY $edi
-    DBG_VALUE _, 0, !12, !DIExpression()
+    DBG_VALUE _, 0, !12, !DIExpression(), debug-location !13
     MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
     $eax = COPY %0
     RETQ $eax
 ...

llvm/test/CodeGen/RISCV/select-optimize-multiple.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=riscv32 -run-pass=finalize-isel -simplify-mir -o - %s \
 # RUN:  | FileCheck -check-prefix=RV32I %s
 # RUN: llc -mtriple=riscv64 -run-pass=finalize-isel -simplify-mir -o - %s \
 # RUN:  | FileCheck -check-prefix=RV64I %s
 
 # Provide dummy definitions of functions and just enough metadata to create a
 # DBG_VALUE.
 --- |
   define void @cmov_interleaved_bad() {
     ret void
   }
   define void @cmov_interleaved_debug_value() {
     ret void
   }
-  !1 = !DIExpression()
 ...
 ---
 # Here we have a sequence of select instructions with a non-select instruction
 # in the middle. Because the non-select depends on the result of a previous
 # select, we cannot optimize the sequence to share control-flow.
 name:            cmov_interleaved_bad
 alignment:       4
 tracksRegLiveness: true
bb.0:
     ; RV32I: liveins: $x10, $x11, $x12, $x13
     ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x13
     ; RV32I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
     ; RV32I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
     ; RV32I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
     ; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
     ; RV32I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
     ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
-    ; RV32I: DBG_VALUE [[ADDI]], $noreg, !DIExpression(), !DIExpression()
+    ; RV32I: DBG_VALUE [[ADDI]], $noreg
     ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2
     ; RV32I: .1:
     ; RV32I: .2:
     ; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
     ; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
-    ; RV32I: DBG_VALUE [[PHI]], $noreg, !DIExpression(), !DIExpression()
-    ; RV32I: DBG_VALUE [[PHI1]], $noreg, !DIExpression(), !DIExpression()
+    ; RV32I: DBG_VALUE [[PHI]], $noreg
+    ; RV32I: DBG_VALUE [[PHI1]], $noreg
     ; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
     ; RV32I: $x10 = COPY [[ADD]]
     ; RV32I: PseudoRET implicit $x10
     ; RV64I-LABEL: name: cmov_interleaved_debug_value
     ; RV64I: successors: %bb.1, %bb.2
     ; RV64I: liveins: $x10, $x11, $x12, $x13
     ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13
     ; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
     ; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
     ; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
     ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
     ; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
     ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
-    ; RV64I: DBG_VALUE [[ADDI]], $noreg, !DIExpression(), !DIExpression()
+    ; RV64I: DBG_VALUE [[ADDI]], $noreg
     ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
     ; RV64I: .1:
     ; RV64I: .2:
     ; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
     ; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
-    ; RV64I: DBG_VALUE [[PHI]], $noreg, !DIExpression(), !DIExpression()
-    ; RV64I: DBG_VALUE [[PHI1]], $noreg, !DIExpression(), !DIExpression()
+    ; RV64I: DBG_VALUE [[PHI]], $noreg
+    ; RV64I: DBG_VALUE [[PHI1]], $noreg
     ; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
     ; RV64I: $x10 = COPY [[ADD]]
     ; RV64I: PseudoRET implicit $x10
     %3:gpr = COPY $x13
     %2:gpr = COPY $x12
     %1:gpr = COPY $x11
     %0:gpr = COPY $x10
     %5:gpr = ANDI %0, 1
     %6:gpr = COPY $x0
     %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %1, %2
-    DBG_VALUE %7, $noreg, !1, !1
+    DBG_VALUE %7, $noreg
     %8:gpr = ADDI %0, 1
-    DBG_VALUE %8, $noreg, !1, !1
+    DBG_VALUE %8, $noreg
     %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %3, %2
-    DBG_VALUE %9, $noreg, !1, !1
+    DBG_VALUE %9, $noreg
     %10:gpr = ADD %7, killed %9
     $x10 = COPY %10
     PseudoRET implicit $x10
 
 ...
 ---

llvm/test/CodeGen/X86/machine-cp-debug.mir

 # RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass=machine-cp %s -o - | FileCheck %s
 
 # Machine copy propagation can remove dead copies. Make sure that the
 # DBG_VALUE does not keep the copy alive.
 #
 # CHECK-NOT: $ebx = COPY $eax
 
 --- |
   define void @fred() {
     ret void
   }
-  !1 = !DIExpression()
 ...
 
 ---
 name: fred
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $eax
     $ebx = COPY $eax
-    DBG_VALUE $ebx, _, !1, !1
+    DBG_VALUE $ebx, _
 ...

llvm/test/CodeGen/X86/pr38952.mir

 body:             |
   bb.0.entry:
     successors: %bb.2(0x40000000), %bb.1(0x40000000)
     liveins: $edi
   
   ; Test that the DBG_VALUE on ebx below is sunk with the def of ebx, despite
   ; not being adjacent to the def, see PR38952
 
-    DBG_VALUE $edi, $noreg, !21, !DIExpression()
+    DBG_VALUE $edi, $noreg
     renamable $ebx = COPY $edi
     renamable $eax = MOV32r0 implicit-def dead $eflags
-    DBG_VALUE $ebx, $noreg, !21, !DIExpression()
+    DBG_VALUE $ebx, $noreg
     CMP32ri $edi, 255, implicit-def $eflags
     JCC_1 %bb.2, 15, implicit killed $eflags
     JMP_1 %bb.1
   
   bb.1.if.end:
   ; CHECK-LABEL: bb.1.if.end
     successors: %bb.2(0x80000000)
     liveins: $ebx