[RISCV] Enable 'undisturbed' semantics in instruction definitions.

[HsiangKai]

Summary

In RISC-V V specification, 'undisturbed' means the values of destination registers will not be changed. There are two scenarios there will be 'undisturbed' elements. One is for tail elements and the other is masked off elements. If the instructions have 'undisturbed' semantics, destination register is also one of the inputs of the instructions.

[rogfer01]

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

831

Shouldn't these instructions have a maskedoff field as well? As you mention undisturbed applies both to inactive elements (masked-off) and tail elements.

That is what I understand from https://riscv.github.io/documents/riscv-v-spec/#sec-mask-register-logical

Vector mask logical instructions are always unmasked so there are no inactive elements. Mask elements past vl, the tail elements, are unchanged.

[HsiangKai]

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

831

It seems like every instruction should have maskedoff argument, because every instruction may have tail elements. I will review it. Thanks, Roger.

[HsiangKai]

I need to think about is it necessary to describe 'undisturbed' semantics in instruction definitions. Do not review it now.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

bool RISCVAsmParser::validateInstruction(MCInst &Inst,
   unsigned TargetFlags =
       (MCID.TSFlags >> RISCV::ConstraintOffset) & RISCV::ConstraintMask;
   if (TargetFlags == RISCV::NoConstraint)
     return false;
 
   unsigned DestReg = Inst.getOperand(0).getReg();
   // Operands[1] will be the first operand, DestReg.
   SMLoc Loc = Operands[1]->getStartLoc();
+  unsigned Src2Idx = 1;
+  unsigned Src1Idx = 2;
+  unsigned MaskIdx;
+  // Masked instructions have 5 operands. vd, maskedoff, vs2, vs1, mask.
+  // Non-masked instructions have 3 operands. vd, vs2, vs1.
+  if (Inst.getNumOperands() == 5) {
+    Src2Idx = 2;
+    Src1Idx = 3;
+    MaskIdx = 4;
+  }
   if ((TargetFlags == RISCV::WidenV) || (TargetFlags == RISCV::WidenW) ||
-      (TargetFlags == RISCV::SlideUp) || (TargetFlags == RISCV::Vrgather) ||
-      (TargetFlags == RISCV::Vcompress)) {
+      (TargetFlags == RISCV::SlideUp) || (TargetFlags == RISCV::Vrgather)) {
     if (TargetFlags != RISCV::WidenW) {
-      unsigned Src2Reg = Inst.getOperand(1).getReg();
+      unsigned Src2Reg = Inst.getOperand(Src2Idx).getReg();
       if (DestReg == Src2Reg)
         return Error(Loc, "The destination vector register group cannot overlap"
                           " the source vector register group.");
     }
-    if (Inst.getOperand(2).isReg()) {
-      unsigned Src1Reg = Inst.getOperand(2).getReg();
+    if (Inst.getOperand(Src1Idx).isReg()) {
+      unsigned Src1Reg = Inst.getOperand(Src1Idx).getReg();
       if (DestReg == Src1Reg)
         return Error(Loc, "The destination vector register group cannot overlap"
                           " the source vector register group.");
     }
-    if (Inst.getNumOperands() == 4) {
-      unsigned MaskReg = Inst.getOperand(3).getReg();
+    if (Inst.getNumOperands() == 5) {
+      unsigned MaskReg = Inst.getOperand(MaskIdx).getReg();
 
       if (DestReg == MaskReg)
         return Error(Loc, "The destination vector register group cannot overlap"
                           " the mask register.");
     }
   } else if (TargetFlags == RISCV::Narrow) {
-    unsigned Src2Reg = Inst.getOperand(1).getReg();
+    unsigned Src2Reg = Inst.getOperand(Src2Idx).getReg();
     if (DestReg == Src2Reg)
       return Error(Loc, "The destination vector register group cannot overlap"
                         " the source vector register group.");
-  } else if (TargetFlags == RISCV::WidenCvt || TargetFlags == RISCV::Iota) {
-    unsigned Src2Reg = Inst.getOperand(1).getReg();
+  } else if (TargetFlags == RISCV::Vcompress) {
+    unsigned Src2Reg = Inst.getOperand(2).getReg();
     if (DestReg == Src2Reg)
       return Error(Loc, "The destination vector register group cannot overlap"
                         " the source vector register group.");
-    if (Inst.getNumOperands() == 3) {
-      unsigned MaskReg = Inst.getOperand(2).getReg();
+    unsigned Src1Reg = Inst.getOperand(3).getReg();
+    if (DestReg == Src1Reg)
+      return Error(Loc, "The destination vector register group cannot overlap"
+                        " the source vector register group.");
+  } else if (TargetFlags == RISCV::WidenCvt || TargetFlags == RISCV::NarrowCvt ||
+             TargetFlags == RISCV::Iota) {
+    unsigned Src2Reg = Inst.getOperand(2).getReg();
+    if (DestReg == Src2Reg)
+      return Error(Loc, "The destination vector register group cannot overlap"
+                        " the source vector register group.");
+    if (Inst.getNumOperands() == 4) {
+      unsigned MaskReg = Inst.getOperand(3).getReg();
 
       if (DestReg == MaskReg)
         return Error(Loc, "The destination vector register group cannot overlap"
                           " the mask register.");
     }
   }
   return false;
 }

llvm/lib/Target/RISCV/RISCVInstrFormats.td

class RISCVVConstraint<bits<4> val> {
   bits<4> Value = val;
 }
 def NoConstraint : RISCVVConstraint<0>;
 def WidenV       : RISCVVConstraint<1>;
 def WidenW       : RISCVVConstraint<2>;
 def WidenCvt     : RISCVVConstraint<3>;
 def QuadWiden    : RISCVVConstraint<4>;
 def Narrow       : RISCVVConstraint<5>;
-def Iota         : RISCVVConstraint<6>;
-def SlideUp      : RISCVVConstraint<7>;
-def Vrgather     : RISCVVConstraint<8>;
-def Vcompress    : RISCVVConstraint<9>;
+def NarrowCvt    : RISCVVConstraint<6>;
+def Iota         : RISCVVConstraint<7>;
+def SlideUp      : RISCVVConstraint<8>;
+def Vrgather     : RISCVVConstraint<9>;
+def Vcompress    : RISCVVConstraint<10>;
 
 // The following opcode names match those given in Table 19.1 in the
 // RISC-V User-level ISA specification ("RISC-V base opcode map").
 class RISCVOpcode<bits<7> val> {
   bits<7> Value = val;
 }
 def OPC_LOAD      : RISCVOpcode<0b0000011>;
 def OPC_LOAD_FP   : RISCVOpcode<0b0000111>;

llvm/lib/Target/RISCV/RISCVInstrInfo.h

 // Match with the definitions in RISCVInstrFormatsV.td
 enum RVVConstraintType {
   NoConstraint = 0,
   WidenV = 1,
   WidenW = 2,
   WidenCvt = 3,
   QuadWiden = 4,
   Narrow = 5,
-  Iota = 6,
-  SlideUp = 7,
-  Vrgather = 8,
-  Vcompress = 9,
+  NarrowCvt = 6,
+  Iota = 7,
+  SlideUp = 8,
+  Vrgather = 9,
+  Vcompress = 10,
 
   ConstraintOffset = 5,
   ConstraintMask = 0b1111
 };
 } // end namespace RISCV
 
 } // end namespace llvm
 #endif

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
 // load vd, (rs1), vm
 class VUnitStrideLoad<RISCVMOP mop, RISCVLSUMOP lumop, RISCVWidth width,
                         string opcodestr>
     : RVInstVLU<0b000, mop, lumop, width, (outs VRegOp:$vd),
-                (ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">;
+                (ins VRegOp:$maskedoff, GPR:$rs1, VMaskOp:$vm),
+                opcodestr, "$vd, (${rs1})$vm"> {
+  let Constraints = "$vd = $maskedoff";
+}
 
 // load vd, (rs1), rs2, vm
 class VStridedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
     : RVInstVLS<0b000, mop, width, (outs VRegOp:$vd),
-                (ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
-                "$vd, (${rs1}), $rs2$vm">;
+                (ins VRegOp:$maskedoff, GPR:$rs1, GPR:$rs2, VMaskOp:$vm),
+                opcodestr, "$vd, (${rs1}), $rs2$vm"> {
+  let Constraints = "$vd = $maskedoff";
+}
 
 // load vd, (rs1), vs2, vm
 class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
     : RVInstVLX<0b000, mop, width, (outs VRegOp:$vd),
-                (ins GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm), opcodestr,
-                "$vd, (${rs1}), $vs2$vm">;
+                (ins VRegOp:$maskedoff, GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm),
+                opcodestr, "$vd, (${rs1}), $vs2$vm"> {
+  let Constraints = "$vd = $maskedoff";
+}
 
 // vl<nf>r.v vd, (rs1)
 class VWholeLoad<bits<3> nf, string opcodestr>
     : RVInstVLU<nf, MOPLDUnitStrideU, LUMOPUnitStrideWholeReg,
                 LSWidthVSEW, (outs VRegOp:$vd), (ins GPR:$rs1),
                 opcodestr, "$vd, (${rs1})"> {
   let vm = 1;
   let Uses = [];
: RVInstVSU<nf, MOPSTUnitStride, SUMOPUnitStrideWholeReg,
                 opcodestr, "$vs3, (${rs1})"> {
   let vm = 1;
   let Uses = [];
 }
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 1
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 // op vd, vs2, vs1, vm
-class VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr,
+             string constraints = "">
     : RVInstVV<funct6, opv, (outs VRegOp:$vd),
-                (ins VRegOp:$vs2, VRegOp:$vs1, VMaskOp:$vm),
-                opcodestr, "$vd, $vs2, $vs1$vm">;
+                (ins VRegOp:$maskedoff, VRegOp:$vs2, VRegOp:$vs1, VMaskOp:$vm),
+                opcodestr, "$vd, $vs2, $vs1$vm"> {
+  let Constraints = !if(!eq(constraints, ""), "$vd = $maskedoff",
+                        constraints#",$vd = $maskedoff");
+}
 
 // op vd, vs2, vs1, v0 (without mask, use v0 as carry input)
 class VALUmVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
     : RVInstVV<funct6, opv, (outs VRegOp:$vd),
                 (ins VRegOp:$vs2, VRegOp:$vs1, VMV0:$v0),
                 opcodestr, "$vd, $vs2, $vs1, v0"> {
   let vm = 0;
 }
 
 // op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
-class VALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr,
+              string constraints = "">
     : RVInstVV<funct6, opv, (outs VRegOp:$vd),
-                (ins VRegOp:$vs1, VRegOp:$vs2, VMaskOp:$vm),
-                opcodestr, "$vd, $vs1, $vs2$vm">;
+                (ins VRegOp:$maskedoff, VRegOp:$vs1, VRegOp:$vs2, VMaskOp:$vm),
+                opcodestr, "$vd, $vs1, $vs2$vm"> {
+  let Constraints = !if(!eq(constraints, ""), "$vd = $maskedoff",
+                        constraints#",$vd = $maskedoff");
+}
 
 // op vd, vs1, vs2
 class VALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
     : RVInstVV<funct6, opv, (outs VRegOp:$vd),
                (ins VRegOp:$vs2, VRegOp:$vs1),
                opcodestr, "$vd, $vs2, $vs1"> {
   let vm = 1;
 }
 
+class VALUVVNoVmMaskedOff<bits<6> funct6, RISCVVFormat opv, string opcodestr,
+                          string constraints = "">
+    : RVInstVV<funct6, opv, (outs VRegOp:$vd),
+               (ins VRegOp:$maskedoff, VRegOp:$vs2, VRegOp:$vs1),
+               opcodestr, "$vd, $vs2, $vs1"> {
+  let vm = 1;
+  let Constraints = !if(!eq(constraints, ""), "$vd = $maskedoff",
+                        constraints#",$vd = $maskedoff");
+}
+
 // op vd, vs2, rs1, vm
-class VALUVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VALUVX<bits<6> funct6, RISCVVFormat opv, string opcodestr,
+             string constraints = "">
     : RVInstVX<funct6, opv, (outs VRegOp:$vd),
-                (ins VRegOp:$vs2, GPR:$rs1, VMaskOp:$vm),
-                opcodestr, "$vd, $vs2, $rs1$vm">;
+                (ins VRegOp:$maskedoff, VRegOp:$vs2, GPR:$rs1, VMaskOp:$vm),
+                opcodestr, "$vd, $vs2, $rs1$vm"> {
+  let Constraints = !if(!eq(constraints, ""), "$vd = $maskedoff",
+                        constraints#",$vd = $maskedoff");
+}
 
 // op vd, vs2, rs1, v0 (without mask, use v0 as carry input)
-class VALUmVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VALUmVX<bits<6> funct6, RISCVVFormat opv, string opcodestr,
+              string constraints = "">
     : RVInstVX<funct6, opv, (outs VRegOp:$vd),
-                (ins VRegOp:$vs2, GPR:$rs1, VMV0:$v0),
+                (ins VRegOp:$maskedoff, VRegOp:$vs2, GPR:$rs1, VMV0:$v0),
                 opcodestr, "$vd, $vs2, $rs1, v0"> {
   let vm = 0;
+  let Constraints = !if(!eq(constraints, ""), "$vd = $maskedoff",
+                        constraints#",$vd = $maskedoff");
 }
 
 // op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
-class VALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr,
+              string constraints = "">
     : RVInstVX<funct6, opv, (outs VRegOp:$vd),
-                (ins GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm),
-                opcodestr, "$vd, $rs1, $vs2$vm">;
+                (ins VRegOp:$maskedoff, GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm),
+                opcodestr, "$vd, $rs1, $vs2$vm"> {
+  let Constraints = !if(!eq(constraints, ""), "$vd = $maskedoff",
+                        constraints#",$vd = $maskedoff");
+}
 
 // op vd, vs1, vs2
 class VALUVXNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
     : RVInstVX<funct6, opv, (outs VRegOp:$vd),
                (ins VRegOp:$vs2, GPR:$rs1),
                opcodestr, "$vd, $vs2, $rs1"> {
   let vm = 1;
 }
 
 // op vd, vs2, imm, vm
-class VALUVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
+class VALUVI<bits<6> funct6, string opcodestr, string constraints = "",
+             Operand optype = simm5>
     : RVInstIVI<funct6, (outs VRegOp:$vd),
-                (ins VRegOp:$vs2, optype:$imm, VMaskOp:$vm),
-                opcodestr, "$vd, $vs2, $imm$vm">;
+                (ins VRegOp:$maskedoff, VRegOp:$vs2, optype:$imm, VMaskOp:$vm),
+                opcodestr, "$vd, $vs2, $imm$vm"> {
+  let Constraints = !if(!eq(constraints, ""), "$vd = $maskedoff",
+                        constraints#",$vd = $maskedoff");
+}
 
 // op vd, vs2, imm, v0 (without mask, use v0 as carry input)
 class VALUmVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
     : RVInstIVI<funct6, (outs VRegOp:$vd),
                 (ins VRegOp:$vs2, optype:$imm, VMV0:$v0),
                 opcodestr, "$vd, $vs2, $imm, v0"> {
   let vm = 0;
 }
 
 // op vd, vs2, imm, vm
 class VALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5>
     : RVInstIVI<funct6, (outs VRegOp:$vd),
                 (ins VRegOp:$vs2, optype:$imm),
                 opcodestr, "$vd, $vs2, $imm"> {
   let vm = 1;
 }
 
 // op vd, vs2, rs1, vm (Float)
-class VALUVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VALUVF<bits<6> funct6, RISCVVFormat opv, string opcodestr,
+             string constraints = "">
     : RVInstVX<funct6, opv, (outs VRegOp:$vd),
-                (ins VRegOp:$vs2, FPR32:$rs1, VMaskOp:$vm),
-                opcodestr, "$vd, $vs2, $rs1$vm">;
+                (ins VRegOp:$maskedoff, VRegOp:$vs2, FPR32:$rs1, VMaskOp:$vm),
+                opcodestr, "$vd, $vs2, $rs1$vm"> {
+  let Constraints = !if(!eq(constraints, ""), "$vd = $maskedoff",
+                        constraints#",$vd = $maskedoff");
+}
 
 // op vd, rs1, vs2, vm (Float) (with mask, reverse the order of rs1 and vs2)
-class VALUrVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VALUrVF<bits<6> funct6, RISCVVFormat opv, string opcodestr,
+              string constraints = "">
     : RVInstVX<funct6, opv, (outs VRegOp:$vd),
-                (ins FPR32:$rs1, VRegOp:$vs2, VMaskOp:$vm),
-                opcodestr, "$vd, $rs1, $vs2$vm">;
+                (ins VRegOp:$maskedoff, FPR32:$rs1, VRegOp:$vs2, VMaskOp:$vm),
+                opcodestr, "$vd, $rs1, $vs2$vm"> {
+  let Constraints = !if(!eq(constraints, ""), "$vd = $maskedoff",
+                        constraints#",$vd = $maskedoff");
+}
 
 // op vd, vs2, vm (use vs1 as instruction encoding)
-class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
+class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr,
+              string constraints = "">
     : RVInstV<funct6, vs1, opv, (outs VRegOp:$vd),
-               (ins VRegOp:$vs2, VMaskOp:$vm),
-               opcodestr, "$vd, $vs2$vm">;
+               (ins VRegOp:$maskedoff, VRegOp:$vs2, VMaskOp:$vm),
+               opcodestr, "$vd, $vs2$vm"> {
+  let Constraints = !if(!eq(constraints, ""), "$vd = $maskedoff",
+                        constraints#",$vd = $maskedoff");
+}
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 //===----------------------------------------------------------------------===//
 // Combination of instruction classes.
 // Use these multiclasses to define instructions more easily.
 //===----------------------------------------------------------------------===//
-multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
-  def V  : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">;
-  def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
-  def I  : VALUVI<funct6, opcodestr # "." # vw # "i", optype>;
+multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5,
+                         string constraints = "", string vw = "v"> {
+  def V  : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v", constraints>;
+  def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x", constraints>;
+  def I  : VALUVI<funct6, opcodestr # "." # vw # "i", constraints, optype>;
 }
 
 multiclass VALU_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">;
   def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
 }
 
 multiclass VALUr_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
   def V : VALUrVV<funct6, OPIVV, opcodestr # "." # vw # "v">;
   def X : VALUrVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
 }
 
-multiclass VALU_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
-  def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
-  def I  : VALUVI<funct6, opcodestr # "." # vw # "i", optype>;
+multiclass VALU_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5,
+                       string constraints = "", string vw = "v"> {
+  def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x", constraints>;
+  def I  : VALUVI<funct6, opcodestr # "." # vw # "i", constraints, optype>;
 }
 
-multiclass VALU_IV_V<string opcodestr, bits<6> funct6> {
-  def _VS  : VALUVV<funct6, OPIVV, opcodestr # ".vs">;
+multiclass VALU_IV_V<string opcodestr, bits<6> funct6, string constraints> {
+  def _VS  : VALUVV<funct6, OPIVV, opcodestr # ".vs", constraints>;
 }
 
 multiclass VALUr_IV_X<string opcodestr, bits<6> funct6, string vw = "v"> {
   def X : VALUrVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
 }
 
-multiclass VALU_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
-  def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">;
-  def X  : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">;
+multiclass VALU_MV_V_X<string opcodestr, bits<6> funct6, string constraints = "",
+                       string vw = "v"> {
+  def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v", constraints>;
+  def X  : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x", constraints>;
 }
 
 multiclass VALU_MV_V<string opcodestr, bits<6> funct6> {
   def _VS : VALUVV<funct6, OPMVV, opcodestr # ".vs">;
 }
 
 multiclass VALU_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> {
   def M : VALUVVNoVm<funct6, OPMVV, opcodestr # "." # vm # "m">;
 }
 
-multiclass VALU_MV_X<string opcodestr, bits<6> funct6, string vw = "v"> {
-  def X  : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">;
+multiclass VALU_MV_Compress<string opcodestr, bits<6> funct6, 
+                            string constraints> {
+  def M : VALUVVNoVmMaskedOff<funct6, OPMVV, opcodestr # ".vm",
+                              constraints>;
 }
 
-multiclass VALUr_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
-  def V : VALUrVV<funct6, OPMVV, opcodestr # "." # vw # "v">;
-  def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">;
+multiclass VALU_MV_X<string opcodestr, bits<6> funct6, string constraints = "",
+                     string vw = "v"> {
+  def X  : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x", constraints>;
 }
 
-multiclass VALUr_MV_X<string opcodestr, bits<6> funct6, string vw = "v"> {
-  def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">;
+multiclass VALUr_MV_V_X<string opcodestr, bits<6> funct6, string constraints = "",
+                        string vw = "v"> {
+  def V : VALUrVV<funct6, OPMVV, opcodestr # "." # vw # "v", constraints>;
+  def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x", constraints>;
 }
 
-multiclass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
-  def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>;
+multiclass VALUr_MV_X<string opcodestr, bits<6> funct6, string constraints> {
+  def X : VALUrVX<funct6, OPMVX, opcodestr # ".vx", constraints>;
+}
+
+multiclass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1,
+                       string constraints = ""> {
+  def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr, constraints>;
 }
 
 multiclass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6> {
   def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">;
   def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">;
   def IM : VALUmVI<funct6, opcodestr # ".vim">;
 }
 
 multiclass VALUm_IV_V_X<string opcodestr, bits<6> funct6> {
   def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">;
   def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">;
 }
 
 multiclass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5> {
   def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">;
   def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">;
   def I : VALUVINoVm<funct6, opcodestr # ".vi", optype>;
 }
 
 multiclass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> {
   def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">;
   def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">;
 }
 
-multiclass VALU_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> {
-  def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">;
-  def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
+multiclass VALU_FV_V_F<string opcodestr, bits<6> funct6, string constraints = "",
+                       string vw = "v"> {
+  def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v", constraints>;
+  def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f", constraints>;
 }
 
-multiclass VALU_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> {
+multiclass VALU_FV_F<string opcodestr, bits<6> funct6, string constraints = "",
+                     string vw = "v"> {
   def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
 }
 
-multiclass VALUr_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> {
-  def V : VALUrVV<funct6, OPFVV, opcodestr # "." # vw # "v">;
-  def F : VALUrVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
+multiclass VALUr_FV_V_F<string opcodestr, bits<6> funct6, string constraints = "",
+                        string vw = "v"> {
+  def V : VALUrVV<funct6, OPFVV, opcodestr # "." # vw # "v", constraints>;
+  def F : VALUrVF<funct6, OPFVF, opcodestr # "." # vw # "f", constraints>;
 }
 
-multiclass VALU_FV_V<string opcodestr, bits<6> funct6> {
-  def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">;
+multiclass VALU_FV_V<string opcodestr, bits<6> funct6, string constraints = ""> {
+  def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs", constraints>;
 }
 
-multiclass VALU_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
-  def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>;
+multiclass VALU_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1,
+                       string constraints = ""> {
+  def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr, constraints>;
 }
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
+defvar earlyclobber = "@earlyclobber $vd";
 
 let Predicates = [HasStdExtV] in {
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
 def VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp:$vtypei),
                            "vsetvli", "$rd, $rs1, $vtypei">;
 
 def VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
                          "vsetvl", "$rd, $rs1, $rs2">;

 defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
 defm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>;
 
 // Vector Widening Integer Add/Subtract
 // Refer to 11.2 Widening Vector Arithmetic Instructions
 // The destination vector register group cannot overlap a source vector
 // register group of a different element width (including the mask register
 // if masked), otherwise an illegal instruction exception is raised.
-let Constraints = "@earlyclobber $vd" in {
 let RVVConstraint = WidenV in {
-defm VWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000>;
-defm VWSUBU_V : VALU_MV_V_X<"vwsubu", 0b110010>;
-defm VWADD_V : VALU_MV_V_X<"vwadd", 0b110001>;
-defm VWSUB_V : VALU_MV_V_X<"vwsub", 0b110011>;
+defm VWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000, earlyclobber>;
+defm VWSUBU_V : VALU_MV_V_X<"vwsubu", 0b110010, earlyclobber>;
+defm VWADD_V : VALU_MV_V_X<"vwadd", 0b110001, earlyclobber>;
+defm VWSUB_V : VALU_MV_V_X<"vwsub", 0b110011, earlyclobber>;
 } // RVVConstraint = WidenV
 // Set earlyclobber for following instructions for second and mask operands.
 // This has the downside that the earlyclobber constraint is too coarse and
 // will impose unnecessary restrictions by not allowing the destination to
 // overlap with the first (wide) operand.
 let RVVConstraint = WidenW in {
-defm VWADDU_W : VALU_MV_V_X<"vwaddu", 0b110100, "w">;
-defm VWSUBU_W : VALU_MV_V_X<"vwsubu", 0b110110, "w">;
-defm VWADD_W : VALU_MV_V_X<"vwadd", 0b110101, "w">;
-defm VWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">;
+defm VWADDU_W : VALU_MV_V_X<"vwaddu", 0b110100, earlyclobber, "w">;
+defm VWSUBU_W : VALU_MV_V_X<"vwsubu", 0b110110, earlyclobber, "w">;
+defm VWADD_W : VALU_MV_V_X<"vwadd", 0b110101, earlyclobber, "w">;
+defm VWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, earlyclobber, "w">;
 } // RVVConstraint = WidenW
-} // Constraints = "@earlyclobber $vd"
 
 def : InstAlias<"vwcvt.x.x.v $vd, $vs$vm",
                 (VWADD_VX VRegOp:$vd, VRegOp:$vs, X0, VMaskOp:$vm)>;
 def : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm",
                 (VWADDU_VX VRegOp:$vd, VRegOp:$vs, X0, VMaskOp:$vm)>;
 
 // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
 defm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>;

 defm VSRL_V : VALU_IV_V_X_I<"vsrl", 0b101000, uimm5>;
 defm VSRA_V : VALU_IV_V_X_I<"vsra", 0b101001, uimm5>;
 
 // Vector Narrowing Integer Right Shift Instructions
 // Refer to 11.3. Narrowing Vector Arithmetic Instructions
 // The destination vector register group cannot overlap the first source
 // vector register group (specified by vs2). The destination vector register
 // group cannot overlap the mask register if used, unless LMUL=1.
-let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in {
-defm VNSRL_W : VALU_IV_V_X_I<"vnsrl", 0b101100, uimm5, "w">;
-defm VNSRA_W : VALU_IV_V_X_I<"vnsra", 0b101101, uimm5, "w">;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow
+let RVVConstraint = Narrow in {
+defm VNSRL_W : VALU_IV_V_X_I<"vnsrl", 0b101100, uimm5, earlyclobber, "w">;
+defm VNSRA_W : VALU_IV_V_X_I<"vnsra", 0b101101, uimm5, earlyclobber, "w">;
+} // RVVConstraint = Narrow
 
 // Vector Integer Comparison Instructions
 defm VMSEQ_V : VALU_IV_V_X_I<"vmseq", 0b011000>;
 defm VMSNE_V : VALU_IV_V_X_I<"vmsne", 0b011001>;
 defm VMSLTU_V : VALU_IV_V_X<"vmsltu", 0b011010>;
 defm VMSLT_V : VALU_IV_V_X<"vmslt", 0b011011>;
 defm VMSLEU_V : VALU_IV_V_X_I<"vmsleu", 0b011100>;
 defm VMSLE_V : VALU_IV_V_X_I<"vmsle", 0b011101>;

 
 // Vector Integer Divide Instructions
 defm VDIVU_V : VALU_MV_V_X<"vdivu", 0b100000>;
 defm VDIV_V : VALU_MV_V_X<"vdiv", 0b100001>;
 defm VREMU_V : VALU_MV_V_X<"vremu", 0b100010>;
 defm VREM_V : VALU_MV_V_X<"vrem", 0b100011>;
 
 // Vector Widening Integer Multiply Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
-defm VWMUL_V : VALU_MV_V_X<"vwmul", 0b111011>;
-defm VWMULU_V : VALU_MV_V_X<"vwmulu", 0b111000>;
-defm VWMULSU_V : VALU_MV_V_X<"vwmulsu", 0b111010>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
+let RVVConstraint = WidenV in {
+defm VWMUL_V : VALU_MV_V_X<"vwmul", 0b111011, earlyclobber>;
+defm VWMULU_V : VALU_MV_V_X<"vwmulu", 0b111000, earlyclobber>;
+defm VWMULSU_V : VALU_MV_V_X<"vwmulsu", 0b111010, earlyclobber>;
+} // RVVConstraint = WidenV
 
 // Vector Single-Width Integer Multiply-Add Instructions
 defm VMACC_V : VALUr_MV_V_X<"vmacc", 0b101101>;
 defm VNMSAC_V : VALUr_MV_V_X<"vnmsac", 0b101111>;
 defm VMADD_V : VALUr_MV_V_X<"vmadd", 0b101001>;
 defm VNMSUB_V : VALUr_MV_V_X<"vnmsub", 0b101011>;
 
 // Vector Widening Integer Multiply-Add Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
-defm VWMACCU_V : VALUr_MV_V_X<"vwmaccu", 0b111100>;
-defm VWMACC_V : VALUr_MV_V_X<"vwmacc", 0b111101>;
-defm VWMACCSU_V : VALUr_MV_V_X<"vwmaccsu", 0b111111>;
-defm VWMACCUS_V : VALUr_MV_X<"vwmaccus", 0b111110>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
+let RVVConstraint = WidenV in {
+defm VWMACCU_V : VALUr_MV_V_X<"vwmaccu", 0b111100, earlyclobber>;
+defm VWMACC_V : VALUr_MV_V_X<"vwmacc", 0b111101, earlyclobber>;
+defm VWMACCSU_V : VALUr_MV_V_X<"vwmaccsu", 0b111111, earlyclobber>;
+defm VWMACCUS_V : VALUr_MV_X<"vwmaccus", 0b111110, earlyclobber>;
+} // RVVConstraint = WidenV
 
 // Vector Integer Merge Instructions
 defm VMERGE_V : VALUm_IV_V_X_I<"vmerge", 0b010111>;
 
 // Vector Integer Move Instructions
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1 in {
 // op vd, vs1
 def VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VRegOp:$vd),

 // Vector Single-Width Fractional Multiply with Rounding and Saturation
 defm VSMUL_V : VALU_IV_V_X<"vsmul", 0b100111>;
 
 // Vector Single-Width Scaling Shift Instructions
 defm VSSRL_V : VALU_IV_V_X_I<"vssrl", 0b101010, uimm5>;
 defm VSSRA_V : VALU_IV_V_X_I<"vssra", 0b101011, uimm5>;
 
 // Vector Narrowing Fixed-Point Clip Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in {
-defm VNCLIPU_W : VALU_IV_V_X_I<"vnclipu", 0b101110, uimm5, "w">;
-defm VNCLIP_W : VALU_IV_V_X_I<"vnclip", 0b101111, uimm5, "w">;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow
+let RVVConstraint = Narrow in {
+defm VNCLIPU_W : VALU_IV_V_X_I<"vnclipu", 0b101110, uimm5, earlyclobber, "w">;
+defm VNCLIP_W : VALU_IV_V_X_I<"vnclip", 0b101111, uimm5, earlyclobber, "w">;
+} // RVVConstraint = Narrow
 
 // Vector Single-Width Floating-Point Add/Subtract Instructions
 defm VFADD_V : VALU_FV_V_F<"vfadd", 0b000000>;
 defm VFSUB_V : VALU_FV_V_F<"vfsub", 0b000010>;
 defm VFRSUB_V : VALU_FV_F<"vfrsub", 0b100111>;
 
 // Vector Widening Floating-Point Add/Subtract Instructions
-let Constraints = "@earlyclobber $vd" in {
 let RVVConstraint = WidenV in {
-defm VFWADD_V : VALU_FV_V_F<"vfwadd", 0b110000>;
-defm VFWSUB_V : VALU_FV_V_F<"vfwsub", 0b110010>;
+defm VFWADD_V : VALU_FV_V_F<"vfwadd", 0b110000, earlyclobber>;
+defm VFWSUB_V : VALU_FV_V_F<"vfwsub", 0b110010, earlyclobber>;
 } // RVVConstraint = WidenV
 // Set earlyclobber for following instructions for second and mask operands.
 // This has the downside that the earlyclobber constraint is too coarse and
 // will impose unnecessary restrictions by not allowing the destination to
 // overlap with the first (wide) operand.
 let RVVConstraint = WidenW in {
-defm VFWADD_W : VALU_FV_V_F<"vfwadd", 0b110100, "w">;
-defm VFWSUB_W : VALU_FV_V_F<"vfwsub", 0b110110, "w">;
+defm VFWADD_W : VALU_FV_V_F<"vfwadd", 0b110100, earlyclobber, "w">;
+defm VFWSUB_W : VALU_FV_V_F<"vfwsub", 0b110110, earlyclobber, "w">;
 } // RVVConstraint = WidenW
-} // Constraints = "@earlyclobber $vd"
 
 // Vector Single-Width Floating-Point Multiply/Divide Instructions
 defm VFMUL_V : VALU_FV_V_F<"vfmul", 0b100100>;
 defm VFDIV_V : VALU_FV_V_F<"vfdiv", 0b100000>;
 defm VFRDIV_V : VALU_FV_F<"vfrdiv", 0b100001>;
 
 // Vector Widening Floating-Point Multiply
-let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
-defm VFWMUL_V : VALU_FV_V_F<"vfwmul", 0b111000>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
+let RVVConstraint = WidenV in {
+defm VFWMUL_V : VALU_FV_V_F<"vfwmul", 0b111000, earlyclobber>;
+} // RVVConstraint = WidenV
 
 // Vector Single-Width Floating-Point Fused Multiply-Add Instructions
 defm VFMACC_V : VALUr_FV_V_F<"vfmacc", 0b101100>;
 defm VFNMACC_V : VALUr_FV_V_F<"vfnmacc", 0b101101>;
 defm VFMSAC_V : VALUr_FV_V_F<"vfmsac", 0b101110>;
 defm VFNMSAC_V : VALUr_FV_V_F<"vfnmsac", 0b101111>;
 defm VFMADD_V : VALUr_FV_V_F<"vfmadd", 0b101000>;
 defm VFNMADD_V : VALUr_FV_V_F<"vfnmadd", 0b101001>;
 defm VFMSUB_V : VALUr_FV_V_F<"vfmsub", 0b101010>;
 defm VFNMSUB_V : VALUr_FV_V_F<"vfnmsub", 0b101011>;
 
 // Vector Widening Floating-Point Fused Multiply-Add Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
-defm VFWMACC_V : VALUr_FV_V_F<"vfwmacc", 0b111100>;
-defm VFWNMACC_V : VALUr_FV_V_F<"vfwnmacc", 0b111101>;
-defm VFWMSAC_V : VALUr_FV_V_F<"vfwmsac", 0b111110>;
-defm VFWNMSAC_V : VALUr_FV_V_F<"vfwnmsac", 0b111111>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
+let RVVConstraint = WidenV in {
+defm VFWMACC_V : VALUr_FV_V_F<"vfwmacc", 0b111100, earlyclobber>;
+defm VFWNMACC_V : VALUr_FV_V_F<"vfwnmacc", 0b111101, earlyclobber>;
+defm VFWMSAC_V : VALUr_FV_V_F<"vfwmsac", 0b111110, earlyclobber>;
+defm VFWNMSAC_V : VALUr_FV_V_F<"vfwnmsac", 0b111111, earlyclobber>;
+} // RVVConstraint = WidenV
 
 // Vector Floating-Point Square-Root Instruction
 defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b100011, 0b00000>;
 
 // Vector Floating-Point MIN/MAX Instructions
 defm VFMIN_V : VALU_FV_V_F<"vfmin", 0b000100>;
 defm VFMAX_V : VALU_FV_V_F<"vfmax", 0b000110>;
 

 
 // Single-Width Floating-Point/Integer Type-Convert Instructions
 defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b100010, 0b00000>;
 defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b100010, 0b00001>;
 defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b100010, 0b00010>;
 defm VFCVT_F_X_V : VALU_FV_VS2<"vfcvt.f.x.v", 0b100010, 0b00011>;
 
 // Widening Floating-Point/Integer Type-Convert Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt in {
-defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b100010, 0b01000>;
-defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b100010, 0b01001>;
-defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b100010, 0b01010>;
-defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b100010, 0b01011>;
-defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b100010, 0b01100>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt
+let RVVConstraint = WidenCvt in {
+defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b100010, 0b01000, earlyclobber>;
+defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b100010, 0b01001, earlyclobber>;
+defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b100010, 0b01010, earlyclobber>;
+defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b100010, 0b01011, earlyclobber>;
+defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b100010, 0b01100, earlyclobber>;
+} // RVVConstraint = WidenCvt
 
 // Narrowing Floating-Point/Integer Type-Convert Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in {
-defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b100010, 0b10000>;
-defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b100010, 0b10001>;
-defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b100010, 0b10010>;
-defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b100010, 0b10011>;
-defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b100010, 0b10100>;
-defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b100010, 0b10101>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow
+let RVVConstraint = NarrowCvt in {
+defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b100010, 0b10000, earlyclobber>;
+defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b100010, 0b10001, earlyclobber>;
+defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b100010, 0b10010, earlyclobber>;
+defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b100010, 0b10011, earlyclobber>;
+defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b100010, 0b10100, earlyclobber>;
+defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b100010, 0b10101, earlyclobber>;
+} // RVVConstraint = NarrowCvt
 
 // Vector Single-Width Integer Reduction Instructions
 defm VREDSUM : VALU_MV_V<"vredsum", 0b000000>;
 defm VREDMAXU : VALU_MV_V<"vredmaxu", 0b000110>;
 defm VREDMAX : VALU_MV_V<"vredmax", 0b000111>;
 defm VREDMINU : VALU_MV_V<"vredminu", 0b000100>;
 defm VREDMIN : VALU_MV_V<"vredmin", 0b000101>;
 defm VREDAND : VALU_MV_V<"vredand", 0b000001>;
 defm VREDOR : VALU_MV_V<"vredor", 0b000010>;
 defm VREDXOR : VALU_MV_V<"vredxor", 0b000011>;
 
 // Vector Widening Integer Reduction Instructions
-let Constraints = "@earlyclobber $vd" in {
 // Set earlyclobber for following instructions for second and mask operands.
 // This has the downside that the earlyclobber constraint is too coarse and
 // will impose unnecessary restrictions by not allowing the destination to
 // overlap with the first (wide) operand.
-defm VWREDSUMU : VALU_IV_V<"vwredsumu", 0b110000>;
-defm VWREDSUM : VALU_IV_V<"vwredsum", 0b110001>;
-} // Constraints = "@earlyclobber $vd"
+defm VWREDSUMU : VALU_IV_V<"vwredsumu", 0b110000, earlyclobber>;
+defm VWREDSUM : VALU_IV_V<"vwredsum", 0b110001, earlyclobber>;
 
 // Vector Single-Width Floating-Point Reduction Instructions
 defm VFREDOSUM : VALU_FV_V<"vfredosum", 0b000011>;
 defm VFREDSUM : VALU_FV_V<"vfredsum", 0b000001>;
 defm VFREDMAX : VALU_FV_V<"vfredmax", 0b000111>;
 defm VFREDMIN : VALU_FV_V<"vfredmin", 0b000101>;
 
 // Vector Widening Floating-Point Reduction Instructions
-let Constraints = "@earlyclobber $vd" in {
 // Set earlyclobber for following instructions for second and mask operands.
 // This has the downside that the earlyclobber constraint is too coarse and
 // will impose unnecessary restrictions by not allowing the destination to
 // overlap with the first (wide) operand.
-defm VFWREDOSUM : VALU_FV_V<"vfwredosum", 0b110011>;
-defm VFWREDSUM : VALU_FV_V<"vfwredsum", 0b110001>;
-} // Constraints = "@earlyclobber $vd"
+defm VFWREDOSUM : VALU_FV_V<"vfwredosum", 0b110011, earlyclobber>;
+defm VFWREDSUM : VALU_FV_V<"vfwredsum", 0b110001, earlyclobber>;
 
 // Vector Mask-Register Logical Instructions
 defm VMAND_M : VALU_MV_Mask<"vmand", 0b011001, "m">;
 defm VMNAND_M : VALU_MV_Mask<"vmnand", 0b011101, "m">;
 defm VMANDNOT_M : VALU_MV_Mask<"vmandnot", 0b011000, "m">;
 defm VMXOR_M : VALU_MV_Mask<"vmxor", 0b011011, "m">;
 defm VMOR_M : VALU_MV_Mask<"vmor", 0b011010, "m">;
 defm VMNOR_M : VALU_MV_Mask<"vmnor", 0b011110, "m">;
 defm VMORNOT_M : VALU_MV_Mask<"vmornot", 0b011100, "m">;
 defm VMXNOR_M : VALU_MV_Mask<"vmxnor", 0b011111, "m">;
 

 
 // vmsif.m set-including-first mask bit
 defm VMSIF_M : VALU_MV_VS2<"vmsif.m", 0b010100, 0b00011>;
 
 // vmsof.m set-only-first mask bit
 defm VMSOF_M : VALU_MV_VS2<"vmsof.m", 0b010100, 0b00010>;
 
 // Vector Iota Instruction
-let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in {
-defm VIOTA_M : VALU_MV_VS2<"viota.m", 0b010100, 0b10000>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota
+let RVVConstraint = Iota in {
+defm VIOTA_M : VALU_MV_VS2<"viota.m", 0b010100, 0b10000, earlyclobber>;
+} // RVVConstraint = Iota
 
 // Vector Element Index Instruction
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VRegOp:$vd),
                       (ins VMaskOp:$vm), "vid.v", "$vd$vm"> {
   let vs2 = 0;
 }
 

 def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd),
                       (ins VRegOp:$vs2), "vfmv.f.s", "$vd, $vs2">;
 def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VRegOp:$vd),
                       (ins FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">;
 
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1
 
 // Vector Slide Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
-defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
+let RVVConstraint = SlideUp in {
+defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5, earlyclobber>;
+} // RVVConstraint = SlideUp
 defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>;
 
-let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
-defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
+let RVVConstraint = SlideUp in {
+defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110, earlyclobber>;
+} // RVVConstraint = SlideUp
 defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>;
 
 // Vector Register Gather Instruction
-let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
-defm VRGATHER_V : VALU_IV_V_X_I<"vrgather", 0b001100, uimm5>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather
+let RVVConstraint = Vrgather in {
+defm VRGATHER_V : VALU_IV_V_X_I<"vrgather", 0b001100, uimm5, earlyclobber>;
+} // RVVConstraint = Vrgather
 
 // Vector Compress Instruction
-let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
-defm VCOMPRESS_V : VALU_MV_Mask<"vcompress", 0b010111>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
+let RVVConstraint = Vcompress in {
+defm VCOMPRESS_V : VALU_MV_Compress<"vcompress", 0b010111, earlyclobber>;
+} // RVVConstraint = Vcompress
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 foreach nf = [1, 2, 4, 8] in {
   def VMV#nf#R_V  : RVInstV<0b100111, !add(nf, -1), OPIVI, (outs VRegOp:$vd),
                             (ins VRegOp:$vs2), "vmv" # nf # "r.v",
                             "$vd, $vs2"> {
     let Uses = [];
     let vm = 1;
   }
 }
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 } // Predicates = [HasStdExtV]