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Differential D73414

AMDGPU/GlobalISel: Do a better job splitting 64-bit G_SEXT_INREG
ClosedPublic

Authored by arsenm on Jan 25 2020, 6:33 AM.

Details

Reviewers
nhaehnle
kerbowa
cdevadas
Summary

We don't need to expand to full shifts for the > 32-bit case. This
just switches to a sext_inreg of the high half.

Diff Detail

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
67 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
57 lines

Diff 240374

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 1,829 Lines • ▼ Show 20 Lines if (Ty == S16) {
// FIXME: This is relying on widenScalar leaving MI in place. // FIXME: This is relying on widenScalar leaving MI in place.
lowerScalarMinMax(B, MI); lowerScalarMinMax(B, MI);
} else } else
lowerScalarMinMax(B, MI); lowerScalarMinMax(B, MI);
return; return;
} }
case AMDGPU::G_SEXT_INREG: { case AMDGPU::G_SEXT_INREG: {
const RegisterBank *SrcBank = SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1));
OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; if (SrcRegs.empty())
break; // Nothing to repair
// We can directly handle all 64-bit cases with s_bfe_i64.
if (SrcBank == &AMDGPU::SGPRRegBank)
break;
const LLT S32 = LLT::scalar(32); const LLT S32 = LLT::scalar(32);
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
LLT Ty = MRI.getType(DstReg);
if (Ty == S32)
break;
MachineIRBuilder B(MI); MachineIRBuilder B(MI);
ApplyRegBankMapping O(*this, MRI, &AMDGPU::VGPRRegBank); ApplyRegBankMapping O(*this, MRI, &AMDGPU::VGPRRegBank);
GISelObserverWrapper Observer(&O); GISelObserverWrapper Observer(&O);
B.setChangeObserver(Observer); B.setChangeObserver(Observer);
int Amt = MI.getOperand(2).getImm();
if (Amt <= 32) {
// Don't use LegalizerHelper's narrowScalar. It produces unwanted G_SEXTs // Don't use LegalizerHelper's narrowScalar. It produces unwanted G_SEXTs
// we would need to further expand, and doesn't let us directly set the // we would need to further expand, and doesn't let us directly set the
// result registers. // result registers.
SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0)); SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0));
SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1));
if (SrcRegs.empty()) int Amt = MI.getOperand(2).getImm();
split64BitValueForMapping(B, SrcRegs, S32, SrcReg); if (Amt <= 32) {
// Extend in the low bits and propagate the sign bit to the high half.
auto ShiftAmt = B.buildConstant(S32, 31);
if (Amt == 32) { if (Amt == 32) {
// The low bits are unchanged.
B.buildCopy(DstRegs[0], SrcRegs[0]); B.buildCopy(DstRegs[0], SrcRegs[0]);
B.buildAShr(DstRegs[1], DstRegs[0], ShiftAmt);
} else { } else {
// Extend in the low bits and propagate the sign bit to the high half.
B.buildSExtInReg(DstRegs[0], SrcRegs[0], Amt); B.buildSExtInReg(DstRegs[0], SrcRegs[0], Amt);
B.buildAShr(DstRegs[1], DstRegs[0], ShiftAmt);
} }
B.buildAShr(DstRegs[1], DstRegs[0], B.buildConstant(S32, 31));
} else { } else {
assert(empty(OpdMapper.getVRegs(0)) && empty(OpdMapper.getVRegs(1))); // The low bits are unchanged, and extend in the high bits.
const LLT S64 = LLT::scalar(64); B.buildCopy(DstRegs[0], SrcRegs[0]);
// This straddles two registers. Expand with 64-bit shifts. B.buildSExtInReg(DstRegs[1], DstRegs[0], Amt - 32);
auto ShiftAmt = B.buildConstant(S32, 64 - Amt);
auto Shl = B.buildShl(S64, SrcReg, ShiftAmt);
B.buildAShr(DstReg, Shl, ShiftAmt);
} }
Register DstReg = MI.getOperand(0).getReg();
MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank); MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank);
MI.eraseFromParent(); MI.eraseFromParent();
return; return;
} }
case AMDGPU::G_SEXT: case AMDGPU::G_SEXT:
case AMDGPU::G_ZEXT: { case AMDGPU::G_ZEXT: {
Register SrcReg = MI.getOperand(1).getReg(); Register SrcReg = MI.getOperand(1).getReg();
LLT SrcTy = MRI.getType(SrcReg); LLT SrcTy = MRI.getType(SrcReg);
▲ Show 20 Lines • Show All 1,056 Lines • ▼ Show 20 Lines case AMDGPU::G_TRUNC: {
OpdsMapping[0] = DstSize == 1 && Bank != AMDGPU::SGPRRegBankID ? OpdsMapping[0] = DstSize == 1 && Bank != AMDGPU::SGPRRegBankID ?
AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, DstSize) : AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, DstSize) :
AMDGPU::getValueMapping(Bank, DstSize); AMDGPU::getValueMapping(Bank, DstSize);
OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize); OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize);
break; break;
} }
case AMDGPU::G_ZEXT: case AMDGPU::G_ZEXT:
case AMDGPU::G_SEXT: case AMDGPU::G_SEXT:
case AMDGPU::G_ANYEXT: { case AMDGPU::G_ANYEXT:
case AMDGPU::G_SEXT_INREG: {
Register Dst = MI.getOperand(0).getReg(); Register Dst = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg(); Register Src = MI.getOperand(1).getReg();
unsigned DstSize = getSizeInBits(Dst, MRI, *TRI); unsigned DstSize = getSizeInBits(Dst, MRI, *TRI);
unsigned SrcSize = getSizeInBits(Src, MRI, *TRI); unsigned SrcSize = getSizeInBits(Src, MRI, *TRI);
unsigned DstBank; unsigned DstBank;
const RegisterBank *SrcBank = getRegBank(Src, MRI, *TRI); const RegisterBank *SrcBank = getRegBank(Src, MRI, *TRI);
assert(SrcBank); assert(SrcBank);
Show All 14 Lines if (MI.getOpcode() == AMDGPU::G_ANYEXT) {
// Scalar extend can use 64-bit BFE, but VGPRs require extending to // Scalar extend can use 64-bit BFE, but VGPRs require extending to
// 32-bits, and then to 64. // 32-bits, and then to 64.
OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(DstBank, DstSize); OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(DstBank, DstSize);
OpdsMapping[1] = AMDGPU::getValueMappingSGPR64Only(SrcBank->getID(), OpdsMapping[1] = AMDGPU::getValueMappingSGPR64Only(SrcBank->getID(),
SrcSize); SrcSize);
} }
break; break;
} }
case AMDGPU::G_SEXT_INREG: {
Register Dst = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg();
Register Amt = MI.getOperand(2).getImm();
unsigned Size = getSizeInBits(Dst, MRI, *TRI);
unsigned BankID = getRegBank(Src, MRI, *TRI)->getID();
if (Amt <= 32) {
OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(BankID, Size);
} else {
// If we need to expand a 64 bit for the VALU, this will straddle two
// registers. Just expand this with 64-bit shifts.
OpdsMapping[0] = AMDGPU::getValueMapping(BankID, Size);
}
OpdsMapping[1] = OpdsMapping[0];
break;
}
case AMDGPU::G_FCMP: { case AMDGPU::G_FCMP: {
unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI); unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1);
OpdsMapping[1] = nullptr; // Predicate Operand. OpdsMapping[1] = nullptr; // Predicate Operand.
OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size); OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
break; break;
▲ Show 20 Lines • Show All 559 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir

Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: sext_inreg_v_s64_1 ; CHECK-LABEL: name: sext_inreg_v_s64_1
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[UV]], 1 ; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[UV]], 1
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32) ; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SEXT_INREG]](s32), [[ASHR]](s32) ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SEXT_INREG]](s32), [[ASHR]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s64) ; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 1 %1:_(s64) = G_SEXT_INREG %0, 1
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: sext_inreg_v_s64_31 name: sext_inreg_v_s64_31
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: sext_inreg_v_s64_31 ; CHECK-LABEL: name: sext_inreg_v_s64_31
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[UV]], 31 ; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[UV]], 31
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32) ; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SEXT_INREG]](s32), [[ASHR]](s32) ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SEXT_INREG]](s32), [[ASHR]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s64) ; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 31 %1:_(s64) = G_SEXT_INREG %0, 31
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: sext_inreg_v_s64_32 name: sext_inreg_v_s64_32
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: sext_inreg_v_s64_32 ; CHECK-LABEL: name: sext_inreg_v_s64_32
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32) ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[COPY1]], [[C]](s32) ; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[COPY1]], [[C]](s32)
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[ASHR]](s32) ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[ASHR]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s64) ; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 32 %1:_(s64) = G_SEXT_INREG %0, 32
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: sext_inreg_v_s64_33 name: sext_inreg_v_s64_33
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: sext_inreg_v_s64_33 ; CHECK-LABEL: name: sext_inreg_v_s64_33
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31 ; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[SHL:%[0-9]+]]:vgpr(s64) = G_SHL [[COPY]], [[C]](s32) ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
; CHECK: [[ASHR:%[0-9]+]]:vgpr(s64) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[COPY1]], 1
; CHECK: S_ENDPGM 0, implicit [[ASHR]](s64) ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[SEXT_INREG]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 33 %1:_(s64) = G_SEXT_INREG %0, 33
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
---
name: sext_inreg_v_s64_35
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: sext_inreg_v_s64_35
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[COPY1]], 3
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[SEXT_INREG]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 35
S_ENDPGM 0, implicit %1
...
---
name: sext_inreg_v_s64_63
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: sext_inreg_v_s64_63
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[COPY1]], 31
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[SEXT_INREG]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 63
S_ENDPGM 0, implicit %1
...