[ISEL][ARM][AARCH64] Tracking simple parameter forwarding registers

[NikolaPrica]

Summary

Support for tracking registers that forward function parameters into the following function frame. For now we only support cases when parameter is forwarded through single register.

[vsk]

Thanks, I think this is a great starting point. LGTM.

test/DebugInfo/ARM/call-site-info-output.ll

14

Could hardcoding the offset be brittle?

[NikolaPrica]

Replacing hard-coded test case values with regex.

@vsk Thanks for the review!

[NikolaPrica]

Rebase:

-AArch64ISEL part is changed in order do avoid tracking cases when two or more parameters can be in same register.

[NikolaPrica]

lib/Target/AArch64/AArch64ISelLowering.cpp

3841

@t.p.northover can you take a look at this part of code since I've just rebased on top of your changes?

lib/Target/AArch64/AArch64ISelLowering.cpp

AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
   SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
   SDValue Chain = CLI.Chain;
   SDValue Callee = CLI.Callee;
   bool &IsTailCall = CLI.IsTailCall;
   CallingConv::ID CallConv = CLI.CallConv;
   bool IsVarArg = CLI.IsVarArg;
 
   MachineFunction &MF = DAG.getMachineFunction();
+  MachineFunction::CallSiteInfo CSInfo;
   bool IsThisReturn = false;
 
   AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
   bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
   bool IsSibCall = false;
 
   if (IsTailCall) {
     // Check if it's really possible to do a tail call.
if (VA.isRegLoc()) {
       if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
           Outs[0].VT == MVT::i64) {
         assert(VA.getLocVT() == MVT::i64 &&
                "unexpected calling convention register assignment");
         assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
                "unexpected use of 'returned'");
         IsThisReturn = true;
       }
+      const TargetOptions &Options = DAG.getTarget().Options;
+      if (Options.EnableDebugEntryValues)
+        CSInfo.emplace_back(VA.getLocReg(), i);
       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
     } else {
       assert(VA.isMemLoc());
 
       SDValue DstAddr;
       MachinePointerInfo DstInfo;
 
       // FIXME: This works on big-endian for composite byvals, which are the
if (InFlag.getNode())
     Ops.push_back(InFlag);
 
   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
 
   // If we're doing a tall call, use a TC_RETURN here rather than an
   // actual call instruction.
   if (IsTailCall) {
     MF.getFrameInfo().setHasTailCall();
-    return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
+    SDValue Ret = DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
+    DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
+    return Ret;
   }
 
   // Returns a chain and a flag for retval copy to use.
   Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
   InFlag = Chain.getValue(1);
+  DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
 
   uint64_t CalleePopBytes =
       DoesCalleeRestoreStack(CallConv, TailCallOpt) ? alignTo(NumBytes, 16) : 0;
 
   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
                              DAG.getIntPtrConstant(CalleePopBytes, DL, true),
                              InFlag, DL);
   if (!Ins.empty())

lib/Target/ARM/ARMExpandPseudoInsts.cpp

case ARM::TCRETURNri: {
                 TII.get(Opcode))
             .addReg(JumpTarget.getReg(), RegState::Kill);
       }
 
       auto NewMI = std::prev(MBBI);
       for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
         NewMI->addOperand(MBBI->getOperand(i));
 
-      // Delete the pseudo instruction TCRETURN.
+
+      // Update call site info and delete the pseudo instruction TCRETURN.
+      MBB.getParent()->updateCallSiteInfo(&MI, &*NewMI);
       MBB.erase(MBBI);
+
       MBBI = NewMI;
       return true;
     }
     case ARM::VMOVScc:
     case ARM::VMOVDcc: {
       unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
               MI.getOperand(1).getReg())
case ARM::TPsoft: {
                       TII->get(Thumb ? ARM::tBL : ARM::BL));
         if (Thumb)
           MIB.add(predOps(ARMCC::AL));
         MIB.addExternalSymbol("__aeabi_read_tp", 0);
       }
 
       MIB.cloneMemRefs(MI);
       TransferImpOps(MI, MIB, MIB);
+      MI.getMF()->updateCallSiteInfo(&MI, &*MIB);
       MI.eraseFromParent();
       return true;
     }
     case ARM::tLDRpci_pic:
     case ARM::t2LDRpci_pic: {
       unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
         ? ARM::tLDRpci : ARM::t2LDRpci;
       Register DstReg = MI.getOperand(0).getReg();

lib/Target/ARM/ARMISelLowering.cpp

ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
   SDValue Chain                         = CLI.Chain;
   SDValue Callee                        = CLI.Callee;
   bool &isTailCall                      = CLI.IsTailCall;
   CallingConv::ID CallConv              = CLI.CallConv;
   bool doesNotRet                       = CLI.DoesNotReturn;
   bool isVarArg                         = CLI.IsVarArg;
 
   MachineFunction &MF = DAG.getMachineFunction();
+  MachineFunction::CallSiteInfo CSInfo;
   bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
   bool isThisReturn = false;
   auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
   bool PreferIndirect = false;
 
   // Disable tail calls if they're not supported.
   if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
     isTailCall = false;
if (VA.needsCustom()) {
       if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
           Outs[0].VT == MVT::i32) {
         assert(VA.getLocVT() == MVT::i32 &&
                "unexpected calling convention register assignment");
         assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
                "unexpected use of 'returned'");
         isThisReturn = true;
       }
+      const TargetOptions &Options = DAG.getTarget().Options;
+      if (Options.EnableDebugEntryValues)
+        CSInfo.emplace_back(VA.getLocReg(), i);
       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
     } else if (isByVal) {
       assert(VA.isMemLoc());
       unsigned offset = 0;
 
       // True if this byval aggregate will be split between registers
       // and memory.
       unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
   }
 
   if (InFlag.getNode())
     Ops.push_back(InFlag);
 
   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
   if (isTailCall) {
     MF.getFrameInfo().setHasTailCall();
-    return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
+    SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
+    DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
+    return Ret;
   }
 
   // Returns a chain and a flag for retval copy to use.
   Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
   InFlag = Chain.getValue(1);
+  DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
 
   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
                              DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
   if (!Ins.empty())
     InFlag = Chain.getValue(1);
 
   // Handle result values, copying them out of physregs into vregs that we
   // return.

test/DebugInfo/AArch64/call-site-info-output.ll

+; RUN: llc -mtriple aarch64-linux-gnu -debug-entry-values %s -o - -stop-before=finalize-isel | FileCheck %s
+; Verify that Selection DAG knows how to recognize simple function parameter forwarding registers.
+; Produced from:
+; extern int fn1(int,int,int);
+; int fn2(int a, int b, int c) {
+;   int local = fn1(a+b, c, 10);
+;   if (local > 10)
+;     return local + 10;
+;   return local;
+; }
+; clang -g -O2 -target aarch64-linux-gnu -S -emit-llvm %s
+; CHECK: callSites:
+; CHECK-NEXT:   - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK-NEXT:       - { arg: 0, reg: '$w0' }
+; CHECK-NEXT:       - { arg: 1, reg: '$w1' }
+; CHECK-NEXT:       - { arg: 2, reg: '$w2' } }
+
+; ModuleID = 'call-site-info-output.c'
+source_filename = "call-site-info-output.c"
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define dso_local i32 @fn2(i32 %a, i32 %b, i32 %c) local_unnamed_addr{
+entry:
+  %add = add nsw i32 %b, %a
+  %call = tail call i32 @fn1(i32 %add, i32 %c, i32 10)
+  %cmp = icmp sgt i32 %call, 10
+  %add1 = add nsw i32 %call, 10
+  %retval.0 = select i1 %cmp, i32 %add1, i32 %call
+  ret i32 %retval.0
+}
+
+declare dso_local i32 @fn1(i32, i32, i32) local_unnamed_addr
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 10.0.0"}

test/DebugInfo/ARM/call-site-info-output.ll

+; RUN: llc -mtriple arm-linux-gnu -debug-entry-values %s -o - -stop-before=finalize-isel | FileCheck %s
+; Verify that Selection DAG knows how to recognize simple function parameter forwarding registers.
+; Produced from:
+; extern int fn1(int,int,int);
+; int fn2(int a, int b, int c) {
+;   int local = fn1(a+b, c, 10);
+;   if (local > 10)
+;     return local + 10;
+;   return local;
+; }
+; clang -g -O2 -target arm-linux-gnu -S -emit-llvm %s
+; CHECK: callSites:
+; CHECK-NEXT:   - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK-NEXT:       - { arg: 0, reg: '$r0' }
+; CHECK-NEXT:       - { arg: 1, reg: '$r1' }
+; CHECK-NEXT:       - { arg: 2, reg: '$r2' } }
+
+; ModuleID = 'call-site-info-output.c'
+source_filename = "call-site-info-output.c"
+target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv4t-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define dso_local arm_aapcscc i32 @fn2(i32 %a, i32 %b, i32 %c) {
+entry:
+  %add = add nsw i32 %b, %a
+  %call = tail call arm_aapcscc i32 @fn1(i32 %add, i32 %c, i32 10)
+  %cmp = icmp sgt i32 %call, 10
+  %add1 = select i1 %cmp, i32 %c, i32 0
+  %retval.0 = add nsw i32 %add1, %call
+  ret i32 %retval.0
+}
+
+declare dso_local arm_aapcscc i32 @fn1(i32, i32, i32) local_unnamed_addr
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 10.0.0"}