[PPC] Expand ISEL instruction into if-then-else sequence

[jtony]

Summary

This patch will expand the isel instruction into an if-then-else sequence.
The expansion is done late, after instruction scheduling, as the isel instruction does terminate basic blocks, allowing for larger scopes for scheduling.

There are still some performance problems that I'm investigating. Specifically, there is a significant slowdown in SPEC2k6 hmmer (roughly 40%).
So, there will likely be another version of this patch necessary before committing. However, any feedback on the current patch is appreciated.

[nemanjai]

lib/Target/PowerPC/PPCExpandISEL.cpp

35

I think it's clearer if you explicitly initialize this to false (presumably that's the default).

130

The doxygen comment for this function states that we want to expand the isel instructions on Power7 and Power8 processors but this actually relies on different conditions. I am not entirely clear on whether the SVR4 ABI only applies on those processors, but the conditions seem to be mismatched.

144

Is there any concern that there may be some [pathological] cases where this would end up copying an unreasonably large vector (i.e. if the BB contains many isel instructions and has heap-allocated storage)?

149

Should this whole function be in an
#ifndef _NDEBUG
block? And of course the call.

165

Minor nit: The block numbers are dumped as "BB#<num>" above, but here they're dumped as "block <num>".

183

Not that this is likely to ever change, but perhaps for the sake of consistency this assert should be:

assert(isISEL(MI) && "Expecting an ISEL instruction");

188

Again, when the only statement[s] in the loop will be compiled out without asserts, I think the whole loop should be in a DEBUG() block. Mind you, I don't fully follow why we're dumping the operands separately after we've already dumped the MachineInstr - especially since they'll be dumped again below (Dest, TrueValue, False, ConditionRegister).

213

Does this cast work (i.e. converting an iterator to a pointer)?

222

I don't know the details of this so this may just be a ridiculous suggestion, but will this not assert if the isel is the very last instruction before returning from the function? Perhaps that would be impossible because the branch-to-link-register would be last. Except perhaps if this is a "noreturn" function (in which case, I'm not sure why there'd be an isel at the end).

223

Minor nit: I think that "succ_it" (although a cool variable name :)) breaks with variable naming conventions (camel vs. underscores).

267

Probably forgot to delete this line. Same applies to similar lines below.

268

I think for both cases where you add this instruction, a check should be performed whether the two registers are the same. If they are, you don't need the instruction. Also, just out of curiosity, is there any significance to the choice to use ADDI vs. OR (which I think is what we normally use for reg-to-reg copies)?

272

This is probably not needed since you're not saving a pointer to the instruction. Same applies below.

285

I wonder if there's anything available at this stage in the compilation that can be used for some heuristics to choose which block we should branch to and which should be a fall-through block?

[jtony]

Generally, the ISEL is expanded into if-then-else sequence, in some cases (like when the destination register is the same with the true or false value register), it may just be expanded into just the if or else sequence. This patches does these further optimizations compare to the previous patch by Kit Barton.

[nemanjai]

lib/Target/PowerPC/PPCExpandISEL.cpp

86

This is just not true. Please see the comment below at the definition of the function.

130

At this point, I would question the applicability of this function. We now have an option that is meant to tell the compiler to generate or not generate the instruction, but has unexpected behaviour on some platforms.
Namely, when the option is specified to be true, the compiler will generate the isel on every platform. On the other hand, when the option is specified to be false, the compiler will not generate the isel on 64-bit non-Darwin targets. This of course, may be the desired behaviour (i.e. always generate isel on 32-bit or Darwin targets), but it should be documented as such.

167

I am not in favour of naming this function the same as the other overload. The two overloads do different things - this one expands ALL isel's, the other overload expands only ONE isel. I know this is somewhat common, but I think giving this one a name that suggests this plurality aids readability of the code.

177

I assume you have tested this, but I am just curious if dumping this iterator without dereferencing it prints the actual MI.

196

These names don't conform to the naming convention (variables start with a capital letter).

200

This is a very long function. I wonder if it would be a little easier to follow the code if it was split into (for example):

PPCExpandISEL::expandISELBothBlocks()
PPCExpandISEL::expandISELNoTrueBlock()
PPCExpandISEL::expandISELNoFalseBlock()

Or if that would lead to code duplication, perhaps just move all the code that sets up the basic block layout as needed in the given situation into
PPCExpandISEL::reorganizeBlockLayout()

216

The indentation seems off here.

245

I think this should be moved up to where you select how to set Successor. Basically within that conditional statement, handle reordering the layout of the basic blocks and then move on to creating the true/false blocks as necessary.

273

I don't understand the need for this strange code layout. Namely, you have:

if (isTrueBlockRequired)
  // do true block stuff
if (isFalseBlockRequired)
  // do false block stuff
if (isTrueBlockRequired)
  // do more true block stuff
if (isFalseBlockRequired)
  // do more false block stuff
...

Why can't the code in these conditional blocks be collapsed together?

[nemanjai]

lib/Target/PowerPC/PPCExpandISEL.cpp

34

Should probably be changed to something along the lines of
Disable generating the ISEL instruction on 64-bit non-Darwin PPC targets.

185

I'm not sure it makes sense for this function to have a bool return value since it can never return false. This should likely be a void function.

303

One of these may be redundant. I think if the code is reorganized to keep things together, it will be clearer what needs to be done. What I mean is that if we group together things we do if we need a true block and group together things we do if we need a false block, the logic will be easier to follow.

[jtony]

Special case 1: If all the registers of ISEL instruction are the same, we simply remove the ISEL instruction.
Special case 2: If the input registers of the ISEL instruction are the same but different with the output register, we just replace ISEL with one unconditional copy.
Special case 3: If the true value register of the ISEL instruction is the same with the dest register, we skip the true block.
Special case 4: If the false value register of the ISEL instruction is the same with the dest register, we skip the false block.
Most general case 5: Otherwise, we expand ISEL to if-then-else.

[kbarton]

There are some things that need to get cleaned up.

lib/Target/PowerPC/PPCExpandISEL.cpp

35

Good idea. I will change this.

130

These checks are really messy right now, in my opinion.
This will enable it on all non-Darwin systems, which should include PWR7 and PWR8, regardless of endianness. I'm happy to change this if there is something more specific to use.

130

Yes, I agree with this given the new direction of the patch (continue to generate ISEL, provide a switch to disable it).
If we want to disable ISEL generation by default, we can assess whether we should add similar logic to focus it to a subset of architectures.

144

You could certainly construct such a case, but I doubt it would happen in practice.

183

Good call, done.

200

Could you please add a statistic to track the number of ISEL instructions that are removed.

223

Fixed

226

This should be done earlier, especially before (possibly) creating the NewSuccessor basic block above.
I would move this as early as possible, once all the information needed is available.

268

OR treats R0 as special (the literal value 0), while ADDI respects the contents of R0. So, if the register allocator has decided to use R0 for one of the inputs to ISEL, and you simply do an OR, you can end up with incorrect results.

272

Good point, fixed.

285

Yes, the expansion can certainly be changed. We can discuss various heuristics, if we decide we want to actually expand the ISELs. For now I'd prefer to leave this as the default until that decision has been made.

303

I agree - I think we should be able to consolidate some of this code into just two tests.

test/CodeGen/PowerPC/expand-isel.ll

2

You need to include PowerPC triple

[nemanjai]

test/CodeGen/PowerPC/expand-isel.ll

2

Yes, please do not forget this because I'm pretty sure it would break every multi-target build bot other than the PPC ones.

[nemanjai]

lib/Target/PowerPC/PPCExpandISEL.cpp

226

Yes, I'd handle the cases where you're getting rid of the ISEL without introducing new control flow first - i.e. before you start creating new control flow.

[jtony]

lib/Target/PowerPC/PPCExpandISEL.cpp

34

I reconsider this comment and realize that this ppc-gen-isel option is set to true, maybe it is better (I mean consistent with the default behavior) we use the "Enable generating the ISEL instruction"?

35

Shall we make this option visible to all users?

268

Nemanjaj already noticed the bug in the patch :-) (always use ADDI for both True and False branch, we should just use ADDI for True branch and ORI for false branch), if we have considered this comments more carefully, could avoid this bug.

303

Last time when I move around these code, it caused assertion, so I just combined a few blocks, leave some other blocks untouched. If people strongly disagree, I can try again to move these blocks around.

[hfinkel]

As a general note: I'd like to see this controlled with our existing isel toggle. In other words, take all of the existing places that call hasISEL() and hard-code them to true and then have this pass expand the isel instructions when hasISEL() is false.

There are a lot of loops here that could be range-based for loops. Please make them range-based for loops.

I've been thinking about how difficult it might be to handle the case where multiple isels use the same condition. I don't think it would be too difficult to support this: As you iterate through the isels in each block, keep track of the true block, false block and condition for the last expanded isel. If this isel has the same condition as the last one, then scan between them to make sure that nothing defines this isel's input registers in between the two isels and that this isel does not depend on the last one. If that's true, then insert the generated instructions into the blocks from the last isel instead of making new ones.

As a quick example, I'm thinking about something like this:

int foo(int a, int b, int d, int f, int g) {
  int q = g > 0 ? a : b;
  int r = g > 0 ? d : f;
  return q+r;
}

which generates code like this:

cmpwi 0, 7, 0
isel 3, 3, 4, 1
isel 12, 5, 6, 1
add 3, 3, 12
extsw 3, 3
blr

lib/Target/PowerPC/PPCExpandISEL.cpp

12

Please note here that this pass is intended to be run post-RA only.

[jtony]

Fix the bootstrap ISEl bug (should use ORI instruction rather than ADDI for the false branch) .
Update all the existing test cases that used to generate ISEL to test -ppc-gen-isel=false situation.
Address the comments in phabricator.
Update the new expand-isel.ll file according to the bug fix.

[kbarton]

In D23630#609933, @hfinkel wrote:

I've been thinking about how difficult it might be to handle the case where multiple isels use the same condition. I don't think it would be too difficult to support this: As you iterate through the isels in each block, keep track of the true block, false block and condition for the last expanded isel. If this isel has the same condition as the last one, then scan between them to make sure that nothing defines this isel's input registers in between the two isels and that this isel does not depend on the last one. If that's true, then insert the generated instructions into the blocks from the last isel instead of making new ones.

I agree this can be done, and set up the original code to make this fairly straightforward. I had hoped to make a decision about whether we want ISEL generated or not before making further improvements to this patch, but it may be better to handle this case first, as it can effect performance and thus influence the final decision regarding what the defaults for ISEL generation will be.

lib/Target/PowerPC/PPCExpandISEL.cpp

89

We can remove all uses of \brief since doxygen autobrief is now enabled by default.

[kbarton]

Need to address Hal's comments and post a subsequent patch. Thanks.

[jtony]

Support merging contiguous ISELs.

[jtony]

test/CodeGen/PowerPC/expand-contiguous-isel.ll

2

This test case is reduced from a bootstrap build bug, still very complex, I am not sure whether we want to deliver it or not.

[jtony]

The total SPEC statistics:

Number Expanded 23601

For these ISEL with same CR (just compare operand(3), it is still possible CR can be modified in between the two ISELs, and the registers used or defined by the later ISEL could also be changed) :

Number Contiguous 825
Number Non-Contiguous 2618

Also, this patch doesn't address the option comment by Hal.

[jtony]

Address the option comment from Hal. Now all the patch is complete, it address all the three comments from Hal.

[hfinkel]

Thanks for all of the updates! Some more things...

In general, our policy is that comments are complete sentences, starting with a capital letter and ending with a period (or other punctuation). Please audit all comments and adjust accordingly.

lib/Target/PowerPC/PPCExpandISEL.cpp

310

I think that, in rare circumstances, this assert would fire. It would happen if you had a block that was the last block in a function which ended with an "unreachable" and the instruction before that were an isel. I think you need to handle this case. I think that you should be able to create a .mir test case for this.

399

Don't compare with literial zero here either.

[hfinkel]

lib/Target/PowerPC/PPCExpandISEL.cpp

256

if -> If

265

You need to check against PPC::X0 and PPC::R0, not the literal 0. Please create some .mir test cases for these.

275

Do we need to reset IsTrueBlockRequired and IsFalseBlockRequired here?

281

Same here (don't compare to the literal 0).

lib/Target/PowerPC/PPCTargetMachine.cpp

420

Do you require the verifyAfter = false here? (I'm not sure why we have that for the others either). Can you test without it?

[kbarton]

lib/Target/PowerPC/PPCExpandISEL.cpp

56

You've got two different references to MachineFunction: MF here and Fn on line 60

63

Why do we need an LLVM_BB? I would have expected we're only working with MachineBasicBlocks at this point.

70

In general I don't like this approach of caching all of these intermediate values here. Given the algorithm iterates over lists of ISELs and does expansions somewhat different each time, you need to be very careful that all of these are set/reset between each iteration to ensure that the values are not stale. My previous experiences have taught me that this can be both confusing and error prone.

189

I don't see why these parameters need to references to MachineInstr *, why can't they just be references to MachineInstr?
I think the preference is to only use pointers if the value can be null for some reason. If it cannot be null, then it's better to use references.

282

insturction -> instruction

[jtony]

lib/Target/PowerPC/PPCExpandISEL.cpp

56

Good call, one of them is redundant, I removed all usage of Fn and use MF instead.

70

That's a good point, we should try to restrict the life of a variable as short as possible. Successor can be made a function scope variable while NewSuccessor can be passed around between functions.

275

We don't need to reset them, the removed ISEL isn't considered for calculating the value of IsTrueBlockRequired and IsFalseBlockRequired.

[nemanjai]

lib/Target/PowerPC/PPCExpandISEL.cpp

12

This wasn't addressed. I think it's important to note that since we need to have physical registers here.

37

This comment is no longer accurate.

109

Why does this need to be public?

121

Fragment. Please revise this comment to complete sentences and to account for the new semantics (i.e. interaction with -mno-isel/-mattr=-isel).

133

I would move this down. We don't want to dump out an entire MachineFunction if we're not planning to do anything with it.

160

I don't really understand the purpose for this function any longer. Why do we want two different options to disable generating ISEL's?
With this we have -mno-isel/-mattr=-isel as well as -ppc-generate-isel=false.

248

I don't think the name of the variable is useful to the consumer of the debug output. Probably something like:
DEBUG(dbgs() << "ISEL: " << **MI << "\n");

274

I suppose you've considered whether the erase here invalidates the iterator...
Perhaps setting MI to the result of the erase keeps the iterator valid. If so, maybe a quick comment to that end.

281

Just out of curiosity, is the comparison even needed? Wouldn't an ISEL that looks like
isel 5, 0, 0, 1
actually be a MachineInstr like
ISEL %X5, %ZERO8, %X0, %CR0LT
or something along those lines?

345

I am wondering if this is safe to do.
If there's a KILL for one of the live-ins in this MBB prior to the ISEL being expanded (or the ISEL itself is a KILL), would we violate some kind of invariant? Basically adding a live-in to a block when it isn't live out of the now truncated MBB.

[jtony]

lib/Target/PowerPC/PPCExpandISEL.cpp

35

Discussed in the scrum, we want it to be hidden because the user can use the FE option -misel and -mno-isel to control the generation of ISEL instructions.

109

Good call, it doesn't need to be public, have made it class private.

160

Good question, we need the -ppc-generate-isel only for our convenient, without it we couldn't control the IR and MIR test cases to expand ISEL in the BE, the FE options misel and mno-isel is for the users, the ppc-gen-isel option is set to hidden are only used by us.

274

Exactly, a lot of people made errors about this, I fixed one such bug before in the FE. Good call, I will add a comment to that end.

281

The (TrueValue.getReg() != PPC::R0) parted is redundant, removed.

310

Good call! Fixed and tested with a MIR file: expand-isel-6.mir

345

You are right we don't need to copy all the LiveIn registers, but it's hard to tell which ones we should copy and which shouldn't, we simply called everything to the NewSuccessor. I think it is just some performance issue, won't cause any problem as far as I know. I also tested adding an redudant register to an MIR file, it doesn't cause issue.

[jtony]

Add 6 MIR test cases for special conditions ( mainly about R0)
(2) Fix the bug that triggers the can-fall-through assertion (when the ISEL is the last non-debug instruction of the last BB). And create 1 MIR test case for this assertion.
(3) Address some other minor comments posted on phabricator.

[nemanjai]

None of the comments indicate a serious issue that requires a major revision. However, there are a number of comments to be addressed and I think it'd be better if you published another revision that addresses them.

However, if other reviewers feel this is ready to commit, I certainly won't object.

lib/Target/PowerPC/PPCExpandISEL.cpp

62

Minor nit: I'd just state in the comment what this actually is - "A map of MBB numbers to their lists of contained ISEL instructions."

71

I don't think the name clearly reflects what the function does. Perhaps expandAndMergeISELs.

86

"Are the two operands..."

87

Please make these references const, we don't want to modify them.

166

I wonder if we should maybe have an assert here that the insert actually inserts something (i.e. we don't somehow end up with duplicate MBB numbers). Of course, this is not likely to happen, but if it did, we'd have unpredictable behaviour.

182

I would simplify this function with early exits rather than initializing boolean variables you'll only query once:

if (!(isSameRegister(...))
  return false;
// more init - come to think of it, you may want to just get rid of them and cast to iterator in the if below

if (std::prev(MBBI) != PrevPushedMBBI) {
  NumNonContiguous++;
  return false;
}

NumContiguous++;
return true;

227

No need to evaluate BIL.end() on every iteration. Or is it needed because of the potential call to erase()?

294

Perhaps a quick comment above this line. Sure you know why we're creating the basic block now, but you (or anyone else) will have to think about this condition a fair bit to understand why.
Maybe something like:

// Another basic block is needed to move the instructions that follow this ISEL.
// If the ISEL is the last instruction in a block that can't fall through,
// we need another block to branch to.

305

Why is this not a range-based for loop? The MBB should have a way to get an iterator_range for its successors. Perhaps something like MBB->successors()

338

Again, there must be a way to make this a range-based for loop. Perhaps MBB->liveins()?

349

It seems that you only need to add Successor as a successor to MBB if either the TrueBlock or the FalseBlock are not required. If so, these don't need to be executed unconditionally here - they can be sunk into the respective if statement.

387

Perhaps I've lost track here since the patch is fairly large, but don't you already have this available in IsTrueBlockRequired? Similarly with IsFalseBlockRequired below.

405

Why? I don't see the need for a register you're about to define to be added as live-in.

412

This seems a bit suspicious. If the ISEL you're actually expanding was a KILL for the True/False Register[s], it seems wrong to add it as live-in to the successor.

I suppose it doesn't necessarily hurt since you're not actually setting kill flags on the instructions you're adding. The only way I could see this causing a problem is if something that runs after this is looking for free registers. Of course, this isn't impossible. I think it's quite possible that prologue/epilogue insertion happens after this and it may need to find an unused register. Since you've [possibly] eliminated the kill flags, the register scavenger will not find these and we may emit sub-optimal code if we're shrink-wrapping.

lib/Target/PowerPC/PPCSubtarget.h

301–303

I didn't check, but presumably the base class returns false for this? If not, just get rid of the override. If so, put a comment as to why we always want to run EarlyIfConversion.

test/CodeGen/PowerPC/expand-contiguous-isel.ll

124

I don't think this particular register allocation is guaranteed. Perhaps change all of these to something like:

; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], [[SAME]], [[SAME]]

test/CodeGen/PowerPC/expand-isel-2.mir

36

All the %bb without a number is confusing. Can you change these to something like
; CHECK: BC %cr0gt, [[TRUE:%bb[0-9]+]]
and so on?

[jtony]

lib/Target/PowerPC/PPCExpandISEL.cpp

166

Sorry , I am not clear what kind of assertion we should insert here, can you be more specific?

227

I think the BIL.end() is needed here, one reason is we may call erase, also even we don't call erase(), we need it to tell us when to finish the loop.

349

I can merge these two ternary expression with the following two if guards by adding two more else, but I prefer to leave it as it is unless for some other solid reason.

387

I agree this patch is really large and kind of hard to follow the whole logic. IsTrueBlockRequired is used to guard whether generate the True Block, while IsADDIInstRequired only guards whether we should generate one ADDI instruction. IsTrueBlockRequired = IsADDIInstRequired(1) OR IsADDIInstRequired(2) ... OR IsADDIInstRequired(N). Similarly for IsFalseBlockRequired and IsORIInstRequired.

[jtony]

Address more comments from Nemanja.

[kbarton]

There are still a few things that need to get cleaned up.

lib/Target/PowerPC/PPCExpandISEL.cpp

85

Technically, I think this should be called useSameRegister

114

insturction -> instruction

256

I don't understand why this is only valid when there is one ISEL in the list.

256

You also need to check for register 0.
This isn't valid if TrueValue or FalseValue is r0, since it has different semantics on the True/False paths.

lib/Target/PowerPC/PPCTargetMachine.cpp

420

Did this get done?
I agree it would be better to not use verifyAfter=false here unless it is needed for some reason.

[nemanjai]

lib/Target/PowerPC/PPCExpandISEL.cpp

69

I meant to rename both expandCanMergeISELs with my previous comment. The name expandCanMergeISELs sounds to me like something called expand has the ability to merge ISELs - it's quite a confusing name.
The function takes a list of ISEL instructions, expands them into control flow AND it merges them (since they're already demonstrably mergeable).

75

This is just a minor nit that you can choose to address or ignore, but this does not need any non-static members so I would make these queries static.

256

I think Kit raises valid points here and I think we should add comments to address them as any reader would reasonably have the same questions when looking at the code.

// Note 1: We favour merging ISEL expansions over folding a single one. If the
//         passed list has multiple merge-able ISEL's, we won't fold any.
// Note 2: There is no need to test for PPC::R0/PPC::X0 because the first input
//         for ISEL uses register class 'gprc_nor0' which explicitly excludes
//         PPC::R0 (and similarly for the 64-bit variants). So:
//         TrueVal.getReg() == FalseVal.getReg() => FalseVal.getReg() != PPC::R0

lib/Target/PowerPC/PPCTargetMachine.cpp

420

I don't know the characteristics of the verification, but I assume that it takes some non-zero compile time and that it will run verification in all build modes.
If this is the case, I am personally in favour of adding a call to MachineFunction::verify() at the end of RunOnMachineFunction() wrapped in an #ifndef NDEBUG so that we get the verification with asserts and in debug mode, but save the associated compile-time in release mode.

[jtony]

Address the comments from Kit and Nemanja.
Main changes are ：
（1）setting verifyAfter=true when adding pass.
（2） fix some undefined physical register errors during verification, which is caused by when splitting one MBB into two, Regs defined in the first half is no longer visible to the second half. Need to add Regs defined in the first half as LiveIns of the second half. See lines 341-352 of file: lib/Target/PowerPC/PPCExpandISEL.cpp for details.

[jtony]

lib/Target/PowerPC/PPCTargetMachine.cpp

420

verifyAfter=false is removed now, by default we will use verifyAfter=true, so the verification is done always.

[jtony]

Set the LiveIns of NewSuccessor Block properly.

Main changes are around lines: 338-349 of file lib/Target/PowerPC/PPCExpandISEL.cpp.

Similar logic can be found in function HexagonFrameLowering::expandStoreVec2() of file lib/Target/Hexagon/HexagonFrameLowering.cpp

[kbarton]

lib/Target/PowerPC/PPCExpandISEL.cpp

260

There is currently a bug filed against the PPC backend for this (https://llvm.org/bugs/show_bug.cgi?id=31065). Once this bug is fixed, the register class will need to include r0.
Please include a check for R0 here as well, to ensure correctness.

347

According to the documentation for stepForward, it is not the preferred method for calculating liveness. Instead, stepBackward should be used instead.
Did you try using stepBackward? If not, please change this to use stepBackward.

[nemanjai]

You'll need to rebase this to the current TopOfTrunk and make changes due to https://reviews.llvm.org/D28556.

[nemanjai]

lib/Target/PowerPC/PPCExpandISEL.cpp

260

The register class can't include PPC::R0/PPC::X0. It must include PPC::ZERO/PPC::ZERO8 instead. The bug mentioned isn't valid (I've added a clarifying comment to it). We certainly do allocate PPC::ZERO/PPC::ZERO8 for the ISEL instruction when the true operand comes from LI 0 (i.e. it's an immediate zero). This is done in PPCInstrInfo::FoldImmediate().

[kbarton]

Aside from updating two comments, this LGTM.

lib/Target/PowerPC/PPCExpandISEL.cpp

260

OK, I understand.
In that case, please change the comment to:

Note 2: There is no need to test for PPC::R0/PPC::X0 because PPC::ZERO/PPC::ZERO8 will be used for the first operand if the value is meant to be zero. In this case, the useSameRegister method will return false, thereby preventing this ISEL from being folded.

347

Based on an off-line conversanion, stepBackwark doesn't work.
Please add a comment here saying why stepForward is being used.

lib/Target/PowerPC/CMakeLists.txt

add_llvm_target(PowerPCCodeGen
   PPCTargetMachine.cpp
   PPCTargetObjectFile.cpp
   PPCTargetTransformInfo.cpp
   PPCTOCRegDeps.cpp
   PPCTLSDynamicCall.cpp
   PPCVSXCopy.cpp
   PPCVSXFMAMutate.cpp
   PPCVSXSwapRemoval.cpp
+  PPCExpandISEL.cpp
   )
 
 add_subdirectory(AsmParser)
 add_subdirectory(Disassembler)
 add_subdirectory(InstPrinter)
 add_subdirectory(TargetInfo)
 add_subdirectory(MCTargetDesc)

lib/Target/PowerPC/PPC.h

#endif
   FunctionPass *createPPCVSXFMAMutatePass();
   FunctionPass *createPPCVSXSwapRemovalPass();
   FunctionPass *createPPCMIPeepholePass();
   FunctionPass *createPPCBranchSelectionPass();
   FunctionPass *createPPCQPXLoadSplatPass();
   FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
   FunctionPass *createPPCTLSDynamicCallPass();
   FunctionPass *createPPCBoolRetToIntPass();
+  FunctionPass *createPPCExpandISELPass();
   void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                     AsmPrinter &AP, bool isDarwin);
 
   void initializePPCVSXFMAMutatePass(PassRegistry&);
   void initializePPCBoolRetToIntPass(PassRegistry&);
+  void initializePPCExpandISELPass(PassRegistry &);
   extern char &PPCVSXFMAMutateID;
 
   namespace PPCII {
     
   /// Target Operand Flag enum.
   enum TOF {
     //===------------------------------------------------------------------===//
     // PPC Specific MachineOperand flags.

lib/Target/PowerPC/PPCExpandISEL.cpp

+//===------------- PPCExpandISEL.cpp - Expand ISEL instruction ------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// A pass that expands the ISEL instruction into an if-then-else sequence.
+// This pass must be run post-RA since all operands must be physical registers.
+//
+//===----------------------------------------------------------------------===//
+
+#include "PPC.h"
+#include "PPCInstrInfo.h"
+#include "PPCSubtarget.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "ppc-expand-isel"
+
+STATISTIC(NumExpanded, "Number of ISEL instructions expanded");
+STATISTIC(NumRemoved, "Number of ISEL instructions removed");
+STATISTIC(NumFolded, "Number of ISEL instructions folded");
+
+// If -ppc-gen-isel=false is set, we will disable generating the ISEL
+// instruction on all PPC targets. Otherwise, if the user set option
+// -misel or the platform supports ISEL by default, still generate the
+// ISEL instruction, else expand it.
+static cl::opt<bool>
+    GenerateISEL("ppc-gen-isel",
+                 cl::desc("Enable generating the ISEL instruction."),
+                 cl::init(true), cl::Hidden);
+
+class PPCExpandISEL : public MachineFunctionPass {
+  DebugLoc dl;
+  MachineFunction *MF;
+  const TargetInstrInfo *TII;
+  bool IsTrueBlockRequired;
+  bool IsFalseBlockRequired;
+  MachineBasicBlock *TrueBlock;
+  MachineBasicBlock *FalseBlock;
+  MachineBasicBlock *NewSuccessor;
+  MachineBasicBlock::iterator TrueBlockI;
+  MachineBasicBlock::iterator FalseBlockI;
+
+  typedef SmallVector<MachineInstr *, 4> BlockISELList;
+  typedef SmallDenseMap<int, BlockISELList> ISELInstructionList;
+
+  // A map of MBB numbers to their lists of contained ISEL instructions.
+  ISELInstructionList ISELInstructions;
+
+  /// Initialize the object.
+  void initialize(MachineFunction &MFParam);
+
+  void handleSpecialCases(BlockISELList &BIL, MachineBasicBlock *MBB);
+  void reorganizeBlockLayout(BlockISELList &BIL, MachineBasicBlock *MBB);
+  void populateBlocks(BlockISELList &BIL);
+  void expandMergeableISELs(BlockISELList &BIL);
+  void expandAndMergeISELs();
+
+  bool canMerge(MachineInstr *PrevPushedMI, MachineInstr *MI);
+
+  ///  Is this instruction an ISEL or ISEL8?
+  static bool isISEL(const MachineInstr &MI) {
+    return (MI.getOpcode() == PPC::ISEL || MI.getOpcode() == PPC::ISEL8);
+  }
+
+  ///  Is this instruction an ISEL8?
+  static bool isISEL8(const MachineInstr &MI) {
+    return (MI.getOpcode() == PPC::ISEL8);
+  }
+
+  /// Are the two operands using the same register?
+  bool useSameRegister(const MachineOperand &Op1, const MachineOperand &Op2) {
+    return (Op1.getReg() == Op2.getReg());
+  }
+
+  ///
+  ///  Collect all ISEL instructions from the current function.
+  ///
+  /// Walk the current function and collect all the ISEL instructions that are
+  /// found. The instructions are placed in the ISELInstructions vector.
+  ///
+  /// \return true if any ISEL instructions were found, false otherwise
+  ///
+  bool collectISELInstructions();
+
+public:
+  static char ID;
+  PPCExpandISEL() : MachineFunctionPass(ID) {
+    initializePPCExpandISELPass(*PassRegistry::getPassRegistry());
+  }
+
+  ///
+  ///  Determine whether to generate the ISEL instruction or expand it.
+  ///
+  /// Expand ISEL instruction into if-then-else sequence when one of
+  /// the following two conditions hold:
+  /// (1) -ppc-gen-isel=false
+  /// (2) hasISEL() return false
+  /// Otherwise, still generate ISEL instruction.
+  /// The -ppc-gen-isel option is set to true by default. Which means the ISEL
+  /// instruction is still generated by default on targets that support them.
+  ///
+  /// \return true if ISEL should be expanded into if-then-else code sequence;
+  ///         false if ISEL instruction should be generated, i.e. not expaned.
+  ///
+  static bool isExpandISELEnabled(const MachineFunction &MF);
+
+#ifndef NDEBUG
+  void DumpISELInstructions() const;
+#endif
+
+  bool runOnMachineFunction(MachineFunction &MF) override {
+    if (!isExpandISELEnabled(MF))
+      return false;
+
+    DEBUG(dbgs() << "Function: "; MF.dump(); dbgs() << "\n");
+    initialize(MF);
+
+    if (!collectISELInstructions()) {
+      DEBUG(dbgs() << "No ISEL instructions in this function\n");
+      return false;
+    }
+
+#ifndef NDEBUG
+    DumpISELInstructions();
+#endif
+
+    expandAndMergeISELs();
+
+    return true;
+  }
+};
+
+void PPCExpandISEL::initialize(MachineFunction &MFParam) {
+  MF = &MFParam;
+  TII = MF->getSubtarget().getInstrInfo();
+  ISELInstructions.clear();
+}
+
+bool PPCExpandISEL::isExpandISELEnabled(const MachineFunction &MF) {
+  return !GenerateISEL || !MF.getSubtarget<PPCSubtarget>().hasISEL();
+}
+
+bool PPCExpandISEL::collectISELInstructions() {
+  for (MachineBasicBlock &MBB : *MF) {
+    BlockISELList thisBlockISELs;
+    for (MachineInstr &MI : MBB)
+      if (isISEL(MI))
+        thisBlockISELs.push_back(&MI);
+    if (!thisBlockISELs.empty())
+      ISELInstructions.insert(std::make_pair(MBB.getNumber(), thisBlockISELs));
+  }
+  return !ISELInstructions.empty();
+}
+
+#ifndef NDEBUG
+void PPCExpandISEL::DumpISELInstructions() const {
+  for (const auto &I : ISELInstructions) {
+    DEBUG(dbgs() << "BB#" << I.first << ":\n");
+    for (const auto &VI : I.second)
+      DEBUG(dbgs() << "    "; VI->print(dbgs()));
+  }
+}
+#endif
+
+/// Contiguous ISELs that have the same condition can be merged.
+bool PPCExpandISEL::canMerge(MachineInstr *PrevPushedMI, MachineInstr *MI) {
+  // Same Condition Register?
+  if (!useSameRegister(PrevPushedMI->getOperand(3), MI->getOperand(3)))
+    return false;
+
+  MachineBasicBlock::iterator PrevPushedMBBI = *PrevPushedMI;
+  MachineBasicBlock::iterator MBBI = *MI;
+  return (std::prev(MBBI) == PrevPushedMBBI); // Contiguous ISELs?
+}
+
+void PPCExpandISEL::expandAndMergeISELs() {
+  for (auto &BlockList : ISELInstructions) {
+    DEBUG(dbgs() << "Expanding ISEL instructions in BB#" << BlockList.first
+                 << "\n");
+
+    BlockISELList &CurrentISELList = BlockList.second;
+    auto I = CurrentISELList.begin();
+    auto E = CurrentISELList.end();
+
+    while (I != E) {
+      BlockISELList SubISELList;
+
+      SubISELList.push_back(*I++);
+
+      // Collect the ISELs that can be merged together.
+      while (I != E && canMerge(SubISELList.back(), *I))
+        SubISELList.push_back(*I++);
+
+      expandMergeableISELs(SubISELList);
+    }
+  }
+}
+
+void PPCExpandISEL::handleSpecialCases(BlockISELList &BIL,
+                                       MachineBasicBlock *MBB) {
+  IsTrueBlockRequired = false;
+  IsFalseBlockRequired = false;
+
+  auto MI = BIL.begin();
+  while (MI != BIL.end()) {
+    assert(isISEL(**MI) && "Expecting an ISEL instruction");
+    DEBUG(dbgs() << "ISEL: " << **MI << "\n");
+
+    MachineOperand &Dest = (*MI)->getOperand(0);       // location to store to
+    MachineOperand &TrueValue = (*MI)->getOperand(1);  // Value to store if
+                                                       // condition is true
+    MachineOperand &FalseValue = (*MI)->getOperand(2); // Value to store if
+                                                       // condition is false
+    MachineOperand &ConditionRegister = (*MI)->getOperand(3); // Condition
+
+    DEBUG(dbgs() << "Dest: " << Dest << "\n");
+    DEBUG(dbgs() << "TrueValue: " << TrueValue << "\n");
+    DEBUG(dbgs() << "FalseValue: " << FalseValue << "\n");
+    DEBUG(dbgs() << "ConditionRegister: " << ConditionRegister << "\n");
+
+    // If at least one of the ISEL instructions satisfy the following
+    // condition, we need the True Block:
+    // The Dest Register and True Value Register are not the same
+    // Similarly, if at least one of the ISEL instructions satisfy the
+    // following condition, we need the False Block:
+    // The Dest Register and False Value Register are not the same.
+
+    bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue);
+    bool IsORIInstRequired = !useSameRegister(Dest, FalseValue);
+
+    // Special case 1, all registers used by ISEL are the same one.
+    if (!IsADDIInstRequired && !IsORIInstRequired) {
+      DEBUG(dbgs() << "Remove redudant ISEL instruction.");
+      NumRemoved++;
+      (*MI)->eraseFromParent();
+      // Setting MI to the erase result keeps the iterator valid and increased.
+      MI = BIL.erase(MI);
+      continue;
+    }
+
+    // Special case 2, the two input registers used by ISEL are the same.
+    // Note 1: We favor merging ISEL expansions over folding a single one. If
+    // the passed list has multiple merge-able ISEL's, we won't fold any.
+    // Note 2: There is no need to test for PPC::R0/PPC::X0 because the first
+    // input for ISEL uses register class 'gprc_nor0' which explicitly excludes
+    // PPC::R0 (and similarly for the 64-bit variants). So:
+    // useSameRegister(TrueValue, FalseValue)  => FalseValue.getReg() != PPC::R0
+    if (useSameRegister(TrueValue, FalseValue) && (BIL.size() == 1)) {
+      DEBUG(dbgs() << "Fold the ISEL instruction to an unconditonal copy.");
+      NumFolded++;
+      BuildMI(*MBB, (*MI), dl, TII->get(isISEL8(**MI) ? PPC::ADDI8 : PPC::ADDI))
+          .addOperand(Dest)
+          .addOperand(TrueValue)
+          .addOperand(MachineOperand::CreateImm(0));
+      (*MI)->eraseFromParent();
+      // Setting MI to the erase result keeps the iterator valid and increased.
+      MI = BIL.erase(MI);
+      continue;
+    }
+
+    IsTrueBlockRequired |= IsADDIInstRequired;
+    IsFalseBlockRequired |= IsORIInstRequired;
+    MI++;
+  }
+}
+
+void PPCExpandISEL::reorganizeBlockLayout(BlockISELList &BIL,
+                                          MachineBasicBlock *MBB) {
+  if (BIL.empty())
+    return;
+
+  assert((IsTrueBlockRequired || IsFalseBlockRequired) &&
+         "Should have been handled by special cases earlier!");
+
+  MachineBasicBlock *Successor = nullptr;
+  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
+  MachineBasicBlock::iterator MBBI = (*BIL.back());
+  NewSuccessor = (MBBI != MBB->getLastNonDebugInstr() || !MBB->canFallThrough())
+                     // Another BB is needed to move the instructions that
+                     // follow this ISEL.  If the ISEL is the last instruction
+                     // in a block that can't fall through, we also need a block
+                     // to branch to.
+                     ? MF->CreateMachineBasicBlock(LLVM_BB)
+                     : nullptr;
+
+  MachineFunction::iterator It = MBB->getIterator();
+  ++It; // Point to the successor block of MBB.
+
+  // If NewSuccessor is NULL then the last ISEL in this group is the last
+  // non-debug instruction in this block. Find the fall-through successor
+  // of this block to use when updating the CFG below.
+  if (!NewSuccessor) {
+    for (auto &Succ : MBB->successors()) {
+      if (MBB->isLayoutSuccessor(Succ)) {
+        Successor = Succ;
+        break;
+      }
+    }
+  } else
+    Successor = NewSuccessor;
+
+  // The FalseBlock and TrueBlock are inserted after the MBB block but before
+  // its successor.
+  // Note this need to be done *after* the above setting the Successor code.
+  if (IsFalseBlockRequired) {
+    FalseBlock = MF->CreateMachineBasicBlock(LLVM_BB);
+    MF->insert(It, FalseBlock);
+  }
+
+  if (IsTrueBlockRequired) {
+    TrueBlock = MF->CreateMachineBasicBlock(LLVM_BB);
+    MF->insert(It, TrueBlock);
+  }
+
+  if (NewSuccessor) {
+    MF->insert(It, NewSuccessor);
+
+    // Transfer the rest of this block into the new successor block.
+    NewSuccessor->splice(NewSuccessor->end(), MBB,
+                         std::next(MachineBasicBlock::iterator(BIL.back())),
+                         MBB->end());
+    NewSuccessor->transferSuccessorsAndUpdatePHIs(MBB);
+
+    // Copy the original liveIns of MBB to NewSuccessor.
+    for (auto &LI : MBB->liveins())
+      NewSuccessor->addLiveIn(LI);
+
+    // After splitting the NewSuccessor block, Regs defined but not killed
+    // in MBB should be treated as liveins of NewSuccessor.
+    LivePhysRegs LPR(MF->getSubtarget<PPCSubtarget>().getRegisterInfo());
+    SmallVector<std::pair<unsigned, const MachineOperand*>,2> Clobbers;
+    for (MachineInstr &MI : *MBB)
+      LPR.stepForward(MI, Clobbers);
+    for (auto &LI : LPR)
+      NewSuccessor->addLiveIn(LI);
+  } else {
+    // Remove successor from MBB.
+    MBB->removeSuccessor(Successor);
+  }
+
+  // Note that this needs to be done *after* transfering the successors from MBB
+  // to the NewSuccessor block, otherwise these blocks will also be transferred
+  // as successors!
+  MBB->addSuccessor(IsTrueBlockRequired ? TrueBlock : Successor);
+  MBB->addSuccessor(IsFalseBlockRequired ? FalseBlock : Successor);
+
+  if (IsTrueBlockRequired) {
+    TrueBlockI = TrueBlock->begin();
+    TrueBlock->addSuccessor(Successor);
+  }
+
+  if (IsFalseBlockRequired) {
+    FalseBlockI = FalseBlock->begin();
+    FalseBlock->addSuccessor(Successor);
+  }
+
+  // Conditional branch to the TrueBlock or Successor
+  BuildMI(*MBB, BIL.back(), dl, TII->get(PPC::BC))
+      .addOperand(BIL.back()->getOperand(3))
+      .addMBB(IsTrueBlockRequired ? TrueBlock : Successor);
+
+  // Jump over the true block to the new successor if the condition is false.
+  BuildMI(*(IsFalseBlockRequired ? FalseBlock : MBB),
+          (IsFalseBlockRequired ? FalseBlockI : BIL.back()), dl,
+          TII->get(PPC::B))
+      .addMBB(Successor);
+
+  if (IsFalseBlockRequired)
+    FalseBlockI = FalseBlock->begin(); // get the position of PPC::B
+}
+
+void PPCExpandISEL::populateBlocks(BlockISELList &BIL) {
+  for (auto &MI : BIL) {
+    assert(isISEL(*MI) && "Expecting an ISEL instruction");
+
+    MachineOperand &Dest = MI->getOperand(0);
+    MachineOperand &TrueValue = MI->getOperand(1);
+    MachineOperand &FalseValue = MI->getOperand(2);
+    MachineOperand &ConditionRegister = MI->getOperand(3);
+
+    // If the Dest Register and True Value Register are not the same one, we
+    // need the True Block.
+    bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue);
+    bool IsORIInstRequired = !useSameRegister(Dest, FalseValue);
+
+    if (IsADDIInstRequired) {
+      // Copy the result into the destination if the condition is true.
+      BuildMI(*TrueBlock, TrueBlockI, dl,
+              TII->get(isISEL8(*MI) ? PPC::ADDI8 : PPC::ADDI))
+          .addOperand(Dest)
+          .addOperand(TrueValue)
+          .addOperand(MachineOperand::CreateImm(0));
+
+      // Add the LiveIn registers required by true block.
+      TrueBlock->addLiveIn(TrueValue.getReg());
+    }
+
+    if (IsORIInstRequired) {
+      // Add the LiveIn registers required by false block.
+      FalseBlock->addLiveIn(FalseValue.getReg());
+    }
+
+    if (NewSuccessor) {
+      // Add the LiveIn registers required by NewSuccessor block.
+      NewSuccessor->addLiveIn(Dest.getReg());
+      NewSuccessor->addLiveIn(TrueValue.getReg());
+      NewSuccessor->addLiveIn(FalseValue.getReg());
+      NewSuccessor->addLiveIn(ConditionRegister.getReg());
+    }
+
+    // Copy the value into the destination if the condition is false.
+    if (IsORIInstRequired)
+      BuildMI(*FalseBlock, FalseBlockI, dl,
+              TII->get(isISEL8(*MI) ? PPC::ORI8 : PPC::ORI))
+          .addOperand(Dest)
+          .addOperand(FalseValue)
+          .addOperand(MachineOperand::CreateImm(0));
+
+    MI->eraseFromParent(); // Remove the ISEL instruction.
+
+    NumExpanded++;
+  }
+}
+
+void PPCExpandISEL::expandMergeableISELs(BlockISELList &BIL) {
+  // At this stage all the ISELs of BIL are in the same MBB.
+  MachineBasicBlock *MBB = BIL.back()->getParent();
+
+  handleSpecialCases(BIL, MBB);
+  reorganizeBlockLayout(BIL, MBB);
+  populateBlocks(BIL);
+}
+
+INITIALIZE_PASS(PPCExpandISEL, DEBUG_TYPE, "PowerPC Expand ISEL Generation",
+                false, false)
+char PPCExpandISEL::ID = 0;
+
+FunctionPass *llvm::createPPCExpandISELPass() { return new PPCExpandISEL(); }

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 }
 
 // Check if all users of this node will become isel where the second operand
 // is the constant zero. If this is so, and if we can negate the condition,
 // then we can flip the true and false operands. This will allow the zero to
 // be folded with the isel so that we don't need to materialize a register
 // containing zero.
 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
-  // If we're not using isel, then this does not matter.
-  if (!PPCSubTarget->hasISEL())
-    return false;
-
   for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
        UI != UE; ++UI) {
     SDNode *User = *UI;
     if (!User->isMachineOpcode())
       return false;
     if (User->getMachineOpcode() != PPC::SELECT_I4 &&
         User->getMachineOpcode() != PPC::SELECT_I8)
       return false;

lib/Target/PowerPC/PPCISelLowering.cpp

PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
 
   // To "insert" these instructions we actually have to insert their
   // control-flow patterns.
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
   MachineFunction::iterator It = ++BB->getIterator();
 
   MachineFunction *F = BB->getParent();
 
-  if (Subtarget.hasISEL() &&
-      (MI.getOpcode() == PPC::SELECT_CC_I4 ||
+  if (MI.getOpcode() == PPC::SELECT_CC_I4 ||
        MI.getOpcode() == PPC::SELECT_CC_I8 ||
-       MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8)) {
+       MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8) {
     SmallVector<MachineOperand, 2> Cond;
     if (MI.getOpcode() == PPC::SELECT_CC_I4 ||
         MI.getOpcode() == PPC::SELECT_CC_I8)
       Cond.push_back(MI.getOperand(4));
     else
       Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
     Cond.push_back(MI.getOperand(1));
 

lib/Target/PowerPC/PPCInstrInfo.cpp

unsigned PPCInstrInfo::insertBranch(MachineBasicBlock &MBB,
   return 2;
 }
 
 // Select analysis.
 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
                 ArrayRef<MachineOperand> Cond,
                 unsigned TrueReg, unsigned FalseReg,
                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
-  if (!Subtarget.hasISEL())
-    return false;
-
   if (Cond.size() != 2)
     return false;
 
   // If this is really a bdnz-like condition, then it cannot be turned into a
   // select.
   if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
     return false;
 

 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MI,
                                 const DebugLoc &dl, unsigned DestReg,
                                 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
                                 unsigned FalseReg) const {
   assert(Cond.size() == 2 &&
          "PPC branch conditions have two components!");
 
-  assert(Subtarget.hasISEL() &&
-         "Cannot insert select on target without ISEL support");
-
   // Get the register classes.
   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
   const TargetRegisterClass *RC =
     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
   assert(RC && "TrueReg and FalseReg must have overlapping register classes");
 
   bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
                  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);

lib/Target/PowerPC/PPCSubtarget.h

public:
   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
 
   bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
   bool isSVR4ABI() const { return !isDarwinABI(); }
   bool isELFv2ABI() const;
 
-  bool enableEarlyIfConversion() const override { return hasISEL(); }
+  /// Originally, this function return hasISEL(). Now we always enable it,
+  /// but may expand the ISEL instruction later.
+  bool enableEarlyIfConversion() const override { return true; }
 
   // Scheduling customization.
   bool enableMachineScheduler() const override;
   // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
   bool enablePostRAScheduler() const override;
   AntiDepBreakMode getAntiDepBreakMode() const override;
   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
 

lib/Target/PowerPC/PPCTargetMachine.cpp

 extern "C" void LLVMInitializePowerPCTarget() {
   // Register the targets
   RegisterTargetMachine<PPC32TargetMachine> A(getThePPC32Target());
   RegisterTargetMachine<PPC64TargetMachine> B(getThePPC64Target());
   RegisterTargetMachine<PPC64TargetMachine> C(getThePPC64LETarget());
 
   PassRegistry &PR = *PassRegistry::getPassRegistry();
   initializePPCBoolRetToIntPass(PR);
+  initializePPCExpandISELPass(PR);
 }
 
 /// Return the datalayout string of a subtarget.
 static std::string getDataLayoutString(const Triple &T) {
   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
   std::string Ret;
 
   // Most PPC* platforms are big endian, PPC64LE is little endian.
if (getOptLevel() != CodeGenOpt::None) {
     // forwarding. Here we're after RA (and, thus, when spills are inserted)
     // but before post-RA scheduling.
     if (!DisableQPXLoadSplat)
       addPass(createPPCQPXLoadSplatPass());
   }
 }
 
 void PPCPassConfig::addPreEmitPass() {
+  addPass(createPPCExpandISELPass());
+
   if (getOptLevel() != CodeGenOpt::None)
     addPass(createPPCEarlyReturnPass(), false);
   // Must run branch selection immediately preceding the asm printer.
   addPass(createPPCBranchSelectionPass(), false);
 }
 
 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
   return TargetIRAnalysis([this](const Function &F) {
     return TargetTransformInfo(PPCTTIImpl(this, F));
   });
 }

test/CodeGen/PowerPC/crbit-asm.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false  < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
+; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
+
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 {
 entry:
   %0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0
   %1 = and i8 %0, 1
   %tobool3 = icmp ne i8 %1, 0
   ret i1 %tobool3
 
 ; CHECK-LABEL: @testi1
 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
 ; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
 ; CHECK-DAG: li [[REG4:[0-9]+]], 1
 ; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
+; CHECK-NO-ISEL-LABEL: @testi1
+; CHECK-NO-ISEL: bclr 12, 20, 0
+; CHECK-NO-ISEL: ori 3, 5, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 {
 entry:
   %0 = tail call i32 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i32 %b1, i32 %b2) #0
   ret i32 %0
 

test/CodeGen/PowerPC/crbits.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s 
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; Function Attrs: nounwind readnone
 define zeroext i1 @test1(float %v1, float %v2) #0 {
 entry:
   %cmp = fcmp oge float %v1, %v2
   %cmp2 = fcmp ole float %v2, 0.000000e+00
   %and5 = and i1 %cmp, %cmp2
   ret i1 %and5
 
 ; CHECK-LABEL: @test1
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK-DAG: li [[REG1:[0-9]+]], 1
 ; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
 ; CHECK: crnor
 ; CHECK: crnor
 ; CHECK: crnand [[REG4:[0-9]+]],
 ; CHECK: isel 3, 0, [[REG1]], [[REG4]]
+; CHECK-NO-ISEL-LABEL: @test1
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 ; Function Attrs: nounwind readnone
 define zeroext i1 @test2(float %v1, float %v2) #0 {
 entry:
   %cmp = fcmp oge float %v1, %v2
   %cmp2 = fcmp ole float %v2, 0.000000e+00

test/CodeGen/PowerPC/expand-contiguous-isel.ll

+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+; This file mainly tests that one of the ISEL instruction in the group uses the same register for operand RT, RA, RB
+; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=true < %s | FileCheck %s --check-prefix=CHECK-GEN-ISEL-TRUE
+; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel
+; Function Attrs: norecurse nounwind readnone
+@.str = private unnamed_addr constant [3 x i8] c"]]\00", align 1
+@.str.1 = private unnamed_addr constant [35 x i8] c"Index < Length && \22Invalid index!\22\00", align 1
+@.str.2 = private unnamed_addr constant [50 x i8] c"/home/jtony/src/llvm/include/llvm/ADT/StringRef.h\00", align 1
+@__PRETTY_FUNCTION__._ZNK4llvm9StringRefixEm = private unnamed_addr constant [47 x i8] c"char llvm::StringRef::operator[](size_t) const\00", align 1
+@.str.3 = private unnamed_addr constant [95 x i8] c"(data || length == 0) && \22StringRef cannot be built from a NULL argument with non-null length\22\00", align 1
+@__PRETTY_FUNCTION__._ZN4llvm9StringRefC2EPKcm = private unnamed_addr constant [49 x i8] c"llvm::StringRef::StringRef(const char *, size_t)\00", align 1
+; Function Attrs: nounwind
+define i64 @_Z3fn1N4llvm9StringRefE([2 x i64] %Str.coerce) local_unnamed_addr #0 {
+entry:
+  %Str.coerce.fca.0.extract = extractvalue [2 x i64] %Str.coerce, 0
+  %Str.coerce.fca.1.extract = extractvalue [2 x i64] %Str.coerce, 1
+  br label %while.cond.outer
+while.cond.outer:                                 ; preds = %_ZNK4llvm9StringRef6substrEmm.exit, %entry
+  %Str.sroa.0.0.ph = phi i64 [ %8, %_ZNK4llvm9StringRef6substrEmm.exit ], [ %Str.coerce.fca.0.extract, %entry ]
+  %.sink.ph = phi i64 [ %sub.i, %_ZNK4llvm9StringRef6substrEmm.exit ], [ %Str.coerce.fca.1.extract, %entry ]
+  %BracketDepth.0.ph = phi i64 [ %BracketDepth.1, %_ZNK4llvm9StringRef6substrEmm.exit ], [ undef, %entry ]
+  %cmp65 = icmp eq i64 %BracketDepth.0.ph, 0
+  br i1 %cmp65, label %while.cond.us.preheader, label %while.cond.preheader
+while.cond.us.preheader:                          ; preds = %while.cond.outer
+  br label %while.cond.us
+while.cond.preheader:                             ; preds = %while.cond.outer
+  %cmp.i34129 = icmp eq i64 %.sink.ph, 0
+  br i1 %cmp.i34129, label %cond.false.i.loopexit135, label %_ZNK4llvm9StringRefixEm.exit.preheader
+_ZNK4llvm9StringRefixEm.exit.preheader:           ; preds = %while.cond.preheader
+  br label %_ZNK4llvm9StringRefixEm.exit
+while.cond.us:                                    ; preds = %while.cond.us.preheader, %_ZNK4llvm9StringRef6substrEmm.exit50.us
+  %Str.sroa.0.0.us = phi i64 [ %3, %_ZNK4llvm9StringRef6substrEmm.exit50.us ], [ %Str.sroa.0.0.ph, %while.cond.us.preheader ]
+  %.sink.us = phi i64 [ %sub.i41.us, %_ZNK4llvm9StringRef6substrEmm.exit50.us ], [ %.sink.ph, %while.cond.us.preheader ]
+  %cmp.i30.us = icmp ult i64 %.sink.us, 2
+  br i1 %cmp.i30.us, label %if.end.us, label %if.end.i.i.us
+if.end.i.i.us:                                    ; preds = %while.cond.us
+  %0 = inttoptr i64 %Str.sroa.0.0.us to i8*
+  %call.i.i.us = tail call signext i32 @memcmp(i8* %0, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i64 0, i64 0), i64 2) #3
+  %phitmp.i.us = icmp eq i32 %call.i.i.us, 0
+  br i1 %phitmp.i.us, label %if.then, label %_ZNK4llvm9StringRefixEm.exit.us
+if.end.us:                                        ; preds = %while.cond.us
+  %cmp.i34.us = icmp eq i64 %.sink.us, 0
+  br i1 %cmp.i34.us, label %cond.false.i.loopexit, label %_ZNK4llvm9StringRefixEm.exit.us
+_ZNK4llvm9StringRefixEm.exit.us:                  ; preds = %if.end.i.i.us, %if.end.us
+  %1 = inttoptr i64 %Str.sroa.0.0.us to i8*
+  %2 = load i8, i8* %1, align 1, !tbaa !2
+  switch i8 %2, label %_ZNK4llvm9StringRef6substrEmm.exit.loopexit [
+    i8 92, label %if.then4.us
+    i8 93, label %if.then9
+  ]
+if.then4.us:                                      ; preds = %_ZNK4llvm9StringRefixEm.exit.us
+  %.sroa.speculated12.i38.us = select i1 %cmp.i30.us, i64 %.sink.us, i64 2
+  %add.ptr.i40.us = getelementptr inbounds i8, i8* %1, i64 %.sroa.speculated12.i38.us
+  %sub.i41.us = sub i64 %.sink.us, %.sroa.speculated12.i38.us
+  %tobool.i.i44.us = icmp ne i8* %add.ptr.i40.us, null
+  %cmp.i4.i45.us = icmp eq i64 %sub.i41.us, 0
+  %or.cond.i.i46.us = or i1 %tobool.i.i44.us, %cmp.i4.i45.us
+  br i1 %or.cond.i.i46.us, label %_ZNK4llvm9StringRef6substrEmm.exit50.us, label %cond.false.i.i47.loopexit
+_ZNK4llvm9StringRef6substrEmm.exit50.us:          ; preds = %if.then4.us
+  %3 = ptrtoint i8* %add.ptr.i40.us to i64
+  br label %while.cond.us
+if.then:                                          ; preds = %if.end.i.i.us
+  ret i64 undef
+cond.false.i.loopexit:                            ; preds = %if.end.us
+  br label %cond.false.i
+cond.false.i.loopexit134:                         ; preds = %_ZNK4llvm9StringRef6substrEmm.exit50
+  br label %cond.false.i
+cond.false.i.loopexit135:                         ; preds = %while.cond.preheader
+  br label %cond.false.i
+cond.false.i:                                     ; preds = %cond.false.i.loopexit135, %cond.false.i.loopexit134, %cond.false.i.loopexit
+  tail call void @__assert_fail(i8* getelementptr inbounds ([35 x i8], [35 x i8]* @.str.1, i64 0, i64 0), i8* getelementptr inbounds ([50 x i8], [50 x i8]* @.str.2, i64 0, i64 0), i32 zeroext 225, i8* getelementptr inbounds ([47 x i8], [47 x i8]* @__PRETTY_FUNCTION__._ZNK4llvm9StringRefixEm, i64 0, i64 0)) #4
+  unreachable
+_ZNK4llvm9StringRefixEm.exit:                     ; preds = %_ZNK4llvm9StringRefixEm.exit.preheader, %_ZNK4llvm9StringRef6substrEmm.exit50
+  %.sink131 = phi i64 [ %sub.i41, %_ZNK4llvm9StringRef6substrEmm.exit50 ], [ %.sink.ph, %_ZNK4llvm9StringRefixEm.exit.preheader ]
+  %Str.sroa.0.0130 = phi i64 [ %6, %_ZNK4llvm9StringRef6substrEmm.exit50 ], [ %Str.sroa.0.0.ph, %_ZNK4llvm9StringRefixEm.exit.preheader ]
+  %4 = inttoptr i64 %Str.sroa.0.0130 to i8*
+  %5 = load i8, i8* %4, align 1, !tbaa !2
+  switch i8 %5, label %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132 [
+    i8 92, label %if.then4
+    i8 93, label %if.end10
+  ]
+if.then4:                                         ; preds = %_ZNK4llvm9StringRefixEm.exit
+  %cmp.i.i37 = icmp ult i64 %.sink131, 2
+  %.sroa.speculated12.i38 = select i1 %cmp.i.i37, i64 %.sink131, i64 2
+  %add.ptr.i40 = getelementptr inbounds i8, i8* %4, i64 %.sroa.speculated12.i38
+  %sub.i41 = sub i64 %.sink131, %.sroa.speculated12.i38
+  %tobool.i.i44 = icmp ne i8* %add.ptr.i40, null
+  %cmp.i4.i45 = icmp eq i64 %sub.i41, 0
+  %or.cond.i.i46 = or i1 %tobool.i.i44, %cmp.i4.i45
+  br i1 %or.cond.i.i46, label %_ZNK4llvm9StringRef6substrEmm.exit50, label %cond.false.i.i47.loopexit133
+cond.false.i.i47.loopexit:                        ; preds = %if.then4.us
+  br label %cond.false.i.i47
+cond.false.i.i47.loopexit133:                     ; preds = %if.then4
+  br label %cond.false.i.i47
+cond.false.i.i47:                                 ; preds = %cond.false.i.i47.loopexit133, %cond.false.i.i47.loopexit
+  tail call void @__assert_fail(i8* getelementptr inbounds ([95 x i8], [95 x i8]* @.str.3, i64 0, i64 0), i8* getelementptr inbounds ([50 x i8], [50 x i8]* @.str.2, i64 0, i64 0), i32 zeroext 90, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @__PRETTY_FUNCTION__._ZN4llvm9StringRefC2EPKcm, i64 0, i64 0)) #4
+  unreachable
+_ZNK4llvm9StringRef6substrEmm.exit50:             ; preds = %if.then4
+  %6 = ptrtoint i8* %add.ptr.i40 to i64
+  %cmp.i34 = icmp eq i64 %sub.i41, 0
+  br i1 %cmp.i34, label %cond.false.i.loopexit134, label %_ZNK4llvm9StringRefixEm.exit
+if.then9:                                         ; preds = %_ZNK4llvm9StringRefixEm.exit.us
+  tail call void @exit(i32 signext 1) #4
+  unreachable
+if.end10:                                         ; preds = %_ZNK4llvm9StringRefixEm.exit
+  %dec = add i64 %BracketDepth.0.ph, -1
+  br label %_ZNK4llvm9StringRef6substrEmm.exit
+_ZNK4llvm9StringRef6substrEmm.exit.loopexit:      ; preds = %_ZNK4llvm9StringRefixEm.exit.us
+  br label %_ZNK4llvm9StringRef6substrEmm.exit
+_ZNK4llvm9StringRef6substrEmm.exit.loopexit132:   ; preds = %_ZNK4llvm9StringRefixEm.exit
+  br label %_ZNK4llvm9StringRef6substrEmm.exit
+_ZNK4llvm9StringRef6substrEmm.exit:               ; preds = %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit, %if.end10
+  %.sink76 = phi i64 [ %.sink131, %if.end10 ], [ %.sink.us, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit ], [ %.sink131, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132 ]
+  %7 = phi i8* [ %4, %if.end10 ], [ %1, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit ], [ %4, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132 ]
+  %BracketDepth.1 = phi i64 [ %dec, %if.end10 ], [ 0, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit ], [ %BracketDepth.0.ph, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132 ]
+  %sub.i = add i64 %.sink76, -1
+  %add.ptr.i = getelementptr inbounds i8, i8* %7, i64 1
+  %8 = ptrtoint i8* %add.ptr.i to i64
+  br label %while.cond.outer
+
+; CHECK-LABEL: @_Z3fn1N4llvm9StringRefE
+; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], [[SAME]], [[SAME]]
+; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], {{r[0-9]+}}, [[SAME]]
+; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT: [[TRUE]]
+; CHECK-NEXT: addi {{r[0-9]+}}, {{r[0-9]+}}, 0
+; CHECK-NEXT: [[SUCCESSOR]]
+}
+
+
+
+; Function Attrs: noreturn nounwind
+declare void @exit(i32 signext) local_unnamed_addr #1
+; Function Attrs: nounwind readonly
+declare signext i32 @memcmp(i8* nocapture, i8* nocapture, i64) local_unnamed_addr #2
+; Function Attrs: noreturn nounwind
+declare void @__assert_fail(i8*, i8*, i32 zeroext, i8*) local_unnamed_addr #1
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { noreturn nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { nounwind readonly }
+attributes #4 = { noreturn nounwind }
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 4.0.0 (trunk 286863) (llvm/trunk 286967)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C++ TBAA"}

test/CodeGen/PowerPC/expand-isel-1.mir

+# This file tests the scenario: ISEL R0, ZERO, R0, CR
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+
+name:            testExpandISEL1
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x0' }
+  - { reg: '%x3' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x3
+
+    %r5 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r0 = ISEL %zero, %r0, %cr0gt
+    ; CHECK-LABEL: testExpandISEL1
+    ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK-NEXT: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r0 = ADDI %zero, 0
+
+    %x3 = EXTSW_32_64 %r0
+
+...
+

test/CodeGen/PowerPC/expand-isel-2.mir

+# This file tests the scenario: ISEL RX, ZERO, RY, CR  (X != 0 && Y != 0)
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x0' }
+  - { reg: '%x3' }
+  - { reg: '%x4' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x3, %x4
+
+    %r5 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r3 = ISEL %zero, %r4, %cr0gt
+    ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK: %[[FALSE:bb.[0-9]+]]
+    ; CHECK: %r3 = ORI %r4, 0
+    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r3 = ADDI %zero, 0
+
+    %x3 = EXTSW_32_64 %r3
+...

test/CodeGen/PowerPC/expand-isel-3.mir

+# This file tests the scenario: ISEL RX, RY, R0, CR  (X != 0 && Y != 0)
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x0' }
+  - { reg: '%x3' }
+  - { reg: '%x4' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x3, %x4
+
+    %r5 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r3 = ISEL %r4, %r0, %cr0gt
+    ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK: %[[FALSE:bb.[0-9]+]]
+    ; CHECK: %r3 = ORI %r0, 0
+    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r3 = ADDI  %r4, 0
+
+    %x3 = EXTSW_32_64  %r3
+
+...

test/CodeGen/PowerPC/expand-isel-4.mir

+# This file tests the scenario: ISEL R0, ZERO, RX, CR  (X != 0)
+# It also tests redundant liveins (%x7) and killed registers.
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x0' }
+  - { reg: '%x3' }
+  - { reg: '%x7' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x3, %x7
+
+    %r5 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r0 = ISEL killed %zero, killed %r5, killed %cr0gt, implicit killed %cr0
+    ; CHECK: BC killed %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK: %[[FALSE:bb.[0-9]+]]
+    ; CHECK: %r0 = ORI killed %r5, 0
+    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r0 = ADDI killed %zero, 0
+
+    %x0 = EXTSW_32_64 killed %r0
+
+...

test/CodeGen/PowerPC/expand-isel-5.mir

+# This file tests the scenario: ISEL R0, RX, R0, CR  (X != 0)
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x0' }
+  - { reg: '%x3' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x3
+
+    %r5 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r0 = ISEL %r5, %r0, %cr0gt
+    ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r0 = ADDI %r5, 0
+    %x3 = EXTSW_32_64 %r0
+
+...

test/CodeGen/PowerPC/expand-isel-6.mir

+# This file tests the scenario when ISEL is the last instruction of the last
+# Basic Block, i.e., the BB cannot fall through to its successor situation.
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x0' }
+  - { reg: '%x3' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x3
+
+    %r5 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r3 = ISEL %zero, %r0, %cr0gt
+    ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK: %[[FALSE:bb.[0-9]+]]
+    ; CHECK: %r3 = ORI %r0, 0
+    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r3 = ADDI %zero, 0
+
+
+...

test/CodeGen/PowerPC/expand-isel-7.mir

+# This file tests the scenario: ISEL RX, RY, RZ, CR  (X != 0 && Y != 0, Z != 0)
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x3' }
+  - { reg: '%x4' }
+  - { reg: '%x5' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x3, %x4, %x5
+
+    %r4 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r5 = ISEL %r3, %r4, %cr0gt
+    ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK: %[[FALSE:bb.[0-9]+]]
+    ; CHECK: %r5 = ORI %r4, 0
+    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r5 = ADDI %r3, 0
+
+    %x5 = EXTSW_32_64 %r5
+
+...

test/CodeGen/PowerPC/expand-isel-8.mir

+# This file tests combining three consecutive ISELs scenario.
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x3' }
+  - { reg: '%x4' }
+  - { reg: '%x5' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x3, %x4, %x5
+
+    %r4 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r5 = ISEL %r3, %r4, %cr0gt
+    %r3 = ISEL %r4, %r5, %cr0gt
+    %r4 = ISEL %r3, %r5, %cr0gt
+    ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK: %[[FALSE:bb.[0-9]+]]
+    ; CHECK: %r5 = ORI %r4, 0
+    ; CHECK: %r3 = ORI %r5, 0
+    ; CHECK: %r4 = ORI %r5, 0
+    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r5 = ADDI %r3, 0
+    ; CHECK: %r3 = ADDI %r4, 0
+    ; CHECK: %r4 = ADDI %r3, 0
+
+    %x5 = EXTSW_32_64 %r5
+    %x3 = EXTSW_32_64 %r3
+
+...

test/CodeGen/PowerPC/expand-isel.ll

+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELToIfElse(i32 signext %i, i32 signext %j) {
+entry:
+  %cmp = icmp sgt i32 %i, 0
+  %add = add nsw i32 %i, 1
+  %cond = select i1 %cmp, i32 %add, i32 %j
+  ret i32 %cond
+
+; CHECK-LABEL: @testExpandISELToIfElse
+; CHECK: addi r5, r3, 1
+; CHECK-NEXT: cmpwi cr0, r3, 0
+; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK: ori r3, r4, 0
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT:  [[TRUE]]
+; CHECK-NEXT: addi r3, r5, 0
+; CHECK-NEXT: [[SUCCESSOR]]
+; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: blr
+}
+
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELToIf(i32 signext %i, i32 signext %j) {
+entry:
+  %cmp = icmp sgt i32 %i, 0
+  %cond = select i1 %cmp, i32 %j, i32 %i
+  ret i32 %cond
+
+; CHECK-LABEL: @testExpandISELToIf
+; CHECK: cmpwi   r3, 0
+; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: blr
+; CHECK-NEXT:  [[TRUE]]
+; CHECK-NEXT: addi r3, r4, 0
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELToElse(i32 signext %i, i32 signext %j) {
+entry:
+  %cmp = icmp sgt i32 %i, 0
+  %cond = select i1 %cmp, i32 %i, i32 %j
+  ret i32 %cond
+
+; CHECK-LABEL: @testExpandISELToElse
+; CHECK: cmpwi   r3, 0
+; CHECK-NEXT: bclr 12, 1, 0
+; CHECK: ori r3, r4, 0
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testReplaceISELWithCopy(i32 signext %i, i32 signext %j) {
+entry:
+  %cmp = icmp sgt i32 %i, 0
+  %cond = select i1 %cmp, i32 %j, i32 %j
+  ret i32 %cond
+
+; CHECK-LABEL: @testReplaceISELWithCopy
+
+; Fix me should really check: addi r3, r4, 0
+; but for some reason it's optimized to mr r3, r4
+; CHECK: mr r3, r4
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELToNull(i32 signext %i, i32 signext %j) {
+entry:
+  %cmp = icmp sgt i32 %i, 0
+  %cond = select i1 %cmp, i32 %i, i32 %i
+  ret i32 %cond
+
+; CHECK-LABEL: @testExpandISELToNull
+; CHECK-NOT: b {{.LBB[0-9]+}}
+; CHECK-NOT: bc
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELsTo2ORIs2ADDIs
+  (i32 signext %a, i32 signext %b, i32 signext %d,
+   i32 signext %f, i32 signext %g) {
+entry:
+
+  %cmp = icmp sgt i32 %g, 0
+  %a.b = select i1 %cmp, i32 %g, i32 %b
+  %d.f = select i1 %cmp, i32 %d, i32 %f
+  %add = add nsw i32 %a.b, %d.f
+  ret i32 %add
+
+; CHECK-LABEL: @testExpandISELsTo2ORIs2ADDIs
+; CHECK: cmpwi r7, 0
+; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK: ori r3, r4, 0
+; CHECK-NEXT: ori r12, r6, 0
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT:  [[TRUE]]
+; CHECK-NEXT: addi r3, r7, 0
+; CHECK-NEXT: addi r12, r5, 0
+; CHECK-NEXT: [[SUCCESSOR]]
+; CHECK-NEXT: add r3, r3, r12
+; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELsTo2ORIs1ADDI
+  (i32 signext %a, i32 signext %b, i32 signext %d,
+   i32 signext %f, i32 signext %g) {
+entry:
+  %cmp = icmp sgt i32 %g, 0
+  %a.b = select i1 %cmp, i32 %a, i32 %b
+  %d.f = select i1 %cmp, i32 %d, i32 %f
+  %add = add nsw i32 %a.b, %d.f
+  ret i32 %add
+
+; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI
+; CHECK: cmpwi cr0, r7, 0
+; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK: ori r3, r4, 0
+; CHECK-NEXT: ori r12, r6, 0
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT: [[TRUE]]
+; CHECK-NEXT: addi r12, r5, 0
+; CHECK-NEXT:  [[SUCCESSOR]]
+; CHECK-NEXT: add r3, r3, r12
+; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELsTo1ORI1ADDI
+  (i32 signext %a, i32 signext %b, i32 signext %d,
+   i32 signext %f, i32 signext %g) {
+entry:
+
+  %cmp = icmp sgt i32 %g, 0
+  %a.b = select i1 %cmp, i32 %a, i32 %b
+  %d.f = select i1 %cmp, i32 %d, i32 %f
+  %add1 = add nsw i32 %a.b, %d.f
+  %add2 = add nsw i32 %a, %add1
+  ret i32 %add2
+
+; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI
+; CHECK: cmpwi cr0, r7, 0
+; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK: ori r5, r6, 0
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT: [[TRUE]]
+; CHECK-NEXT: addi r4, r3, 0
+; CHECK-NEXT:  [[SUCCESSOR]]
+; CHECK-NEXT: add r4, r4, r5
+; CHECK-NEXT: add r3, r3, r4
+; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELsTo0ORI2ADDIs
+  (i32 signext %a, i32 signext %b, i32 signext %d,
+   i32 signext %f, i32 signext %g) {
+entry:
+
+  %cmp = icmp sgt i32 %g, 0
+  %a.b = select i1 %cmp, i32 %a, i32 %b
+  %d.f = select i1 %cmp, i32 %d, i32 %f
+  %add1 = add nsw i32 %a.b, %d.f
+  %add2 = add nsw i32 %a, %add1
+  %sub1 = sub nsw i32 %add2, %d
+  ret i32 %sub1
+
+; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs
+; CHECK: cmpwi cr0, r7, 0
+; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT:  [[TRUE]]
+; CHECK-NEXT: addi r4, r3, 0
+; CHECK-NEXT: addi r6, r5, 0
+; CHECK-NEXT:  [[SUCCESSOR]]
+; CHECK-NEXT: add r4, r4, r6
+; CHECK-NEXT: add r3, r3, r4
+; CHECK-NEXT: subf r3, r5, r3
+; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: blr
+}
+
+
+@b = common local_unnamed_addr global i32 0, align 4
+@a = common local_unnamed_addr global i32 0, align 4
+; Function Attrs: norecurse nounwind readonly
+define signext i32 @testComplexISEL() #0 {
+entry:
+  %0 = load i32, i32* @b, align 4, !tbaa !1
+  %tobool = icmp eq i32 %0, 0
+  br i1 %tobool, label %if.end, label %cleanup
+
+if.end:
+  %1 = load i32, i32* @a, align 4, !tbaa !1
+  %conv = sext i32 %1 to i64
+  %2 = inttoptr i64 %conv to i32 (...)*
+  %cmp = icmp eq i32 (...)* %2, bitcast (i32 ()* @testComplexISEL to i32 (...)*)
+  %conv3 = zext i1 %cmp to i32
+  br label %cleanup
+
+cleanup:
+  %retval.0 = phi i32 [ %conv3, %if.end ], [ 1, %entry ]
+  ret i32 %retval.0
+
+; CHECK-LABEL: @testComplexISEL
+; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT:  [[TRUE]]
+; CHECK-NEXT: addi r3, r12, 0
+; CHECK-NEXT: [[SUCCESSOR]]
+; CHECK-NEXT: clrldi r3, r3, 32
+; CHECK-NEXT: blr
+}
+
+!1 = !{!2, !2, i64 0}
+!2 = !{!"int", !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C/C++ TBAA"}

test/CodeGen/PowerPC/fold-zero.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits | FileCheck %s
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck -check-prefix=CHECK-CRB %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck --check-prefix=CHECK-CRB %s
+; RUN: llc -verify-machineinstrs -ppc-gen-isel=false < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define i32 @test1(i1 %a, i32 %c) nounwind  {
   %x = select i1 %a, i32 %c, i32 0
   ret i32 %x
 
-; CHECK: @test1
+; CHECK-LABEL: @test1
 ; CHECK-NOT: li {{[0-9]+}}, 0
 ; CHECK: isel 3, 0,
 ; CHECK: blr
+; CHECK-NO-ISEL-LABEL: @test1
+; CHECK-NO-ISEL: li 3, 0
+; CHECK-NO-ISEL-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
+; CHECK-NO-ISEL-NEXT: blr
 }
 
 define i32 @test2(i1 %a, i32 %c) nounwind  {
   %x = select i1 %a, i32 0, i32 %c
   ret i32 %x
 
-; CHECK-CRB: @test2
+; CHECK-CRB-LABEL: @test2
 ; CHECK-CRB-NOT: li {{[0-9]+}}, 0
 ; CHECK-CRB: isel 3, 0,
 ; CHECK-CRB: blr
+; CHECK-NO-ISEL-LABEL: @test2
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 4, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: blr
 }
 

test/CodeGen/PowerPC/i1-ext-fold.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; Function Attrs: nounwind readnone
 define signext i32 @foo(i32 signext %a, i32 signext %b) #0 {
 entry:
   %cmp = icmp slt i32 %a, %b
   %conv = zext i1 %cmp to i32
   %shl = shl nuw nsw i32 %conv, 4
   ret i32 %shl
 
 ; CHECK-LABEL: @foo
+; CHECK-NO-ISEL-LABEL: @foo
 ; CHECK-DAG: cmpw
 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
 ; CHECK-DAG: li [[REG2:[0-9]+]], 16
 ; CHECK: isel 3, [[REG2]], [[REG1]],
 ; CHECK: blr
+
+; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 5, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 12, 0
+; CHECK-NO-ISEL-NEXT: blr
 }
 
 ; Function Attrs: nounwind readnone
 define signext i32 @foo2(i32 signext %a, i32 signext %b) #0 {
 entry:
   %cmp = icmp slt i32 %a, %b
   %conv = zext i1 %cmp to i32
   %shl = shl nuw nsw i32 %conv, 4
   %add1 = or i32 %shl, 5
   ret i32 %add1
 
 ; CHECK-LABEL: @foo2
+; CHECK-NO-ISEL-LABEL: @foo2
 ; CHECK-DAG: cmpw
 ; CHECK-DAG: li [[REG1:[0-9]+]], 5
 ; CHECK-DAG: li [[REG2:[0-9]+]], 21
 ; CHECK: isel 3, [[REG2]], [[REG1]],
 ; CHECK: blr
+
+; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 5, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 12, 0
+; CHECK-NO-ISEL-NEXT: blr
 }
 
 ; Function Attrs: nounwind readnone
 define signext i32 @foo3(i32 signext %a, i32 signext %b) #0 {
 entry:
   %cmp = icmp sle i32 %a, %b
   %conv = zext i1 %cmp to i32
   %shl = shl nuw nsw i32 %conv, 4
   ret i32 %shl
 
 ; CHECK-LABEL: @foo3
+; CHECK-NO-ISEL-LABEL: @foo3
 ; CHECK-DAG: cmpw
 ; CHECK-DAG: li [[REG1:[0-9]+]], 16
 ; CHECK: isel 3, 0, [[REG1]],
 ; CHECK: blr
+
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 5, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: blr
 }
 
 attributes #0 = { nounwind readnone }
 

test/CodeGen/PowerPC/i1-to-double.ll

 ; RUN: llc -verify-machineinstrs -march=ppc32 -mcpu=ppc32 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
 define double @test(i1 %X) {
         %Y = uitofp i1 %X to double
         ret double %Y
 }
 
 ; CHECK-LABEL: @test
 
 ; CHECK: andi. {{[0-9]+}}, 3, 1
-; CHECK: bc 12, 1,
-
-; CHECK: li 3, .LCP[[L1:[A-Z0-9_]+]]@l
-; CHECK: addis 3, 3, .LCP[[L1]]@ha
-; CHECK: lfs 1, 0(3)
-; CHECK: blr
-
-; CHECK: li 3, .LCP[[L2:[A-Z0-9_]+]]@l
-; CHECK: addis 3, 3, .LCP[[L2]]@ha
-; CHECK: lfs 1, 0(3)
-; CHECK: blr
-
+; CHECK-NEXT: addis 4, 4, .LCPI
+; CHECK-NEXT: addis 5, 5, .LCPI
+; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK: ori 3, 4, 0
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT: [[TRUE]]
+; CHECK-NEXT: addi 3, 5, 0
+; CHECK-NEXT: [[SUCCESSOR]]
+; CHECK-NEXT: lfs 1, 0(3)
+; CHECK-NEXT: blr

test/CodeGen/PowerPC/i64_fp_round.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -ppc-gen-isel=false < %s | FileCheck %s --check-prefix=CHECK-NO-ISEL
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define float @test(i64 %x) nounwind readnone {
 entry:
   %conv = sitofp i64 %x to float
   ret float %conv
 }
 
 ; Verify that we get the code sequence needed to avoid double-rounding.
 ; Note that only parts of the sequence are checked for here, to allow
 ; for minor code generation differences.
 
+;CHECK-LABEL: test
+;CHECK-NO-ISEL-LABEL: test
 ; CHECK: sradi [[REG1:[0-9]+]], 3, 53
 ; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1
 ; CHECK: cmpldi [[REG2]], 1
 ; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 11, 3, 0
+; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NO-ISEL-NEXT: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 11, 4, 0
 ; CHECK: std [[REG3]], -{{[0-9]+}}(1)
 
 
 ; Also check that with -enable-unsafe-fp-math we do not get that extra
 ; code sequence.  Simply verify that there is no "isel" present.
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK-UNSAFE
 ; CHECK-UNSAFE-NOT: isel
 

test/CodeGen/PowerPC/ifcvt.ll

 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) {
 entry:
   %sext82 = shl i32 %d, 16
   %conv29 = ashr exact i32 %sext82, 16
   %cmp = icmp slt i32 %sext82, 0
   br i1 %cmp, label %cond.true, label %cond.false
 
 cond.true:                                        ; preds = %sw.epilog
   %and33 = and i32 %conv29, 32767
   %sub34 = sub nsw i32 %a, %and33
   br label %cond.end
 
 cond.false:                                       ; preds = %sw.epilog
   %add37 = add nsw i32 %conv29, %a
   br label %cond.end
 
-; CHECK: @test
+; CHECK-LABEL: @test
+; CHECK-NO-ISEL-LABEL: @test
 ; CHECK: add [[REG:[0-9]+]], 
 ; CHECK: subf [[REG2:[0-9]+]],
 ; CHECK: isel {{[0-9]+}}, [[REG]], [[REG2]],
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 5, 6, 0
+; CHECK-NO-ISEL: extsh 5, 5
+; CHECK-NO-ISEL-NEXT: add 3, 3, 5
+; CHECK-NO-ISEL-NEXT: blr
 
 cond.end:                                         ; preds = %cond.false, %cond.true
   %cond = phi i32 [ %sub34, %cond.true ], [ %add37, %cond.false ]
   %sext83 = shl i32 %cond, 16
   %conv39 = ashr exact i32 %sext83, 16
   %add41 = sub i32 %b, %a
   %sub43 = add i32 %add41, %conv39
   ret i32 %sub43
 }
 

test/CodeGen/PowerPC/isel.ll

 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 ; RUN: llc -verify-machineinstrs -mcpu=a2 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 
 define i64 @test1(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %p = icmp uge i64 %a, %b
   %x = select i1 %p, i64 %c, i64 %d
   ret i64 %x
-; CHECK: @test1
+; CHECK-LABEL: @test1
+; CHECK-NO-ISEL-LABEL: @test1
 ; CHECK: isel
+; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 5, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 6, 0
+; CHECK-NO-ISEL-NEXT: blr
 }
 
 define i32 @test2(i32 %a, i32 %b, i32 %c, i32 %d) {
 entry:
   %p = icmp uge i32 %a, %b
   %x = select i1 %p, i32 %c, i32 %d
   ret i32 %x
-; CHECK: @test2
+; CHECK-LABEL: @test2
+; CHECK-NO-ISEL-LABEL: @test2
 ; CHECK: isel
+; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 5, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 6, 0
+; CHECK-NO-ISEL-NEXT: blr
 }
 

test/CodeGen/PowerPC/optcmp.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @foo(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 {
 entry:
   %sub = sub nsw i32 %a, %b
   store i32 %sub, i32* %c, align 4
   %cmp = icmp sgt i32 %a, %b

 define i64 @fool(i64 %a, i64 %b, i64* nocapture %c) #0 {
 entry:
   %sub = sub nsw i64 %a, %b
   store i64 %sub, i64* %c, align 8
   %cmp = icmp sgt i64 %a, %b
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 
-; CHECK: @fool
+; CHECK-LABEL: @fool
+; CHECK-NO-ISEL-LABEL: @fool
 ; CHECK: subf. [[REG:[0-9]+]], 4, 3
 ; CHECK: isel 3, 3, 4, 1
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 4, 0
+; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
+
 ; CHECK: std [[REG]], 0(5)
 }
 
 define i64 @foolb(i64 %a, i64 %b, i64* nocapture %c) #0 {
 entry:
   %sub = sub nsw i64 %a, %b
   store i64 %sub, i64* %c, align 8
   %cmp = icmp sle i64 %a, %b
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 
-; CHECK: @foolb
+; CHECK-LABEL: @foolb
+; CHECK-NO-ISEL-LABEL: @foolb
 ; CHECK: subf. [[REG:[0-9]+]], 4, 3
 ; CHECK: isel 3, 4, 3, 1
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL-NEXT: b .LBB
+; CHECK-NO-ISEL addi: 3, 4, 0
 ; CHECK: std [[REG]], 0(5)
 }
 
 define i64 @foolc(i64 %a, i64 %b, i64* nocapture %c) #0 {
 entry:
   %sub = sub nsw i64 %b, %a
   store i64 %sub, i64* %c, align 8
   %cmp = icmp sgt i64 %a, %b
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 
-; CHECK: @foolc
+; CHECK-LABEL: @foolc
+; CHECK-NO-ISEL-LABEL: @foolc
 ; CHECK: subf. [[REG:[0-9]+]], 3, 4
 ; CHECK: isel 3, 3, 4, 0
+; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 4, 0
+; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK: std [[REG]], 0(5)
 }
 
 define i64 @foold(i64 %a, i64 %b, i64* nocapture %c) #0 {
 entry:
   %sub = sub nsw i64 %b, %a
   store i64 %sub, i64* %c, align 8
   %cmp = icmp slt i64 %a, %b
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 
-; CHECK: @foold
+; CHECK-LABEL: @foold
+; CHECK-NO-ISEL-LABEL: @foold
 ; CHECK: subf. [[REG:[0-9]+]], 3, 4
 ; CHECK: isel 3, 3, 4, 1
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 4, 0
+; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK: std [[REG]], 0(5)
 }
 
 define i64 @foold2(i64 %a, i64 %b, i64* nocapture %c) #0 {
 entry:
   %sub = sub nsw i64 %a, %b
   store i64 %sub, i64* %c, align 8
   %cmp = icmp slt i64 %a, %b
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 
-; CHECK: @foold2
+; CHECK-LABEL: @foold2
+; CHECK-NO-ISEL-LABEL: @foold2
 ; CHECK: subf. [[REG:[0-9]+]], 4, 3
 ; CHECK: isel 3, 3, 4, 0
+; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 4, 0
+; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK: std [[REG]], 0(5)
 }
 
 define i64 @foo2l(i64 %a, i64 %b, i64* nocapture %c) #0 {
 entry:
   %shl = shl i64 %a, %b
   store i64 %shl, i64* %c, align 8
   %cmp = icmp sgt i64 %shl, 0

test/CodeGen/PowerPC/p8-isel-sched.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; Function Attrs: nounwind
 define void @foo(i32* nocapture %r1, i32* nocapture %r2, i32* nocapture %r3, i32* nocapture %r4, i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) #0 {
 entry:
   %tobool = icmp ne i32 %a, 0
   %cond = select i1 %tobool, i32 %b, i32 %c
entry:
   %cond17 = select i1 %tobool, i32 %add13, i32 %sub15
   store i32 %cond17, i32* %r4, align 4
   ret void
 }
 
 ; Make sure that we don't schedule all of the isels together, they should be
 ; intermixed with the adds because each isel starts a new dispatch group.
 ; CHECK-LABEL: @foo
+; CHECK-NO-ISEL-LABEL: @foo
 ; CHECK: isel
+; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 7, 12, 0
+; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 7, 11, 0
 ; CHECK: addi
 ; CHECK: isel
+; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 10, 11, 0
+; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 10, 12, 0
 ; CHECK: blr
 
 attributes #0 = { nounwind }
-

test/CodeGen/PowerPC/ppc-crbits-onoff.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; Function Attrs: nounwind readnone
 define signext i32 @crbitsoff(i32 signext %v1, i32 signext %v2) #0 {
 entry:
   %tobool = icmp ne i32 %v1, 0
   %lnot = icmp eq i32 %v2, 0
   %and3 = and i1 %tobool, %lnot
   %and = zext i1 %and3 to i32
   ret i32 %and
 
 ; CHECK-LABEL: @crbitsoff
+; CHECK-NO-ISEL-LABEL: @crbitsoff
 ; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 0
 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
 ; CHECK-DAG: cntlzw [[REG3:[0-9]+]],
 ; CHECK: isel [[REG4:[0-9]+]], 0, [[REG2]]
+; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 4, 5, 0
+; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 4, 0, 0
 ; CHECK: and 3, [[REG4]], [[REG3]]
 ; CHECK: blr
 }
 
 define signext i32 @crbitson(i32 signext %v1, i32 signext %v2) #1 {
 entry:
   %tobool = icmp ne i32 %v1, 0
   %lnot = icmp eq i32 %v2, 0
   %and3 = and i1 %tobool, %lnot
   %and = zext i1 %and3 to i32
   ret i32 %and
 
 ; CHECK-LABEL: @crbitson
+; CHECK-NO-ISEL-LABEL: @crbitson
 ; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 0
 ; CHECK-DAG: cmpwi {{[0-9]+}}, 4, 0
 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
 ; CHECK-DAG: crorc [[REG3:[0-9]+]],
 ; CHECK: isel 3, 0, [[REG2]], [[REG3]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 
 attributes #0 = { nounwind readnone "target-features"="-crbits" }
 attributes #1 = { nounwind readnone }
 

test/CodeGen/PowerPC/select-i1-vs-i1.ll

 ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; FIXME: We should check the operands to the cr* logical operation itself, but
 ; unfortunately, FileCheck does not yet understand how to do arithmetic, so we
 ; can't do so without introducing a register-allocation dependency.
 
 define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
   %cmp3tmp = icmp eq i32 %c1, %c2
   %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i32 %a1, i32 %a2
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32slt
+; CHECK-NO-ISEL-LABEL: @testi32slt
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define signext i32 @testi32ult(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
   %cmp3tmp = icmp eq i32 %c1, %c2
   %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i32 %a1, i32 %a2
   ret i32 %cond
 
-; CHECK-LABEL: @testi32ult
+; CHECK-NO-ISEL-LABEL: @testi32ult
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
   %cmp3tmp = icmp eq i32 %c1, %c2
   %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i32 %a1, i32 %a2
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32sle
+; CHECK-NO-ISEL-LABEL: @testi32sle
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define signext i32 @testi32ule(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
   %cmp3tmp = icmp eq i32 %c1, %c2
   %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i32 %a1, i32 %a2
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32ule
+; CHECK-NO-ISEL-LABEL: @testi32ule
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define signext i32 @testi32eq(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
   %cmp3tmp = icmp eq i32 %c1, %c2
   %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i32 %a1, i32 %a2
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32eq
+; CHECK-NO-ISEL-LABEL: @testi32eq
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
   %cmp3tmp = icmp eq i32 %c1, %c2
   %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i32 %a1, i32 %a2
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32sge
+; CHECK-NO-ISEL-LABEL: @testi32sge
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define signext i32 @testi32uge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
   %cmp3tmp = icmp eq i32 %c1, %c2
   %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i32 %a1, i32 %a2
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32uge
+; CHECK-NO-ISEL-LABEL: @testi32uge
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
   %cmp3tmp = icmp eq i32 %c1, %c2
   %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i32 %a1, i32 %a2
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32sgt
+; CHECK-NO-ISEL-LABEL: @testi32sgt
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define signext i32 @testi32ugt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
   %cmp3tmp = icmp eq i32 %c1, %c2
   %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i32 %a1, i32 %a2
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32ugt
+; CHECK-NO-ISEL-LABEL: @testi32ugt
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define signext i32 @testi32ne(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
   %cmp3tmp = icmp eq i32 %c1, %c2
   %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i32 %a1, i32 %a2
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32ne
+; CHECK-NO-ISEL-LABEL: @testi32ne
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
   %cmp3tmp = icmp eq i64 %c1, %c2
   %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i64 %a1, i64 %a2
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64slt
+; CHECK-NO-ISEL-LABEL: @testi64slt
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define i64 @testi64ult(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
   %cmp3tmp = icmp eq i64 %c1, %c2
   %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i64 %a1, i64 %a2
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64ult
+; CHECK-NO-ISEL-LABEL: @testi64ult
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define i64 @testi64sle(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
   %cmp3tmp = icmp eq i64 %c1, %c2
   %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i64 %a1, i64 %a2
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64sle
+; CHECK-NO-ISEL-LABEL: @testi64sle
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define i64 @testi64ule(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
   %cmp3tmp = icmp eq i64 %c1, %c2
   %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i64 %a1, i64 %a2
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64ule
+; CHECK-NO-ISEL-LABEL: @testi64ule
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define i64 @testi64eq(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
   %cmp3tmp = icmp eq i64 %c1, %c2
   %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i64 %a1, i64 %a2
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64eq
+; CHECK-NO-ISEL-LABEL: @testi64eq
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define i64 @testi64sge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
   %cmp3tmp = icmp eq i64 %c1, %c2
   %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i64 %a1, i64 %a2
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64sge
+; CHECK-NO-ISEL-LABEL: @testi64sge
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define i64 @testi64uge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
   %cmp3tmp = icmp eq i64 %c1, %c2
   %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i64 %a1, i64 %a2
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64uge
+; CHECK-NO-ISEL-LABEL: @testi64uge
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define i64 @testi64sgt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
   %cmp3tmp = icmp eq i64 %c1, %c2
   %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i64 %a1, i64 %a2
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64sgt
+; CHECK-NO-ISEL-LABEL: @testi64sgt
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define i64 @testi64ugt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
   %cmp3tmp = icmp eq i64 %c1, %c2
   %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i64 %a1, i64 %a2
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64ugt
+; CHECK-NO-ISEL-LABEL: @testi64ugt
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define i64 @testi64ne(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
   %cmp3tmp = icmp eq i64 %c1, %c2
   %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, i64 %a1, i64 %a2
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64ne
+; CHECK-NO-ISEL-LABEL: @testi64ne
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 define float @testfloatslt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp slt i1 %cmp3tmp, %cmp1

test/CodeGen/PowerPC/subreg-postra-2.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; Function Attrs: nounwind
 define void @jbd2_journal_commit_transaction(i32 %input1, i32* %input2, i32* %input3, i8** %input4) #0 {
 entry:
   br label %while.body392
 
wait_on_buffer.exit1319:                          ; preds = %while.body392
   br i1 %cmp.i1312, label %while.end418, label %while.body392
 
 while.end418:                                     ; preds = %wait_on_buffer.exit1319, %do.body378
   %err.4.lcssa = phi i32 [ %ivar, %while.body392 ], [ %.err.4, %wait_on_buffer.exit1319 ]
   %tobool419 = icmp eq i32 %err.4.lcssa, 0
   br i1 %tobool419, label %if.end421, label %if.then420
 
 ; CHECK-LABEL: @jbd2_journal_commit_transaction
+; CHECK-NO-ISEL-LABEL: @jbd2_journal_commit_transaction
 ; CHECK: andi.
 ; CHECK: crmove [[REG:[0-9]+]], 1
 ; CHECK: stdcx.
 ; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 4, 7, 0
+; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 4, 3, 0
 
 if.then420:                                       ; preds = %while.end418
   unreachable
 
 if.end421:                                        ; preds = %while.end418
   unreachable
 
 }
 
 attributes #0 = { nounwind }
 

test/CodeGen/PowerPC/subreg-postra.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; Function Attrs: nounwind
 define void @jbd2_journal_commit_transaction(i32* %journal, i64 %inp1, i32 %inp2,
                                              i32* %inp3, i32** %inp4,
                                              i32** %inp5, i1 %inp6,
                                              i1 %inp7, i1 %inp8) #0 {
wait_on_buffer.exit1319:                          ; preds = %while.body392
   %2 = call i64 asm sideeffect "1:.long 0x7c0000a8 $| ((($0) & 0x1f) << 21) $| (((0) & 0x1f) << 16) $| ((($3) & 0x1f) << 11) $| (((0) & 0x1) << 0) \0Aandc $0,$0,$2\0Astdcx. $0,0,$3\0Abne- 1b\0A", "=&r,=*m,r,r,*m,~{cc},~{memory}"(i64* %b_state.i.i1314, i64 262144, i64* %b_state.i.i1314, i64* %b_state.i.i1314) #1
   %prev.i.i.i1325 = getelementptr inbounds i8, i8* %0, i64 8
   %3 = load i32*, i32** %inp4, align 8
   store i32* %3, i32** %inp5, align 8
   call void @__brelse(i32* %3) #1
   br i1 %inp8, label %while.end418, label %while.body392
 
 ; CHECK-LABEL: @jbd2_journal_commit_transaction
+; CHECK-NO-ISEL-LABEL: @jbd2_journal_commit_transaction
 ; CHECK: andi.
 ; CHECK: crmove
 ; CHECK: stdcx.
 ; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}},
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 30, 3, 0
+; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
+
 
 while.end418:                                     ; preds = %wait_on_buffer.exit1319, %do.body378
   %err.4.lcssa = phi i32 [ %inp2, %do.body378 ], [ %.err.4, %wait_on_buffer.exit1319 ]
   br i1 %inp7, label %if.end421, label %if.then420
 
 if.then420:                                       ; preds = %while.end418
   call void @jbd2_journal_abort(i32* %journal, i32 signext %err.4.lcssa) #1
   br label %if.end421