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[ARM] Add support for embedded position-independent code
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Authored by olista01 on Aug 5 2016, 3:32 AM.

Details

Summary

This patch adds support for some new relocation models to the ARM
backend:

  • Read-only position independence (ROPI): Code and read-only data is accessed PC-relative. The offsets between all code and RO data sections are known at static link time. This does not affect read-write data.
  • Read-write position independence (RWPI): Read-write data is accessed relative to the static base register (r9). The offsets between all writeable data sections are known at static link time. This does not affect read-only data.

These two modes are independent (they specify how different objects
should be addressed), so they can be used individually or together. They
are otherwise the same as the "static" relocation model, and are not
compatible with SysV-style PIC using a global offset table.

These modes are normally used by bare-metal systems or systems with
small real-time operating systems. They are designed to avoid the need
for a dynamic linker, the only initialisation required is setting r9 to
an appropriate value for RWPI code.

I have only added support to SelectionDAG, not FastISel, because
FastISel is currently disabled for bare-metal targets where these modes
would be used.

Diff Detail

Repository
rL LLVM

Event Timeline

olista01 updated this revision to Diff 66919.Aug 5 2016, 3:32 AM
olista01 retitled this revision from to [ARM] Add support for embedded position-independent code.
olista01 updated this object.
olista01 set the repository for this revision to rL LLVM.
olista01 added a subscriber: llvm-commits.
t.p.northover edited edge metadata.Aug 5 2016, 7:26 AM

A surprisingly simple addition!

I see you've skipped SjLj exceptions and stack guards support. I think this is fine, but could you put "unsupported" assertions in at least the stack guard code (*InstrInfo.cpp)? I have less worries about SjLj because no-one should be using that voluntarily anyway.

Similarly, could we have an assertion on non-ELF targets about RWPI (in getEffectiveRelocModel or something)? It looks to me like ROPI would work but MachO certainly doesn't have the required relocations for RWPI and if COFF has them, they're not supported yet.

You also seem to have no tests for the build attributes?

test/CodeGen/ARM/arm-position-independence-jump-table.ll
3–7 ↗(On Diff #66919)

Have you tried disabling machine block placement (-disable-block-placement) and/or other things that mess around with the code?

If that fails, it would be more efficient to only run llc once (to a temporary file) and then FileCheck that repeatedly:

; RUN: llc <whatever> -o %t
; RUN: FileCheck %s --check-prefix=Whatever < %t
...

Actually, sorry, there's no ROPI support in LowerGlobalAddressDarwin (or whatever) so the assertion should cover both on non-ELF.

olista01 updated this revision to Diff 66958.Aug 5 2016, 8:12 AM
olista01 edited edge metadata.
olista01 removed rL LLVM as the repository for this revision.
  • Added assertions for unsupported object formats and features
  • Added tests for build attributes
  • Simplified jump table test
weimingz edited edge metadata.Aug 5 2016, 10:24 AM

Thanks Oliver!

I reviewed the ARMISelLowering part and it LGTM.

lib/Target/ARM/ARMAsmPrinter.cpp
728 ↗(On Diff #66958)

Nitpick: period at end of comment? same for line 738, 744 etc.

olista01 updated this revision to Diff 67134.Aug 8 2016, 2:18 AM
olista01 edited edge metadata.

Added periods at ends of comments.

t.p.northover accepted this revision.Aug 8 2016, 8:13 AM
t.p.northover edited edge metadata.

Thanks Oliver! This looks fine to me.

This revision is now accepted and ready to land.Aug 8 2016, 8:13 AM
This revision was automatically updated to reflect the committed changes.
eugenis added a subscriber: eugenis.Feb 8 2017, 3:13 PM
eugenis added inline comments.
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
2804

What if GV points inside GA->getBaseObject() with non-zero offset?
See https://llvm.org/bugs/show_bug.cgi?id=31896

eugenis added inline comments.Feb 8 2017, 3:36 PM
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
2804

Oh, and even if there is no offset, this is still wrong, because the alias may have different linkage and visibility compared to the aliasee.

pcc added a subscriber: pcc.Feb 8 2017, 3:41 PM