[X86] Accept SELECT op code for x86-64 fp128 type

[chh]

Summary

DAGTypeLegalizer::CanSkipSoftenFloatOperand should allow SELECT op code for x86_64 fp128 type.
Without this patch, the test case fp128-select.ll fails in SoftenFloatOperand because the new
ISD::SELECT generated by llvm is not skipped in CanSkipSoftenFloatOperand.

This bug was found when compiling some compiler-rt code for Android x86-64 target.

[chh]

Ping.

[RKSimon]

test/CodeGen/X86/fp128-select.ll

17 ↗

(On Diff #61988)

Please can you regenerate this with utils/update_llc_test_checks.py or at least improve the checks so that the branch is more obvious.

[chh]

Regenerated test file with utils/update_llc_test_checks.py.

[chh]

Regenerated fp128-select.ll.

[chh]

Ping.

[RKSimon]

Please can you test on at least one other target where fp128 is not legal?

test/CodeGen/X86/fp128-select.ll

3 ↗

(On Diff #62959)

You shouldn't need to specify mmx here

[chh]

Add test cases for both MMX and non-MMX targets.

[chh]

I added test cases for non-MMX cases.
I think non-fp128 types should already be covered in other tests.
So far this patch is to fix the only problem I know with fp128 type on x86-64 targets with MMX.

test/CodeGen/X86/fp128-select.ll

3 ↗

(On Diff #62959)

The problem only happens on x86-64 targets that use 128 bits for long double and with mmx.
Now I added both mmx and non-mmx tests.

[RKSimon]

LGTM

llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

bool DAGTypeLegalizer::CanSkipSoftenFloatOperand(SDNode *N, unsigned OpNo) {
   switch (N->getOpcode()) {
     case ISD::ConstantFP:
     case ISD::CopyFromReg:
     case ISD::CopyToReg:
     case ISD::FABS:
     case ISD::FCOPYSIGN:
     case ISD::FNEG:
     case ISD::Register:
+    case ISD::SELECT:
       return true;
   }
   return false;
 }
 
 SDValue DAGTypeLegalizer::SoftenFloatOp_BITCAST(SDNode *N) {
   return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
                      GetSoftenedFloat(N->getOperand(0)));

llvm/trunk/test/CodeGen/X86/fp128-select.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx | FileCheck %s --check-prefix=MMX
+; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx | FileCheck %s --check-prefix=MMX
+; RUN: llc < %s -O2 -mtriple=x86_64-linux-android | FileCheck %s
+; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu | FileCheck %s
+
+define void @test_select(fp128* %p, fp128* %q, i1 zeroext %c) {
+; MMX-LABEL: test_select:
+; MMX:       # BB#0:
+; MMX-NEXT:    testb %dl, %dl
+; MMX-NEXT:    jne .LBB0_1
+; MMX-NEXT:  # BB#2:
+; MMX-NEXT:    movaps {{.*}}(%rip), %xmm0
+; MMX-NEXT:    movaps %xmm0, (%rsi)
+; MMX-NEXT:    retq
+; MMX-NEXT:  .LBB0_1:
+; MMX-NEXT:    movaps (%rdi), %xmm0
+; MMX-NEXT:    movaps %xmm0, (%rsi)
+; MMX-NEXT:    retq
+;
+; CHECK-LABEL: test_select:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    testb %dl, %dl
+; CHECK-NEXT:    cmovneq (%rdi), %rax
+; CHECK-NEXT:    movabsq $9223231299366420480, %rcx # imm = 0x7FFF800000000000
+; CHECK-NEXT:    cmovneq 8(%rdi), %rcx
+; CHECK-NEXT:    movq %rcx, 8(%rsi)
+; CHECK-NEXT:    movq %rax, (%rsi)
+; CHECK-NEXT:    retq
+  %a = load fp128, fp128* %p, align 2
+  %r = select i1 %c, fp128 %a, fp128 0xL00000000000000007FFF800000000000
+  store fp128 %r, fp128* %q
+  ret void
+}