Add ARM subtarget feature +long64

[pirama]

Summary

This patch adds an ARM subtarget feature +long64 to request that long
datatype's width and alignment be 64-bits.

Tests included in accompanying patch to Clang.

[kristof.beyls]

http://reviews.llvm.org/D20709 is where the review happens for the clang side of this patch.

See also my comments on that ticket.

When using the long-is-64-bits-abi-variant introduced in this patch, code generation must change. I think there should be tests for this as part of this patch.

I don't understand how this patch can change code generation. Did you forget to add some changes to this patch, or am I missing something?

[t.p.northover]

The only thing I know of that "long" could affect is the libcalls we produce, but as far as I'm aware the only dodgy cases are specified in terms of size_t and ptrdiff_t.

Those types vary completely independently of "long" (on some platforms they're "long", on others "long long").

[rengolin]

In D20708#443944, @t.p.northover wrote:

The only thing I know of that "long" could affect is the libcalls we produce, but as far as I'm aware the only dodgy cases are specified in terms of size_t and ptrdiff_t.

Those types vary completely independently of "long" (on some platforms they're "long", on others "long long").

I commented on D20709 that this might be better as a proper ABI, but even in the case we don't do that, having this flag should be mostly harmless.

Users won't have a way to set it without calling CC1 directly, and if they do, than whatever lib calls they were expecting to work has to know about the new sizes/alignments.

cheers,
--renato

[pirama]

Abandoning this revision as the required behavior can be achieved without a change to the backend.

lib/Target/ARM/ARM.td

 def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
                                         "Reserve R9, making it unavailable as "
                                         "GPR">;
 
 def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
                                      "Don't use movt/movw pairs for 32-bit "
                                      "imms">;
 
+def FeatureLong64 : SubtargetFeature<"long64", "UseLong64",
+                                     "true",
+                                     "long type is forced to be 64-bit">;
+
 
 //===----------------------------------------------------------------------===//
 // ARM ISAa.
 //
 
 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
                                    "Support ARM v4T instructions">;
 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",

lib/Target/ARM/ARMSubtarget.h

protected:
   bool UseNaClTrap;
 
   /// Generate calls via indirect call instructions.
   bool GenLongCalls;
 
   /// Target machine allowed unsafe FP math (such as use of NEON fp)
   bool UnsafeFPMath;
 
+  /// Force long to be 64-bit type
+  bool UseLong64;
+
   /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
   bool UseSjLjEH;
 
   /// stackAlignment - The minimum alignment known to hold of the stack frame on
   /// entry to the function and which must be maintained by every function.
   unsigned stackAlignment;
 
   /// CPUString - String name of used CPU.

lib/Target/ARM/ARMSubtarget.cpp

void ARMSubtarget::initializeEnvironment() {
   HasCrypto = false;
   HasCRC = false;
   HasZeroCycleZeroing = false;
   StrictAlign = false;
   HasDSP = false;
   UseNaClTrap = false;
   GenLongCalls = false;
   UnsafeFPMath = false;
+  UseLong64 = false;
   HasV7Clrex = false;
   HasAcquireRelease = false;
 
   // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
   // directly from it, but we can try to make sure they're consistent when both
   // available.
   UseSjLjEH = isTargetDarwin() && !isTargetWatchABI();
   assert((!TM.getMCAsmInfo() ||