[X86] Don't zero/sign-extend i1 or i8 return values to 32 bits (PR22532)

[hans]

Summary

This brings us in line with GCC and MSVC behaviour, and saves on code size.

We were already not extending i1 return values to on x86_64 after [0].

The ABI docs are unclear about this situation. The new i386 psABI [1] clearly states (Table 2.4, page 14) that i1, i8, and i16 return values do not need to be extended beyond 8 bits (GCC and MSVC do extend 16-bit values though, so I'm holding off on that). The old i386 psABI [2] does not mention this. I can't find mention of this in the x86_64 ABI [3], but there is a proposal on [4] that matches the behaviour in this patch.

Please let me know what you think.

[0]. http://llvm.org/viewvc/llvm-project?view=revision&revision=127766
[1]. https://01.org/sites/default/files/file_attach/intel386-psabi-1.0.pdf
[2]. https://refspecs.linuxfoundation.org/elf/abi386-4.pdf
[3]. https://refspecs.linuxfoundation.org/elf/x86_64-abi-0.98.pdf
[4]. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=46942#c4

[hans]

+Cameron who touched this last.

[hans]

I can't find mention of this in the x86_64 ABI.

After looking some more, it *is* mentioned in a newer version of the document: [1, Footnote 16 on Page 23]: "Other bits are left unspecified, hence the consumer side of those values can rely on it being 0 or 1 when truncated to 8 bit.", so I suppose that's where LLVM's current special-casing of i1 on x86_64 comes from.

[1]. https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-r249.pdf

[spatel]

cc'ing some Intel folks both for clarity on the ABI doc and for the potential perf impact.

[hans]

In D16907#345277, @spatel wrote:

cc'ing some Intel folks both for clarity on the ABI doc and for the potential perf impact.

Thanks. I've also raised this on the x86-64-abi mailing list: https://groups.google.com/d/msg/x86-64-abi/E8O33onbnGQ/gecUVGYzDQAJ

But for this specific patch, GCC's and MSVC's behaviours seem very clear, so I'm hoping this one is fairly non-controversial :-)

[majnemer]

This looks fine to me.
It would be good to have another pair of eyes confirm my opinion :)

[spatel]

In D16907#345285, @hans wrote:

In D16907#345277, @spatel wrote:

cc'ing some Intel folks both for clarity on the ABI doc and for the potential perf impact.

Thanks. I've also raised this on the x86-64-abi mailing list: https://groups.google.com/d/msg/x86-64-abi/E8O33onbnGQ/gecUVGYzDQAJ

But for this specific patch, GCC's and MSVC's behaviours seem very clear, so I'm hoping this one is fairly non-controversial :-)

I hope it's non-controversial too, but I'm very curious to know if this impacts big-core Intel perf. :)

If I'm reading H.J.'s proposal correctly, we should treat shorts the same as char/bool. Should it all be fixed in one shot?

test/CodeGen/X86/tail-call-attrs.ll

13–16

This comment doesn't apply anymore?

[jyknight]

Why do you say GCC extends 16-bit numbers?

Given:

short global1, global2;
short bar() {
  return global1 + global2;
}

$ gcc -march=i386 -O2 -S -o - -m32

Results in:

bar:
      movw    global2, %ax
      addw    global1, %ax
      ret

If you use -march=i686, then it results in:

bar:
      movzwl  global2, %eax
      addw    global1, %ax
      ret

[hans]

In D16907#345419, @jyknight wrote:

Why do you say GCC extends 16-bit numbers?

Given:

short global1, global2;
short bar() {
  return global1 + global2;
}

$ gcc -march=i386 -O2 -S -o - -m32

Results in:

bar:
      movw    global2, %ax
      addw    global1, %ax
      ret

If you use -march=i686, then it results in:

bar:
      movzwl  global2, %eax
      addw    global1, %ax
      ret

D'oh, I was holding it wrong.

I was using the same test case I used for bool and char, something like "return x == y", and GCC would use "sete" and then extend that to 32-bit, because that's easy and they have to extend the result anyway. Your test case is obviously better.

David and I also observed MSVC not extending 16-bit return values for this code:

unsigned short f(unsigned short x) {
  return x;
}

where they generate:

00000000: 66 8B 44 24 04     mov         ax,word ptr [esp+4]
00000005: C3                 ret

i.e. they're leaving the high 16 bits of eax undefined.

I'll update the patch to do shorts as well.

(Another interesting note is that MSVC's behaviour is contradictory to what they say in this document: https://msdn.microsoft.com/en-us/library/984x0h58.aspx "On x86 plaftorms, all arguments are widened to 32 bits when they are passed. Return values are also *widened to 32 bits and returned in the EAX register*.")

In D16907#345407, @spatel wrote:

If I'm reading H.J.'s proposal correctly, we should treat shorts the same as char/bool. Should it all be fixed in one shot?

Yes, since James pointed out my doubts about i16 behaviour were unfounded, let's do them all in one shot.

test/CodeGen/X86/tail-call-attrs.ll

13–16

Right. I'll add a FIXME here. The tail call lowering needs an update.

[hans]

Updating the patch to do i16 as well.

(I didn't update the title because I think it tends to break the email thread.)

[zansari]

In D16907#345277, @spatel wrote:

cc'ing some Intel folks both for clarity on the ABI doc and for the potential perf impact.

Well, there's always the potential for the non-extending move into the partial return register to create a false dependency with any prior writes to the whole register, however, you could argue that this isn't the place to deal with that since that's a more general issue ... maybe.

For example, take something like this:

short foo(void);
int bar(short, short);
short x, y = 123;
int A;

main()
{
  int i;
  for (i = 0; i <= 0xfffffff; i++) {
    A = bar(x, y);
    x = foo();
  }
  printf("\nA = %d, x = %x.\n", A, x);
  return 0;
}
-----------------------------
extern short x;
extern short y;

int bar(short a, short b)
{
  return a / b;
}

short foo(void)
{
  return x + y;
}

Foo will be slowed down a bit on a write to %al, whereas, there will be no dependency with a movzbl into %eax (I tried this real quick on an IVB, and it's ~50% faster with the movz, or an xor of eax before the movb).

We could play it safe and only do this for opt/min-size, or go ahead with this if the impact is low and deal with any potential performance issue in a more general way. Have we done any perf tests on this to see if there's any impact?

[spatel]

In D16907#345786, @zansari wrote:

We could play it safe and only do this for opt/min-size, or go ahead with this if the impact is low and deal with any potential performance issue in a more general way. Have we done any perf tests on this to see if there's any impact?

I haven't run any perf tests, but I thought it would be good to alert people about this change since there might be some diffs.

I agree that dealing with any perf issue as a separate pass is the better option, and Kevin mentioned some progress on that here:
http://lists.llvm.org/pipermail/llvm-dev/2016-February/094745.html

This patch LGTM; it's just trying to match the ABI's mandates and as noted, makes LLVM behave more like GCC/MSVC by default.

[hans]

Committed in r260133.

docs/LangRef.rst

 Note that any attributes for the function result (``nounwind``,
 ``readonly``) come immediately after the argument list.
 
 Currently, only the following parameter attributes are defined:
 
 ``zeroext``
     This indicates to the code generator that the parameter or return
     value should be zero-extended to the extent required by the target's
-    ABI (which is usually 32-bits, but is 8-bits for a i1 on x86-64) by
-    the caller (for a parameter) or the callee (for a return value).
+    ABI by the caller (for a parameter) or the callee (for a return value).
 ``signext``
     This indicates to the code generator that the parameter or return
     value should be sign-extended to the extent required by the target's
     ABI (which is usually 32-bits) by the caller (for a parameter) or
     the callee (for a return value).
 ``inreg``
     This indicates that this parameter or return value should be treated
     in a special target-dependent fashion while emitting code for

include/llvm/Target/TargetLowering.h

public:
   /// global variables extension. There is no target-independent behaviour
   /// so the default action is to bail.
   virtual unsigned getRegisterByName(const char* RegName, EVT VT,
                                      SelectionDAG &DAG) const {
     report_fatal_error("Named registers not implemented for this target");
   }
 
   /// Return the type that should be used to zero or sign extend a
-  /// zeroext/signext integer argument or return value.  FIXME: Most C calling
-  /// convention requires the return type to be promoted, but this is not true
-  /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
-  /// calling conventions. The frontend should handle this and include all of
-  /// the necessary information.
-  virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
+  /// zeroext/signext integer return value.  FIXME: Some C calling conventions
+  /// require the return type to be promoted, but this is not true all the time,
+  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
+  /// conventions. The frontend should handle this and include all of the
+  /// necessary information.
+  virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
                                        ISD::NodeType /*ExtendKind*/) const {
     EVT MinVT = getRegisterType(Context, MVT::i32);
     return VT.bitsLT(MinVT) ? MinVT : VT;
   }
 
   /// For some targets, an LLVM struct type must be broken down into multiple
   /// simple types, but the calling convention specifies that the entire struct
   /// must be passed in a block of consecutive registers.

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

if (NumValues) {
       LLVMContext &Context = F->getContext();
       bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
                                                       Attribute::InReg);
 
       for (unsigned j = 0; j != NumValues; ++j) {
         EVT VT = ValueVTs[j];
 
         if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
-          VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
+          VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind);
 
         unsigned NumParts = TLI.getNumRegisters(Context, VT);
         MVT PartVT = TLI.getRegisterType(Context, VT);
         SmallVector<SDValue, 4> Parts(NumParts);
         getCopyToParts(DAG, getCurSDLoc(),
                        SDValue(RetOp.getNode(), RetOp.getResNo() + j),
                        &Parts[0], NumParts, PartVT, &I, ExtendKind);
 

lib/Target/X86/X86ISelLowering.h

private:
     void insertCopiesSplitCSR(
       MachineBasicBlock *Entry,
       const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
 
     bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
 
     bool mayBeEmittedAsTailCall(CallInst *CI) const override;
 
-    EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
-                                 ISD::NodeType ExtendKind) const override;
+    EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
 
     bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                         bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
                         LLVMContext &Context) const override;
 
     const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
 

lib/Target/X86/X86ISelLowering.cpp

bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
 
   if (!HasRet)
     return false;
 
   Chain = TCChain;
   return true;
 }
 
-EVT
-X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
-                                            ISD::NodeType ExtendKind) const {
-  MVT ReturnMVT;
-  // TODO: Is this also valid on 32-bit?
-  if (Subtarget.is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
+EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
+  MVT ReturnMVT = MVT::i32;
+
+  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) {
+    // The ABI does not require i1, i8 or i16 to be extended.
     ReturnMVT = MVT::i8;
-  else
-    ReturnMVT = MVT::i32;
+  }
 
   EVT MinVT = getRegisterType(Context, ReturnMVT);
   return VT.bitsLT(MinVT) ? MinVT : VT;
 }
 
 /// Lower the result values of a call into the
 /// appropriate copies out of appropriate physical registers.
 ///

test/CodeGen/X86/2007-08-10-SignExtSubreg.ll

 ; RUN: llc < %s -march=x86 | grep "movsbl"
 
 @X = global i32 0               ; <i32*> [#uses=1]
 
-define signext i8 @_Z3fooi(i32 %x)   {
+define i32 @_Z3fooi(i32 %x)   {
 entry:
         store i32 %x, i32* @X, align 4
         %retval67 = trunc i32 %x to i8          ; <i8> [#uses=1]
-        ret i8 %retval67
+        %retval = sext i8 %retval67 to i32
+        ret i32 %retval
 }

test/CodeGen/X86/3addr-16bit.ll

 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -asm-verbose=false | FileCheck %s -check-prefix=64BIT
 ; rdar://7329206
 
 ; In 32-bit the partial register stall would degrade performance.
 
 define zeroext i16 @t1(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
 ; 32BIT-LABEL:     t1:
 ; 32BIT:     movw 20(%esp), %ax
 ; 32BIT-NOT: movw %ax, %cx
 ; 32BIT:     leal 1(%eax), %ecx
 
 ; 64BIT-LABEL:     t1:
 ; 64BIT-NOT: movw %si, %ax
-; 64BIT:     leal 1(%rsi), %eax
+; 64BIT:     leal 1(%rsi), %ebx
   %0 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
   %1 = add i16 %k, 1                              ; <i16> [#uses=3]
   br i1 %0, label %bb, label %bb1
 
 bb:                                               ; preds = %entry
   tail call void @foo(i16 zeroext %1) nounwind
   ret i16 %1
 
 bb1:                                              ; preds = %entry
   ret i16 %1
 }
 
 define zeroext i16 @t2(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
 ; 32BIT-LABEL:     t2:
 ; 32BIT:     movw 20(%esp), %ax
 ; 32BIT-NOT: movw %ax, %cx
 ; 32BIT:     leal -1(%eax), %ecx
 
 ; 64BIT-LABEL:     t2:
 ; 64BIT-NOT: movw %si, %ax
-; 64BIT:     leal -1(%rsi), %eax
-; 64BIT:     movzwl %ax
+; 64BIT:     leal -1(%rsi), %ebx
+; 64BIT:     movzwl %bx
   %0 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
   %1 = add i16 %k, -1                             ; <i16> [#uses=3]
   br i1 %0, label %bb, label %bb1
 
 bb:                                               ; preds = %entry
   tail call void @foo(i16 zeroext %1) nounwind
   ret i16 %1
 
 bb1:                                              ; preds = %entry
   ret i16 %1
 }
 
 declare void @foo(i16 zeroext)
 
 define zeroext i16 @t3(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
 ; 32BIT-LABEL:     t3:
 ; 32BIT:     movw 20(%esp), %ax
 ; 32BIT-NOT: movw %ax, %cx
 ; 32BIT:     leal 2(%eax), %ecx
 
 ; 64BIT-LABEL:     t3:
 ; 64BIT-NOT: movw %si, %ax
-; 64BIT:     leal 2(%rsi), %eax
+; 64BIT:     leal 2(%rsi), %ebx
   %0 = add i16 %k, 2                              ; <i16> [#uses=3]
   %1 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
   br i1 %1, label %bb, label %bb1
 
 bb:                                               ; preds = %entry
   tail call void @foo(i16 zeroext %0) nounwind
   ret i16 %0
 
 bb1:                                              ; preds = %entry
   ret i16 %0
 }
 
 define zeroext i16 @t4(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
 ; 32BIT-LABEL:     t4:
 ; 32BIT:     movw 16(%esp), %ax
 ; 32BIT:     movw 20(%esp), %cx
 ; 32BIT-NOT: movw %cx, %dx
 ; 32BIT:     leal (%ecx,%eax), %edx
 
 ; 64BIT-LABEL:     t4:
 ; 64BIT-NOT: movw %si, %ax
-; 64BIT:     leal (%rsi,%rdi), %eax
+; 64BIT:     leal (%rsi,%rdi), %ebx
   %0 = add i16 %k, %c                             ; <i16> [#uses=3]
   %1 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
   br i1 %1, label %bb, label %bb1
 
 bb:                                               ; preds = %entry
   tail call void @foo(i16 zeroext %0) nounwind
   ret i16 %0
 
 bb1:                                              ; preds = %entry
   ret i16 %0
 }

test/CodeGen/X86/bool-zext.ll

+; RUN: llc < %s -mtriple=i686-unknown-linux-gnu | FileCheck %s -check-prefix=X86
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s -check-prefix=X64
 ; RUN: llc < %s -mtriple=x86_64-pc-win32 | FileCheck %s -check-prefix=WIN64
 
-; X64: @bar1
+; Check that the argument gets zero-extended before calling.
+; X86-LABEL: bar1
+; X86: movzbl
+; X86: calll
+; X64-LABEL: bar1
 ; X64: movzbl
 ; X64: jmp
-; WIN64: @bar1
+; WIN64-LABEL: bar1
 ; WIN64: movzbl
 ; WIN64: callq
 define void @bar1(i1 zeroext %v1) nounwind ssp {
 entry:
   %conv = zext i1 %v1 to i32
   %call = tail call i32 (...) @foo1(i32 %conv) nounwind
   ret void
 }
 
-; X64: @bar2
+; Check that on x86-64 the arguments are simply forwarded.
+; X64-LABEL: bar2
 ; X64-NOT: movzbl
 ; X64: jmp
-; WIN64: @bar2
+; WIN64-LABEL: bar2
 ; WIN64-NOT: movzbl
 ; WIN64: callq
 define void @bar2(i8 zeroext %v1) nounwind ssp {
 entry:
   %conv = zext i8 %v1 to i32
   %call = tail call i32 (...) @foo1(i32 %conv) nounwind
   ret void
 }
 
-; X64: @bar3
-; X64: callq
-; X64-NOT: movzbl
-; X64-NOT: and
-; X64: ret
-; WIN64: @bar3
-; WIN64: callq
-; WIN64-NOT: movzbl
-; WIN64-NOT: and
-; WIN64: ret
+; Check that i1 return values are not zero-extended.
+; X86-LABEL: bar3
+; X86: call
+; X86-NEXT: {{add|pop}}
+; X86-NEXT: ret
+; X64-LABEL: bar3
+; X64: call
+; X64-NEXT: {{add|pop}}
+; X64-NEXT: ret
+; WIN64-LABEL: bar3
+; WIN64: call
+; WIN64-NEXT: {{add|pop}}
+; WIN64-NEXT: ret
 define zeroext i1 @bar3() nounwind ssp {
 entry:
   %call = call i1 @foo2() nounwind
   ret i1 %call
 }
 
 declare i32 @foo1(...)
 declare zeroext i1 @foo2()

test/CodeGen/X86/divrem8_ext.ll

 ; RUN: llc -march=x86-64 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-64
 ; RUN: llc -march=x86    < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-32
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.10.0"
 
 define zeroext i8 @test_udivrem_zext_ah(i8 %x, i8 %y) {
 ; CHECK-LABEL: test_udivrem_zext_ah
 ; CHECK:   divb
-; CHECK:   movzbl %ah, [[REG_REM:%[a-z0-9]+]]
+; CHECK:   movzbl %ah, %e[[REG_REM:[a-z]]]x
 ; CHECK:   movb   %al, ([[REG_ZPTR:%[a-z0-9]+]])
-; CHECK:   movl   [[REG_REM]], %eax
+; CHECK:   movb   %[[REG_REM]]l, %al
 ; CHECK:   ret
   %div = udiv i8 %x, %y
   store i8 %div, i8* @z
   %1 = urem i8 %x, %y
   ret i8 %1
 }
 
 define zeroext i8 @test_urem_zext_ah(i8 %x, i8 %y) {
; CHECK:    ret
   %2 = zext i8 %1 to i64
   ret i64 %2
 }
 
 define signext i8 @test_sdivrem_sext_ah(i8 %x, i8 %y) {
 ; CHECK-LABEL: test_sdivrem_sext_ah
 ; CHECK:   cbtw
 ; CHECK:   idivb
-; CHECK:   movsbl %ah, [[REG_REM:%[a-z0-9]+]]
+; CHECK:   movsbl %ah, %e[[REG_REM:[a-z]]]x
 ; CHECK:   movb   %al, ([[REG_ZPTR]])
-; CHECK:   movl   [[REG_REM]], %eax
+; CHECK:   movb   %[[REG_REM]]l, %al
 ; CHECK:   ret
   %div = sdiv i8 %x, %y
   store i8 %div, i8* @z
   %1 = srem i8 %x, %y
   ret i8 %1
 }
 
 define signext i8 @test_srem_sext_ah(i8 %x, i8 %y) {

test/CodeGen/X86/float-conv-elim.ll

 define i32 @foo2(i8 %a) #0 {
   %conv = sitofp i8 %a to float
   %conv1 = fptosi float %conv to i32
   ret i32 %conv1
 }
 
 ; CHECK-LABEL: bar
 ; CHECK-NOT: cvt
-; CHECK: movl
+; CHECK: movb
 define zeroext i8 @bar(i8 zeroext %a) #0 {
   %conv = uitofp i8 %a to float
   %conv1 = fptoui float %conv to i8
   ret i8 %conv1
 }
 
 attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
 

test/CodeGen/X86/h-registers-3.ll

-; RUN: llc < %s -march=x86    | grep mov | count 1
-; RUN: llc < %s -march=x86-64 | grep mov | count 1
-; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | grep mov | count 1
+; RUN: llc < %s -march=x86                   | FileCheck %s -check-prefix=X86
+; RUN: llc < %s -march=x86-64                | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s -check-prefix=X32
 
 define zeroext i8 @foo() nounwind ssp {
 entry:
   %0 = tail call zeroext i16 (...) @bar() nounwind
   %1 = lshr i16 %0, 8
   %2 = trunc i16 %1 to i8
   ret i8 %2
+
+; X86-LABEL: foo
+; X86: calll
+; X86-NEXT: movb %ah, %al
+; X86-NEXT: addl $12, %esp
+; X86-NEXT: retl
+
+; X64-LABEL: foo
+; X64: callq
+; X64-NEXT: shrl $8, %eax
+; X64-NEXT: popq
+; X64-NEXT: retq
+
+; X32-LABEL: foo
+; X32: callq
+; X32-NEXT: shrl $8, %eax
+; X32-NEXT: popq
+; X32-NEXT: retq
 }
 
 declare zeroext i16 @bar(...)

test/CodeGen/X86/promote-i16.ll

 ; RUN: llc < %s -march=x86 | FileCheck %s
 
 define signext i16 @foo(i16 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: foo:
-; CHECK-NOT: movzwl
-; CHECK: movswl 4(%esp), %eax
-; CHECK: xorl $21998, %eax
+; CHECK: movzwl 4(%esp), %eax
+; CHECK-NEXT: xorl $21998, %eax
+; CHECK-NEXT: retl
   %0 = xor i16 %x, 21998
   ret i16 %0
 }
 
 define signext i16 @bar(i16 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: bar:
-; CHECK-NOT: movzwl
-; CHECK: movswl 4(%esp), %eax
-; CHECK: xorl $-10770, %eax
+; CHECK: movzwl 4(%esp), %eax
+; CHECK-NEXT: xorl $54766, %eax
+; CHECK-NEXT: retl
   %0 = xor i16 %x, 54766
   ret i16 %0
 }

test/CodeGen/X86/return-ext.ll

+; RUN: llc < %s -mtriple=i686-unknown-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+
+
+@x = common global i32 0, align 4
+
+define zeroext i1 @unsigned_i1() {
+entry:
+  %0 = load i32, i32* @x
+  %cmp = icmp eq i32 %0, 42
+  ret i1 %cmp
+
+; Unsigned i1 return values are not extended.
+; CHECK-LABEL: unsigned_i1:
+; CHECK:       cmp
+; CHECK-NEXT:  sete
+; CHECK-NEXT:  ret
+}
+
+define zeroext i8 @unsigned_i8() {
+entry:
+  %0 = load i32, i32* @x
+  %cmp = icmp eq i32 %0, 42
+  %retval = zext i1 %cmp to i8
+  ret i8 %retval
+
+; Unsigned i8 return values are not extended.
+; CHECK-LABEL: unsigned_i8:
+; CHECK:       cmp
+; CHECK-NEXT:  sete
+; CHECK-NEXT:  ret
+}
+
+define signext i8 @signed_i8() {
+entry:
+  %0 = load i32, i32* @x
+  %cmp = icmp eq i32 %0, 42
+  %retval = zext i1 %cmp to i8
+  ret i8 %retval
+
+; Signed i8 return values are not extended.
+; CHECK-LABEL: signed_i8:
+; CHECK:       cmp
+; CHECK-NEXT:  sete
+; CHECK-NEXT:  ret
+}
+
+@a = common global i16 0
+@b = common global i16 0
+define zeroext i16 @unsigned_i16() {
+entry:
+  %0 = load i16, i16* @a
+  %1 = load i16, i16* @b
+  %add = add i16 %1, %0
+  ret i16 %add
+
+; i16 return values are not extended.
+; CHECK-LABEL: unsigned_i16:
+; CHECK:       movw
+; CHECK-NEXT:  addw
+; CHECK-NEXT:  ret
+}

test/CodeGen/X86/select.ll

 define signext i8 @test4(i8* nocapture %P, double %F) nounwind readonly {
 entry:
   %0 = fcmp olt double %F, 4.200000e+01    ; <i1> [#uses=1]
   %iftmp.0.0 = select i1 %0, i32 4, i32 0    ; <i32> [#uses=1]
   %1 = getelementptr i8, i8* %P, i32 %iftmp.0.0    ; <i8*> [#uses=1]
   %2 = load i8, i8* %1, align 1    ; <i8> [#uses=1]
   ret i8 %2
 ; CHECK-LABEL: test4:
-; CHECK: movsbl ({{.*}},4), %eax
+; CHECK: movb ({{.*}},4), %al
 
 ; ATOM-LABEL: test4:
-; ATOM: movsbl ({{.*}},4), %eax
+; ATOM: movb ({{.*}},4), %al
 }
 
 define void @test5(i1 %c, <2 x i16> %a, <2 x i16> %b, <2 x i16>* %p) nounwind {
   %x = select i1 %c, <2 x i16> %a, <2 x i16> %b
   store <2 x i16> %x, <2 x i16>* %p
   ret void
 ; CHECK-LABEL: test5:
 

test/CodeGen/X86/sext-ret-val.ll

-; RUN: llc < %s -march=x86 | grep movzbl | count 1
+; RUN: llc < %s -march=x86 | FileCheck %s
 ; rdar://6699246
 
 define signext i8 @t1(i8* %A) nounwind readnone ssp {
 entry:
         %0 = icmp ne i8* %A, null
         %1 = zext i1 %0 to i8
         ret i8 %1
+
+; CHECK-LABEL: t1:
+; CHECK: cmpl
+; CHECK-NEXT: setne
+; CHECK-NEXT: retl
 }
 
 define i8 @t2(i8* %A) nounwind readnone ssp {
 entry:
         %0 = icmp ne i8* %A, null
         %1 = zext i1 %0 to i8
         ret i8 %1
+
+; CHECK-LABEL: t2:
+; CHECK: cmpl
+; CHECK-NEXT: setne
+; CHECK-NEXT: retl
 }

test/CodeGen/X86/sext-trunc.ll

-; RUN: llc < %s -march=x86 > %t
-; RUN: grep movsbl %t
-; RUN: not grep movz %t
-; RUN: not grep and %t
+; RUN: llc < %s -march=x86 | FileCheck %s
 
-define signext  i8 @foo(i16 signext  %x) nounwind  {
+define signext i8 @foo(i16 signext  %x) nounwind  {
   %retval56 = trunc i16 %x to i8
   ret i8 %retval56
+
+; CHECK-LABEL: foo:
+; CHECK: movb
+; CHECK-NEXT: retl
 }

test/CodeGen/X86/tail-call-attrs.ll

 ; RUN: llc -mtriple=x86_64-apple-darwin -o - %s | FileCheck %s
 
 ; Simple case: completely identical returns, even with extensions, shouldn't be
 ; a barrier to tail calls.
 declare zeroext i1 @give_bool()
 define zeroext i1 @test_bool() {
 ; CHECK-LABEL: test_bool:
 ; CHECK: jmp
   %call = tail call zeroext i1 @give_bool()
   ret i1 %call
 }
 
 ; Here, there's more zero extension to be done between the call and the return,
 ; so a tail call is impossible (well, according to current Clang practice
 ; anyway. The AMD64 ABI isn't crystal clear on the matter).
+; FIXME: The high 24 bits returned from test_i32 are undefined; do tail call!
 declare zeroext i32 @give_i32()
 define zeroext i8 @test_i32() {
 ; CHECK-LABEL: test_i32:
 ; CHECK: callq _give_i32
-; CHECK: movzbl %al, %eax
 ; CHECK: ret
 
   %call = tail call zeroext i32 @give_i32()
   %val = trunc i32 %call to i8
   ret i8 %val
 }
 
 ; Here, one function is zeroext and the other is signext. To the extent that
 ; these both mean something they are incompatible so no tail call is possible.
+; FIXME: The high 16 bits returned are undefined; do tail call!
 declare zeroext i16 @give_unsigned_i16()
 define signext i16 @test_incompatible_i16() {
 ; CHECK-LABEL: test_incompatible_i16:
 ; CHECK: callq _give_unsigned_i16
-; CHECK: cwtl
 ; CHECK: ret
 
   %call = tail call zeroext i16 @give_unsigned_i16()
   ret i16 %call
 }
 
 declare inreg i32 @give_i32_inreg()
 define i32 @test_inreg_to_normal() {

test/CodeGen/X86/trunc-to-bool.ll

 ; An integer truncation to i1 should be done with an and instruction to make
 ; sure only the LSBit survives. Test that this is the case both for a returned
 ; value and as the operand of a branch.
 ; RUN: llc < %s -march=x86 | FileCheck %s
 
 define zeroext i1 @test1(i32 %X)  nounwind {
     %Y = trunc i32 %X to i1
     ret i1 %Y
 }
 ; CHECK-LABEL: test1:
-; CHECK: andl $1, %eax
+; CHECK: andb $1, %al
 
 define i1 @test2(i32 %val, i32 %mask) nounwind {
 entry:
     %shifted = ashr i32 %val, %mask
     %anded = and i32 %shifted, 1
     %trunced = trunc i32 %anded to i1
     br i1 %trunced, label %ret_true, label %ret_false
 ret_true:

test/CodeGen/X86/umul-with-overflow.ll

 ; RUN: llc < %s -march=x86 | FileCheck %s
 
 declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b)
 define zeroext i1 @a(i32 %x)  nounwind {
   %res = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %x, i32 3)
   %obil = extractvalue {i32, i1} %res, 1
   ret i1 %obil
   
 ; CHECK-LABEL: a:
 ; CHECK: mull
 ; CHECK: seto %al
-; CHECK: movzbl %al, %eax
 ; CHECK: ret
 }
 
 define i32 @test2(i32 %a, i32 %b) nounwind readnone {
 entry:
   %tmp0 = add i32 %b, %a
   %tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 2)
   %tmp2 = extractvalue { i32, i1 } %tmp1, 0