[Power9] Implement new vector compare, extract, insert instructions

[cycheng]

Summary

This change implements the following vector operations:

• Vector Compare Not Equal
  1. vcmpneb(.) vcmpneh(.) vcmpnew(.)
  2. vcmpnezb(.) vcmpnezh(.) vcmpnezw(.)
• Vector Extract Unsigned
  1. vextractub vextractuh vextractuw vextractd
  2. vextublx vextubrx vextuhlx vextuhrx vextuwlx vextuwrx
• Vector Insert
  1. vinsertb vinserth vinsertw vinsertd

26 instructions.

[nemanjai]

These instructions definitely need intrinsics, a way to get at them through altivec.h and support in PPCISelLowering.cpp (getVectorCompareInfo). Of course, we are only doing the ASM support at this time, but I think this would be the right time to put a note somewhere about what else is needed for these instructions. Perhaps a file named along the lines of P9AdditionalSupportReq.txt in lib/Target/PowerPC/.

[cycheng]

• Use single predicate for power9
• Remove all intrinsics, we will implement them after finish *P9* assembler/disassembler support

[cycheng]

• Change to use multiple predicate, please see D15887 comment: http://reviews.llvm.org/D15887?vs=44743&id=45950&whitespace=ignore-most#335803
• Merge D15917, and add vector insert instructions
• All new Power9 altivec instructions are done by 2 patch: D15887, D15916.

[kbarton]

LGTM

[cycheng]

Write README_P9.txt for conforming the discipline we have discussed in http://reviews.llvm.org/D16842#344765

[cycheng]

Rebase against llvm revision r262104 (Feb 27 2016)

[kbarton]

Committed r262392

lib/Target/PowerPC/PPCInstrAltivec.td

 def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast",
                               int_ppc_altivec_crypto_vcipherlast, v2i64>;
 def VNCIPHER : VX1_Int_Ty<1352, "vncipher",
                           int_ppc_altivec_crypto_vncipher, v2i64>;
 def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast",
                               int_ppc_altivec_crypto_vncipherlast, v2i64>;
 def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;
 } // HasP8Crypto
+
+// The following altivec instructions were introduced in Power ISA 3.0
+def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">;
+let Predicates = [HasP9Altivec] in {
+
+// Vector Compare Not Equal (Zero)
+class P9VCMP<bits<10> xo, string asmstr, ValueType Ty>
+  : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
+              IIC_VecFPCompare, []>;
+class P9VCMPo<bits<10> xo, string asmstr, ValueType Ty>
+  : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
+              IIC_VecFPCompare, []> {
+  let Defs = [CR6];
+  let RC = 1;
+}
+
+// i8 element comparisons.
+def VCMPNEB   : P9VCMP <  7, "vcmpneb $vD, $vA, $vB"  , v16i8>;
+def VCMPNEBo  : P9VCMPo<  7, "vcmpneb. $vD, $vA, $vB" , v16i8>;
+def VCMPNEZB  : P9VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>;
+def VCMPNEZBo : P9VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>;
+
+// i16 element comparisons.
+def VCMPNEH   : P9VCMP < 71, "vcmpneh $vD, $vA, $vB"  , v8i16>;
+def VCMPNEHo  : P9VCMPo< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>;
+def VCMPNEZH  : P9VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>;
+def VCMPNEZHo : P9VCMPo<327, "vcmpnezh. $vD, $vA, $vB", v8i16>;
+
+// i32 element comparisons.
+def VCMPNEW   : P9VCMP <135, "vcmpnew $vD, $vA, $vB"  , v4i32>;
+def VCMPNEWo  : P9VCMPo<135, "vcmpnew. $vD, $vA, $vB" , v4i32>;
+def VCMPNEZW  : P9VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>;
+def VCMPNEZWo : P9VCMPo<391, "vcmpnezw. $vD, $vA, $vB", v4i32>;
+
+// VX-Form: [PO VRT / UIM VRB XO].
+// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
+// "/ UIM" (1 + 4 bit)
+class VX1_VT5_UIM5_VB5<bits<11> xo, string opc, list<dag> pattern>
+  : VXForm_1<xo, (outs vrrc:$vD), (ins u4imm:$UIMM, vrrc:$vB),
+             !strconcat(opc, " $vD, $vB, $UIMM"), IIC_VecGeneral, pattern>;
+
+class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern>
+  : VXForm_1<xo, (outs g8rc:$rD), (ins g8rc:$rA, vrrc:$vB),
+             !strconcat(opc, " $rD, $rA, $vB"), IIC_VecGeneral, pattern>;
+
+// Vector Extract Unsigned
+def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>;
+def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>;
+def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>;
+def VEXTRACTD  : VX1_VT5_UIM5_VB5<717, "vextractd" , []>;
+
+// Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed
+def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>;
+def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>;
+def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>;
+def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>;
+def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>;
+def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>;
+
+// Vector Insert Element Instructions
+def VINSERTB : VX1_VT5_UIM5_VB5<781, "vinsertb", []>;
+def VINSERTH : VX1_VT5_UIM5_VB5<845, "vinserth", []>;
+def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>;
+def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>;
+} // end HasP9Altivec

lib/Target/PowerPC/README_P9.txt

 //===- README_P9.txt - Notes for improving Power9 code gen ----------------===//
 
 TODO: Instructions Need Implement Instrinstics or Map to LLVM IR
 
 Altivec:
+- Vector Compare Not Equal (Zero):
+  vcmpneb(.) vcmpneh(.) vcmpnew(.)
+  vcmpnezb(.) vcmpnezh(.) vcmpnezw(.)
+  . Same as other VCMP*, use VCMP/VCMPo form (support intrinsic)
+
+- Vector Extract Unsigned: vextractub vextractuh vextractuw vextractd
+  . Don't use llvm extractelement because they have different semantics
+  . Use instrinstics:
+    (set v2i64:$vD, (int_ppc_altivec_vextractub v16i8:$vA, imm:$UIMM))
+    (set v2i64:$vD, (int_ppc_altivec_vextractuh v8i16:$vA, imm:$UIMM))
+    (set v2i64:$vD, (int_ppc_altivec_vextractuw v4i32:$vA, imm:$UIMM))
+    (set v2i64:$vD, (int_ppc_altivec_vextractd  v2i64:$vA, imm:$UIMM))
+
+- Vector Extract Unsigned Byte Left/Right-Indexed:
+  vextublx vextubrx vextuhlx vextuhrx vextuwlx vextuwrx
+  . Use instrinstics:
+    // Left-Indexed
+    (set i64:$rD, (int_ppc_altivec_vextublx i64:$rA, v16i8:$vB))
+    (set i64:$rD, (int_ppc_altivec_vextuhlx i64:$rA, v8i16:$vB))
+    (set i64:$rD, (int_ppc_altivec_vextuwlx i64:$rA, v4i32:$vB))
+
+    // Right-Indexed
+    (set i64:$rD, (int_ppc_altivec_vextubrx i64:$rA, v16i8:$vB))
+    (set i64:$rD, (int_ppc_altivec_vextuhrx i64:$rA, v8i16:$vB))
+    (set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB))
+
+- Vector Insert Element Instructions: vinsertb vinsertd vinserth vinsertw
+    (set v16i8:$vD, (int_ppc_altivec_vinsertb v16i8:$vA, imm:$UIMM))
+    (set v8i16:$vD, (int_ppc_altivec_vinsertd v8i16:$vA, imm:$UIMM))
+    (set v4i32:$vD, (int_ppc_altivec_vinserth v4i32:$vA, imm:$UIMM))
+    (set v2i64:$vD, (int_ppc_altivec_vinsertw v2i64:$vA, imm:$UIMM))
 
 VSX:
 
 - QP Compare Ordered/Unordered: xscmpoqp xscmpuqp
   . ref: XSCMPUDP
       def XSCMPUDP : XX3Form_1<60, 35,
                                (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
                                "xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>;

test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt

 0x10 0x40 0x1f 0xc3
 
 # CHECK: mtvscr 2                        
 0x10 0x00 0x16 0x44
 
 # CHECK: mfvscr 2                        
 0x10 0x40 0x06 0x04
 
+# Power9 instructions
+
+# CHECK: vcmpneb   2, 3, 4
+0x10 0x43 0x20 0x07
+
+# CHECK: vcmpneb.  2, 3, 4
+0x10 0x43 0x24 0x07
+
+# CHECK: vcmpnezb  2, 3, 4
+0x10 0x43 0x21 0x07
+
+# CHECK: vcmpnezb. 2, 3, 4
+0x10 0x43 0x25 0x07
+
+# CHECK: vcmpneh   2, 3, 4
+0x10 0x43 0x20 0x47
+
+# CHECK: vcmpneh.  2, 3, 4
+0x10 0x43 0x24 0x47
+
+# CHECK: vcmpnezh  2, 3, 4
+0x10 0x43 0x21 0x47
+
+# CHECK: vcmpnezh. 2, 3, 4
+0x10 0x43 0x25 0x47
+
+# CHECK: vcmpnew   2, 3, 4
+0x10 0x43 0x20 0x87
+
+# CHECK: vcmpnew.  2, 3, 4
+0x10 0x43 0x24 0x87
+
+# CHECK: vcmpnezw  2, 3, 4
+0x10 0x43 0x21 0x87
+
+# CHECK: vcmpnezw. 2, 3, 4
+0x10 0x43 0x25 0x87
+
+# CHECK: vextractub 2, 3, 15
+0x10 0x4f 0x1a 0x0d
+
+# CHECK: vextractuh 2, 3, 14
+0x10 0x4e 0x1a 0x4d
+
+# CHECK: vextractuw 2, 3, 12
+0x10 0x4c 0x1a 0x8d
+
+# CHECK: vextractd 2, 3, 8
+0x10 0x48 0x1a 0xcd
+
+# CHECK: vextublx 2, 3, 4
+0x10 0x43 0x26 0x0d
+
+# CHECK: vextubrx 2, 3, 4
+0x10 0x43 0x27 0x0d
+
+# CHECK: vextuhlx 2, 3, 4
+0x10 0x43 0x26 0x4d
+
+# CHECK: vextuhrx 2, 3, 4
+0x10 0x43 0x27 0x4d
+
+# CHECK: vextuwlx 2, 3, 4
+0x10 0x43 0x26 0x8d
+
+# CHECK: vextuwrx 2, 3, 4
+0x10 0x43 0x27 0x8d
+
+# CHECK: vinsertb 2, 3, 15
+0x10 0x4f 0x1b 0x0d
+
+# CHECK: vinserth 2, 3, 14
+0x10 0x4e 0x1b 0x4d
+
+# CHECK: vinsertw 2, 3, 12
+0x10 0x4c 0x1b 0x8d
+
+# CHECK: vinsertd 2, 3, 8
+0x10 0x48 0x1b 0xcd
+

test/MC/PowerPC/ppc64-encoding-vmx.s

 
 # CHECK-BE: mtvscr 2                        # encoding: [0x10,0x00,0x16,0x44]
 # CHECK-LE: mtvscr 2                        # encoding: [0x44,0x16,0x00,0x10]
             mtvscr 2
 # CHECK-BE: mfvscr 2                        # encoding: [0x10,0x40,0x06,0x04]
 # CHECK-LE: mfvscr 2                        # encoding: [0x04,0x06,0x40,0x10]
             mfvscr 2
 
+# Power9 instructions
+
+# Vector Compare Not Equal (Zero)
+# CHECK-BE: vcmpneb 2, 3, 4                 # encoding: [0x10,0x43,0x20,0x07]
+# CHECK-LE: vcmpneb 2, 3, 4                 # encoding: [0x07,0x20,0x43,0x10]
+            vcmpneb 2, 3, 4
+# CHECK-BE: vcmpneb. 2, 3, 4                # encoding: [0x10,0x43,0x24,0x07]
+# CHECK-LE: vcmpneb. 2, 3, 4                # encoding: [0x07,0x24,0x43,0x10]
+            vcmpneb. 2, 3, 4
+# CHECK-BE: vcmpnezb 2, 3, 4                # encoding: [0x10,0x43,0x21,0x07]
+# CHECK-LE: vcmpnezb 2, 3, 4                # encoding: [0x07,0x21,0x43,0x10]
+            vcmpnezb 2, 3, 4
+# CHECK-BE: vcmpnezb. 2, 3, 4               # encoding: [0x10,0x43,0x25,0x07]
+# CHECK-LE: vcmpnezb. 2, 3, 4               # encoding: [0x07,0x25,0x43,0x10]
+            vcmpnezb. 2, 3, 4
+# CHECK-BE: vcmpneh 2, 3, 4                 # encoding: [0x10,0x43,0x20,0x47]
+# CHECK-LE: vcmpneh 2, 3, 4                 # encoding: [0x47,0x20,0x43,0x10]
+            vcmpneh 2, 3, 4
+# CHECK-BE: vcmpneh. 2, 3, 4                # encoding: [0x10,0x43,0x24,0x47]
+# CHECK-LE: vcmpneh. 2, 3, 4                # encoding: [0x47,0x24,0x43,0x10]
+            vcmpneh. 2, 3, 4
+# CHECK-BE: vcmpnezh 2, 3, 4                # encoding: [0x10,0x43,0x21,0x47]
+# CHECK-LE: vcmpnezh 2, 3, 4                # encoding: [0x47,0x21,0x43,0x10]
+            vcmpnezh 2, 3, 4
+# CHECK-BE: vcmpnezh. 2, 3, 4               # encoding: [0x10,0x43,0x25,0x47]
+# CHECK-LE: vcmpnezh. 2, 3, 4               # encoding: [0x47,0x25,0x43,0x10]
+            vcmpnezh. 2, 3, 4
+# CHECK-BE: vcmpnew 2, 3, 4                 # encoding: [0x10,0x43,0x20,0x87]
+# CHECK-LE: vcmpnew 2, 3, 4                 # encoding: [0x87,0x20,0x43,0x10]
+            vcmpnew 2, 3, 4
+# CHECK-BE: vcmpnew. 2, 3, 4                # encoding: [0x10,0x43,0x24,0x87]
+# CHECK-LE: vcmpnew. 2, 3, 4                # encoding: [0x87,0x24,0x43,0x10]
+            vcmpnew. 2, 3, 4
+# CHECK-BE: vcmpnezw 2, 3, 4                # encoding: [0x10,0x43,0x21,0x87]
+# CHECK-LE: vcmpnezw 2, 3, 4                # encoding: [0x87,0x21,0x43,0x10]
+            vcmpnezw 2, 3, 4
+# CHECK-BE: vcmpnezw. 2, 3, 4               # encoding: [0x10,0x43,0x25,0x87]
+# CHECK-LE: vcmpnezw. 2, 3, 4               # encoding: [0x87,0x25,0x43,0x10]
+            vcmpnezw. 2, 3, 4
+
+# Vector Extract Unsigned
+# CHECK-BE: vextractub 2, 3, 15             # encoding: [0x10,0x4f,0x1a,0x0d]
+# CHECK-LE: vextractub 2, 3, 15             # encoding: [0x0d,0x1a,0x4f,0x10]
+            vextractub 2, 3, 15
+# CHECK-BE: vextractuh 2, 3, 14             # encoding: [0x10,0x4e,0x1a,0x4d]
+# CHECK-LE: vextractuh 2, 3, 14             # encoding: [0x4d,0x1a,0x4e,0x10]
+            vextractuh 2, 3, 14
+# CHECK-BE: vextractuw 2, 3, 12             # encoding: [0x10,0x4c,0x1a,0x8d]
+# CHECK-LE: vextractuw 2, 3, 12             # encoding: [0x8d,0x1a,0x4c,0x10]
+            vextractuw 2, 3, 12
+# CHECK-BE: vextractd 2, 3, 8               # encoding: [0x10,0x48,0x1a,0xcd]
+# CHECK-LE: vextractd 2, 3, 8               # encoding: [0xcd,0x1a,0x48,0x10]
+            vextractd 2, 3, 8
+
+# Vector Extract Unsigned Left/Right-Indexed
+# CHECK-BE: vextublx 2, 3, 4                # encoding: [0x10,0x43,0x26,0x0d]
+# CHECK-LE: vextublx 2, 3, 4                # encoding: [0x0d,0x26,0x43,0x10]
+            vextublx 2, 3, 4
+# CHECK-BE: vextubrx 2, 3, 4                # encoding: [0x10,0x43,0x27,0x0d]
+# CHECK-LE: vextubrx 2, 3, 4                # encoding: [0x0d,0x27,0x43,0x10]
+            vextubrx 2, 3, 4
+# CHECK-BE: vextuhlx 2, 3, 4                # encoding: [0x10,0x43,0x26,0x4d]
+# CHECK-LE: vextuhlx 2, 3, 4                # encoding: [0x4d,0x26,0x43,0x10]
+            vextuhlx 2, 3, 4
+# CHECK-BE: vextuhrx 2, 3, 4                # encoding: [0x10,0x43,0x27,0x4d]
+# CHECK-LE: vextuhrx 2, 3, 4                # encoding: [0x4d,0x27,0x43,0x10]
+            vextuhrx 2, 3, 4
+# CHECK-BE: vextuwlx 2, 3, 4                # encoding: [0x10,0x43,0x26,0x8d]
+# CHECK-LE: vextuwlx 2, 3, 4                # encoding: [0x8d,0x26,0x43,0x10]
+            vextuwlx 2, 3, 4
+# CHECK-BE: vextuwrx 2, 3, 4                # encoding: [0x10,0x43,0x27,0x8d]
+# CHECK-LE: vextuwrx 2, 3, 4                # encoding: [0x8d,0x27,0x43,0x10]
+            vextuwrx 2, 3, 4
+
+# Vector Insert Element
+# CHECK-BE: vinsertb 2, 3, 15               # encoding: [0x10,0x4f,0x1b,0x0d]
+# CHECK-LE: vinsertb 2, 3, 15               # encoding: [0x0d,0x1b,0x4f,0x10]
+            vinsertb 2, 3, 15
+# CHECK-BE: vinserth 2, 3, 14               # encoding: [0x10,0x4e,0x1b,0x4d]
+# CHECK-LE: vinserth 2, 3, 14               # encoding: [0x4d,0x1b,0x4e,0x10]
+            vinserth 2, 3, 14
+# CHECK-BE: vinsertw 2, 3, 12               # encoding: [0x10,0x4c,0x1b,0x8d]
+# CHECK-LE: vinsertw 2, 3, 12               # encoding: [0x8d,0x1b,0x4c,0x10]
+            vinsertw 2, 3, 12
+# CHECK-BE: vinsertd 2, 3, 8                # encoding: [0x10,0x48,0x1b,0xcd]
+# CHECK-LE: vinsertd 2, 3, 8                # encoding: [0xcd,0x1b,0x48,0x10]
+            vinsertd 2, 3, 8
+