[Power9] Implement new vsx instructions: insert, extract, test data class, min/max, reverse, permute, splat

[cycheng]

Summary

This change implements the following vsx instructions:

• Scalar Insert/Extract
  1. xsiexpdp xsiexpqp xsxexpdp xsxsigdp xsxexpqp xsxsigqp
• Vector Insert/Extract
  1. xviexpdp xviexpsp xvxexpdp xvxexpsp xvxsigdp xvxsigsp
  2. xxextractuw xxinsertw
• Scalar/Vector Test Data Class
  1. xststdcdp xststdcsp xststdcqp
  2. xvtstdcdp xvtstdcsp
• Maximum/Minimum
  1. xsmaxcdp xsmaxjdp
  2. xsmincdp xsminjdp
• Vector Byte-Reverse/Permute/Splat
  1. xxbrd xxbrh xxbrq xxbrw
  2. xxperm xxpermr
  3. xxspltib

30 instructions

[nemanjai]

I just have a general comment about this approach we're using for implementing new instructions for assembly and disassembly only. Perhaps it would not be a terrible idea for us to add inline asm test cases for each of them. For example:

%0 = call <2 x i64> asm "xxspltib $0, $1", "=^wa,i"(i32 44) #1, !srcloc !1

should emit something like

xxspltib 0, 44

Or would this not really test anything?

lib/Target/PowerPC/PPCInstrFormats.td

750

I think these comments are quite useful in quickly identifying fields of the instruction. How come such comments do not appear consistently on all the new classes introduced?

lib/Target/PowerPC/PPCInstrVSX.td

1777

These all operate on vectors rather than scalars. This should be the vsrc register class.

1782

This should probably have the ins/outs dags parameterized since it appears to be used by both vector (xviexpdp, xviexpsp, xxperm, etc.) and scalar (xsmax.., xsmin..., etc.).
So the vector ones should probably use vsrc and scalar ones vsfrc.

1800

Perhaps I am missing something, but it seems that (at least the target) should be in the vsrc register class since the instruction can put the word element 1 (BE) of the source into the target starting at any byte (0-12 BE order)? In fact, I would argue that both operands should be vsrc register class since this type of operation makes more sense for vectors than it does for scalars (especially floating point scalars).

Also, isn't the immediate in this instruction a 4-bit immediate? I realize that this isn't necessarily relevant since we will ensure that the immediate is <=12 so it will never set the reserved bit, but it still makes the instruction definition clear and ensures that even without such checks in place, we will not generate illegal instructions.

1805

Same comment applies here as above but in reverse order.

1855

Again, this is a vector instruction and should not be using vsfrc.

lib/Target/PowerPC/README_P9.txt

4

How come this isn't populated with the instructions added here? I think that it would be pertinent to put in as much of the info at this time as possible (since you're looking at the instructions in some amount of detail). Perhaps something like this for all the new instructions:

• Has likely SDAG match (and if there's an obvious candidate SDAG, make the suggestion)
• Likely needs an intrinsic
• If you know that we want to expose some builtin for it, please note that
• Miscellaneous aspects we may or may not need to account for (i.e. instructions that modify the FPSCR)

P.S. I really think this file needs to have each instruction listed so that when we start working on full support for these (not just ASM), we can pick them off one at a time.

[cycheng]

Thanks for your careful feedback :) I'll fix these issues you mentioned:

• Review all using of vsfrc, vssrc, vsrc, because I misunderstand its usage. It looks like
  1. vssrc: for VSX scalar single precision
  2. vsfrc:
     • for VSX scalar double precision fp, or single word, double word int
     • move instruction use vsfrc
  3. vsrc: for VSX vector instructions
• Make the instruction definition clear for XX2_RD6_UIM5_RS6: 5-bit immediate -> 4-bit immediate Review all other new instructions that have similar definition.
• Add format comment for each new form
• README_P9.txt: list each new instructions for
  1. Has likely SDAG match?
  2. Needs an intrinsic?
  3. Needs builtin?
  4. Miscellaneous notes
• Inline assembly test case: Need discuss with Kit

[nemanjai]

Thanks for summarizing and addressing the comments. One of the key aspects of the vsfrc/vssrc/vsrc classes is whether the entire register is used or just the left 64 bits. So vector instructions operate on the entire register and we use the vsrc register class whereas scalar ones operate on the scalar portion of the register.
So your summary is correct with respect to the usage of the register classes.

P.S. There are no operations on integer scalars in vector registers - the moves are used only for:

1. Conversion between integers and FP
2. Bitcasting between integers and FP
3. Freeing up a GPR by moving the value into a VSR (to be moved back when needed)

[cycheng]

Thanks a lot :")

By the way, patch D16919 follows the approach you mentioned here, and I will review D16842, D16709, D16110 again, and update new ones later. I will leave next week, and will be back on Feb 15.

[cycheng]

Fix issues mentioned in:
http://reviews.llvm.org/D16842#344765
http://reviews.llvm.org/D16842#344908

[kbarton]

LGTM

[cycheng]

Committed r264567

lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

public:
   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
   bool isU6ImmX2() const { return Kind == Immediate &&
                                   isUInt<6>(getImm()) &&
                                   (getImm() & 1) == 0; }
+  bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
   bool isU7ImmX4() const { return Kind == Immediate &&
                                   isUInt<7>(getImm()) &&
                                   (getImm() & 3) == 0; }
+  bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
   bool isU8ImmX8() const { return Kind == Immediate &&
                                   isUInt<8>(getImm()) &&
                                   (getImm() & 7) == 0; }
   
   bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
   bool isU16Imm() const {
     switch (Kind) {

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h

public:
 
   void printU1ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU3ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  void printU7ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU10ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O);
 
   void printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
 
   void printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
 };
 } // end namespace llvm
 
 #endif

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

 
 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
                                        raw_ostream &O) {
   unsigned int Value = MI->getOperand(OpNo).getImm();
   assert(Value <= 63 && "Invalid u6imm argument!");
   O << (unsigned int)Value;
 }
 
+void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
+                                       raw_ostream &O) {
+  unsigned int Value = MI->getOperand(OpNo).getImm();
+  assert(Value <= 127 && "Invalid u7imm argument!");
+  O << (unsigned int)Value;
+}
+
+void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
+                                       raw_ostream &O) {
+  unsigned int Value = MI->getOperand(OpNo).getImm();
+  assert(Value <= 255 && "Invalid u8imm argument!");
+  O << (unsigned int)Value;
+}
+
 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
                                         raw_ostream &O) {
   unsigned short Value = MI->getOperand(OpNo).getImm();
   assert(Value <= 1023 && "Invalid u10imm argument!");
   O << (unsigned short)Value;
 }
 
 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,

lib/Target/PowerPC/PPC.td

def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
                                         "Enable POWER8 Altivec instructions",
                                         [FeatureAltivec]>;
 def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
                                        "Enable POWER8 Crypto instructions",
                                        [FeatureP8Altivec]>;
 def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
                                         "Enable POWER8 vector instructions",
                                         [FeatureVSX, FeatureP8Altivec]>;
+def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
+                                        "Enable POWER9 Altivec instructions",
+                                        [FeatureP8Altivec]>;
+def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
+                                        "Enable POWER9 vector instructions",
+                                        [FeatureP8Vector, FeatureP9Altivec]>;
 def FeatureDirectMove :
   SubtargetFeature<"direct-move", "HasDirectMove", "true",
                    "Enable Power8 direct move instructions",
                    [FeatureVSX]>;
 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
                                              "HasPartwordAtomics", "true",
                                              "Enable l[bh]arx and st[bh]cx.">;
 def FeatureInvariantFunctionDescriptors :

lib/Target/PowerPC/PPCInstrFormats.td

class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
   bit RC = 0;
 
   let Inst{6-8}   = BF;
   let Inst{9-20}  = 0;
   let Inst{21-30} = xo;
   let Inst{31}    = RC;
 }
 
+// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RC]
+class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
+                    string asmstr, InstrItinClass itin, list<dag> pattern>
+  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+  let A = xo2;
+}
+
+class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+                      string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<3> BF;
+  bits<7> DCMX;
+  bits<5> VB;
+
+  let Pattern = pattern;
+
+  let Inst{6-8}  = BF;
+  let Inst{9-15} = DCMX;
+  let Inst{16-20} = VB;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
+class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+                 string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<8> IMM8;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = XT{4-0};
+  let Inst{11-12} = 0;
+  let Inst{13-20} = IMM8;
+  let Inst{21-30} = xo;
+  let Inst{31}    = XT{5};
+}
+
 // XX*-Form (VSX)
 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 
               InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<6> XT;
   bits<5> A;
   bits<5> B;
 
class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
   let Inst{11-13} = 0;
   let Inst{14-15} = D;
   let Inst{16-20} = XB{4-0};
   let Inst{21-29} = xo;
   let Inst{30}    = XB{5};
   let Inst{31}    = XT{5};
 }
 
+class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+                       string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<6> XB;
+  bits<5> UIM5;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = XT{4-0};
+  let Inst{11-15} = UIM5;
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-29} = xo;
+  let Inst{30}    = XB{5};
+  let Inst{31}    = XT{5};
+}
+
+// [PO T XO B XO BX /]
+class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
+                       string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<5> RT;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = RT;
+  let Inst{11-15} = xo2;
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-29} = xo;
+  let Inst{30}    = XB{5};
+  let Inst{31}    = 0;
+}
+
+// [PO T XO B XO BX TX]
+class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
+                      string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = XT{4-0};
+  let Inst{11-15} = xo2;
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-29} = xo;
+  let Inst{30}    = XB{5};
+  let Inst{31}    = XT{5};
+}
+
+class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+                      string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<3> BF;
+  bits<7> DCMX;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6-8}  = BF;
+  let Inst{9-15} = DCMX;
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-29} = xo;
+  let Inst{30}    = XB{5};
+  let Inst{31}    = 0;
+}
+
+class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
+                        dag OOL, dag IOL, string asmstr, InstrItinClass itin,
+                        list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<7> DCMX;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = XT{4-0};
+  let Inst{11-15} = DCMX{4-0};
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-24} = xo1;
+  let Inst{25}    = DCMX{5};
+  let Inst{26-28} = xo2;
+  let Inst{29}    = DCMX{6};
+  let Inst{30}    = XB{5};
+  let Inst{31}    = XT{5};
+}
+
 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 
               InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<6> XT;
   bits<6> XA;
   bits<6> XB;
 
   let Pattern = pattern;

lib/Target/PowerPC/PPCInstrInfo.td

def PPCU6ImmAsmOperand : AsmOperandClass {
   let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
   let RenderMethod = "addImmOperands";
 }
 def u6imm   : Operand<i32> {
   let PrintMethod = "printU6ImmOperand";
   let ParserMatchClass = PPCU6ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<6>";
 }
+def PPCU7ImmAsmOperand : AsmOperandClass {
+  let Name = "U7Imm"; let PredicateMethod = "isU7Imm";
+  let RenderMethod = "addImmOperands";
+}
+def u7imm   : Operand<i32> {
+  let PrintMethod = "printU7ImmOperand";
+  let ParserMatchClass = PPCU7ImmAsmOperand;
+  let DecoderMethod = "decodeUImmOperand<7>";
+}
+def PPCU8ImmAsmOperand : AsmOperandClass {
+  let Name = "U8Imm"; let PredicateMethod = "isU8Imm";
+  let RenderMethod = "addImmOperands";
+}
+def u8imm   : Operand<i32> {
+  let PrintMethod = "printU8ImmOperand";
+  let ParserMatchClass = PPCU8ImmAsmOperand;
+  let DecoderMethod = "decodeUImmOperand<8>";
+}
 def PPCU10ImmAsmOperand : AsmOperandClass {
   let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
   let RenderMethod = "addImmOperands";
 }
 def u10imm  : Operand<i32> {
   let PrintMethod = "printU10ImmOperand";
   let ParserMatchClass = PPCU10ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<10>";

lib/Target/PowerPC/PPCInstrVSX.td

let Predicates = [IsLittleEndian, HasDirectMove] in {
   // v2i64 scalar <-> vector conversions (LE)
   def : Pat<(i64 (vector_extract v2i64:$S, 0)),
             (i64 VectorExtractions.LE_DWORD_0)>;
   def : Pat<(i64 (vector_extract v2i64:$S, 1)),
             (i64 VectorExtractions.LE_DWORD_1)>;
   def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)),
             (i64 VectorExtractions.LE_VARIABLE_DWORD)>;
 } // IsLittleEndian, HasDirectMove
+
+// The following VSX instructions were introduced in Power ISA 3.0
+def HasP9Vector : Predicate<"PPCSubTarget->hasP9Vector()">;
+let Predicates = [HasP9Vector] in {
+
+  // [PO VRT XO VRB XO /]
+  class X_VT5_XO5_VB5<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
+                      list<dag> pattern>
+    : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vrrc:$vB),
+                    !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
+
+  // [PO T XO B XO BX /]
+  class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
+                        list<dag> pattern>
+    : XX2_RD5_XO5_RS6<opcode, xo2, xo, (outs g8rc:$rT), (ins vsfrc:$XB),
+                      !strconcat(opc, " $rT, $XB"), IIC_VecFP, pattern>;
+
+  // [PO T XO B XO BX TX]
+  class XX2_XT6_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
+                        list<dag> pattern>
+    : XX2_RD6_XO5_RS6<opcode, xo2, xo, (outs vsrc:$XT), (ins vsrc:$XB),
+                      !strconcat(opc, " $XT, $XB"), IIC_VecFP, pattern>;
+
+  // [PO T A B XO AX BX TX]
+  class XX3_XT5_XA5_XB5<bits<6> opcode, bits<8> xo, string opc,
+                  RegisterOperand xty, RegisterOperand aty, RegisterOperand bty,
+                  InstrItinClass itin, list<dag> pattern>
+    : XX3Form<opcode, xo, (outs xty:$XT), (ins aty:$XA, bty:$XB),
+              !strconcat(opc, " $XT, $XA, $XB"), itin, pattern>;
+
+  // Insert Exponent DP/QP
+  // XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU
+  def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB),
+                          "xsiexpdp $XT, $rA, $rB", IIC_VecFP, []>;
+  // vB NOTE: only vB.dword[0] is used, that's why we don't use
+  //          X_VT5_VA5_VB5 form
+  def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$vT), (ins vrrc:$vA, vsfrc:$vB),
+                          "xsiexpqp $vT, $vA, $vB", IIC_VecFP, []>;
+
+  // Extract Exponent/Significand DP/QP
+  def XSXEXPDP : XX2_RT5_XO5_XB6<60,  0, 347, "xsxexpdp", []>;
+  def XSXSIGDP : XX2_RT5_XO5_XB6<60,  1, 347, "xsxsigdp", []>;
+  def XSXEXPQP : X_VT5_XO5_VB5  <63,  2, 804, "xsxexpqp", []>;
+  def XSXSIGQP : X_VT5_XO5_VB5  <63, 18, 804, "xsxsigqp", []>;
+
+  // Vector Insert Word
+  // XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB.
+  def XXINSERTW   : XX2_RD6_UIM5_RS6<60, 181,
+                                  (outs vsrc:$XT), (ins u4imm:$UIMM, vsrc:$XB),
+                                  "xxinsertw $XT, $XB, $UIMM", IIC_VecFP, []>;
+
+  // Vector Extract Unsigned Word
+  def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165,
+                                  (outs vsrc:$XT), (ins u4imm:$UIMM, vsrc:$XB),
+                                  "xxextractuw $XT, $XB, $UIMM", IIC_VecFP, []>;
+
+  // Vector Insert Exponent DP/SP
+  def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc,
+                                 IIC_VecFP, []>;
+  def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", vsrc, vsrc, vsrc,
+                                 IIC_VecFP, []>;
+
+  // Vector Extract Exponent/Significand DP/SP
+  def XVXEXPDP : XX2_XT6_XO5_XB6<60,  0, 475, "xvxexpdp", []>;
+  def XVXEXPSP : XX2_XT6_XO5_XB6<60,  8, 475, "xvxexpsp", []>;
+  def XVXSIGDP : XX2_XT6_XO5_XB6<60,  1, 475, "xvxsigdp", []>;
+  def XVXSIGSP : XX2_XT6_XO5_XB6<60,  9, 475, "xvxsigsp", []>;
+
+  // Test Data Class SP/DP/QP
+  def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298,
+                              (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
+                              "xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>;
+  def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362,
+                              (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
+                              "xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>;
+  def XSTSTDCQP : X_BF3_DCMX7_RS5  <63, 708,
+                              (outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$vB),
+                              "xststdcqp $BF, $vB, $DCMX", IIC_VecFP, []>;
+
+  // Vector Test Data Class SP/DP
+  def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5,
+                              (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
+                              "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP, []>;
+  def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5,
+                              (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
+                              "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP, []>;
+
+  // Maximum/Minimum Type-C/Type-J DP
+  // XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU, so we use vsrc for XT
+  def XSMAXCDP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", vsrc, vsfrc, vsfrc,
+                                 IIC_VecFP, []>;
+  def XSMAXJDP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", vsrc, vsfrc, vsfrc,
+                                 IIC_VecFP, []>;
+  def XSMINCDP : XX3_XT5_XA5_XB5<60, 136, "xsmincdp", vsrc, vsfrc, vsfrc,
+                                 IIC_VecFP, []>;
+  def XSMINJDP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", vsrc, vsfrc, vsfrc,
+                                 IIC_VecFP, []>;
+
+  // Vector Byte-Reverse H/W/D/Q Word
+  def XXBRH : XX2_XT6_XO5_XB6<60,  7, 475, "xxbrh", []>;
+  def XXBRW : XX2_XT6_XO5_XB6<60, 15, 475, "xxbrw", []>;
+  def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", []>;
+  def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", []>;
+
+  // Vector Permute
+  def XXPERM  : XX3_XT5_XA5_XB5<60, 26, "xxperm" , vsrc, vsrc, vsrc, 
+                                IIC_VecPerm, []>;
+  def XXPERMR : XX3_XT5_XA5_XB5<60, 58, "xxpermr", vsrc, vsrc, vsrc,
+                                IIC_VecPerm, []>;
+
+  // Vector Splat Immediate Byte
+  def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8),
+                            "xxspltib $XT, $IMM8", IIC_VecPerm, []>;
+} // end HasP9Vector

lib/Target/PowerPC/PPCSubtarget.h

protected:
   bool IsPPC64;
   bool HasAltivec;
   bool HasSPE;
   bool HasQPX;
   bool HasVSX;
   bool HasP8Vector;
   bool HasP8Altivec;
   bool HasP8Crypto;
+  bool HasP9Vector;
+  bool HasP9Altivec;
   bool HasFCPSGN;
   bool HasFSQRT;
   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
   bool HasRecipPrec;
   bool HasSTFIWX;
   bool HasLFIWAX;
   bool HasFPRND;
   bool HasFPCVT;
public:
   bool hasFPCVT() const { return HasFPCVT; }
   bool hasAltivec() const { return HasAltivec; }
   bool hasSPE() const { return HasSPE; }
   bool hasQPX() const { return HasQPX; }
   bool hasVSX() const { return HasVSX; }
   bool hasP8Vector() const { return HasP8Vector; }
   bool hasP8Altivec() const { return HasP8Altivec; }
   bool hasP8Crypto() const { return HasP8Crypto; }
+  bool hasP9Vector() const { return HasP9Vector; }
+  bool hasP9Altivec() const { return HasP9Altivec; }
   bool hasMFOCRF() const { return HasMFOCRF; }
   bool hasISEL() const { return HasISEL; }
   bool hasPOPCNTD() const { return HasPOPCNTD; }
   bool hasBPERMD() const { return HasBPERMD; }
   bool hasExtDiv() const { return HasExtDiv; }
   bool hasCMPB() const { return HasCMPB; }
   bool hasLDBRX() const { return HasLDBRX; }
   bool isBookE() const { return IsBookE; }

lib/Target/PowerPC/PPCSubtarget.cpp

void PPCSubtarget::initializeEnvironment() {
   UseSoftFloat = false;
   HasAltivec = false;
   HasSPE = false;
   HasQPX = false;
   HasVSX = false;
   HasP8Vector = false;
   HasP8Altivec = false;
   HasP8Crypto = false;
+  HasP9Vector = false;
+  HasP9Altivec = false;
   HasFCPSGN = false;
   HasFSQRT = false;
   HasFRE = false;
   HasFRES = false;
   HasFRSQRTE = false;
   HasFRSQRTES = false;
   HasRecipPrec = false;
   HasSTFIWX = false;

lib/Target/PowerPC/README_P9.txt

+//===- README_P9.txt - Notes for improving Power9 code gen ----------------===//
+
+TODO: Instructions Need Implement Instrinstics or Map to LLVM IR
+
+Altivec:
+
+VSX:
+- Insert Exponent DP/QP: xsiexpdp xsiexpqp
+  . Use intrinsic?
+  . xsiexpdp:
+    // Note: rA and rB are the unsigned integer value.
+    (set f128:$XT, (int_ppc_vsx_xsiexpdp i64:$rA, i64:$rB))
+
+  . xsiexpqp:
+    (set f128:$vT, (int_ppc_vsx_xsiexpqp f128:$vA, f64:$vB))
+
+- Extract Exponent/Significand DP/QP: xsxexpdp xsxsigdp xsxexpqp xsxsigqp
+  . Use intrinsic?
+  . (set i64:$rT, (int_ppc_vsx_xsxexpdp f64$XB))    // xsxexpdp
+    (set i64:$rT, (int_ppc_vsx_xsxsigdp f64$XB))    // xsxsigdp
+    (set f128:$vT, (int_ppc_vsx_xsxexpqp f128$vB))  // xsxexpqp
+    (set f128:$vT, (int_ppc_vsx_xsxsigqp f128$vB))  // xsxsigqp
+
+- Vector Insert Word: xxinsertw
+  . Note: llvm has insertelem in "Vector Operations"
+    ; yields <n x <ty>>
+    <result> = insertelement <n x <ty>> <val>, <ty> <elt>, <ty2> <idx>
+
+    But how to map to it??
+    [(set v1f128:$XT, (insertelement v1f128:$XTi, f128:$XB, i4:$UIMM))]>,
+    RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+
+  . Or use intrinsic?
+    (set v1f128:$XT, (int_ppc_vsx_xxinsertw v1f128:$XTi, f128:$XB, i4:$UIMM))
+
+- Vector Extract Unsigned Word: xxextractuw
+  . Note: llvm has extractelement in "Vector Operations"
+    ; yields <ty>
+    <result> = extractelement <n x <ty>> <val>, <ty2> <idx>
+
+    How to map to it??
+    [(set f128:$XT, (extractelement v1f128:$XB, i4:$UIMM))]
+
+  . Or use intrinsic?
+    (set f128:$XT, (int_ppc_vsx_xxextractuw v1f128:$XB, i4:$UIMM))
+
+- Vector Insert Exponent DP/SP: xviexpdp xviexpsp
+  . Use intrinsic
+    (set v2f64:$XT, (int_ppc_vsx_xviexpdp v2f64:$XA, v2f64:$XB))
+    (set v4f32:$XT, (int_ppc_vsx_xviexpsp v4f32:$XA, v4f32:$XB))
+
+- Vector Extract Exponent/Significand DP/SP: xvxexpdp xvxexpsp xvxsigdp xvxsigsp
+  . Use intrinsic
+    (set v2f64:$XT, (int_ppc_vsx_xvxexpdp v2f64:$XB))
+    (set v4f32:$XT, (int_ppc_vsx_xvxexpsp v4f32:$XB))
+    (set v2f64:$XT, (int_ppc_vsx_xvxsigdp v2f64:$XB))
+    (set v4f32:$XT, (int_ppc_vsx_xvxsigsp v4f32:$XB))
+
+- Test Data Class SP/DP/QP: xststdcsp xststdcdp xststdcqp
+  . No SDAG, intrinsic, builtin are required?
+    Because it seems that we have no way to map BF field?
+
+    Instruction Form: [PO T XO B XO BX TX]
+    Asm: xststd* BF,XB,DCMX
+
+    BF is an index to CR register field.
+
+- Vector Test Data Class SP/DP: xvtstdcsp xvtstdcdp
+  . Use intrinsic
+    (set v4f32:$XT, (int_ppc_vsx_xvtstdcsp v4f32:$XB, i7:$DCMX))
+    (set v2f64:$XT, (int_ppc_vsx_xvtstdcdp v2f64:$XB, i7:$DCMX))
+
+- Maximum/Minimum Type-C/Type-J DP: xsmaxcdp xsmaxjdp xsmincdp xsminjdp
+  . PowerISA_V3.0:
+    "xsmaxcdp can be used to implement the C/C++/Java conditional operation
+     (x>y)?x:y for single-precision and double-precision arguments."
+
+    Note! c type and j type have different behavior when:
+    1. Either input is NaN
+    2. Both input are +-Infinity, +-Zero
+
+  . dtype map to llvm fmaxnum/fminnum
+    jtype use intrinsic
+
+  . xsmaxcdp xsmincdp
+    (set f64:$XT, (fmaxnum f64:$XA, f64:$XB))
+    (set f64:$XT, (fminnum f64:$XA, f64:$XB))
+
+  . xsmaxjdp xsminjdp
+    (set f64:$XT, (int_ppc_vsx_xsmaxjdp f64:$XA, f64:$XB))
+    (set f64:$XT, (int_ppc_vsx_xsminjdp f64:$XA, f64:$XB))
+
+- Vector Byte-Reverse H/W/D/Q Word: xxbrh xxbrw xxbrd xxbrq
+  . Use intrinsic
+    (set v8i16:$XT, (int_ppc_vsx_xxbrh v8i16:$XB))
+    (set v4i32:$XT, (int_ppc_vsx_xxbrw v4i32:$XB))
+    (set v2i64:$XT, (int_ppc_vsx_xxbrd v2i64:$XB))
+    (set v1i128:$XT, (int_ppc_vsx_xxbrq v1i128:$XB))
+
+- Vector Permute: xxperm xxpermr
+  . I have checked "PPCxxswapd" in PPCInstrVSX.td, but they are different
+  . Use intrinsic
+    (set v16i8:$XT, (int_ppc_vsx_xxperm v16i8:$XA, v16i8:$XB))
+    (set v16i8:$XT, (int_ppc_vsx_xxpermr v16i8:$XA, v16i8:$XB))
+
+- Vector Splat Immediate Byte: xxspltib
+  . Similar to XXSPLTW:
+      def XXSPLTW : XX2Form_2<60, 164,
+                           (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM),
+                           "xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>;
+
+  . No SDAG, intrinsic, builtin are required?
+

test/MC/Disassembler/PowerPC/vsx.txt

 # CHECK: mtvsrd 0, 3
 0x7c 0x03 0x01 0x66
 
 # CHECK: mtvsrwa 0, 3
 0x7c 0x03 0x01 0xa6
 
 # CHECK: mtvsrwz 0, 3
 0x7c 0x03 0x01 0xe6
+
+# Power9 Instructions:
+
+# CHECK: xsiexpdp 63, 3, 4
+0xf3 0xe3 0x27 0x2d
+
+# CHECK: xsiexpqp 7, 31, 27
+0xfc 0xff 0xde 0xc8
+
+# CHECK: xviexpdp 7, 63, 27
+0xf0 0xff 0xdf 0xc4
+
+# CHECK: xviexpsp 7, 63, 27
+0xf0 0xff 0xde 0xc4
+
+# CHECK: xxextractuw 7, 63, 15
+0xf0 0xef 0xfa 0x96
+
+# CHECK: xxinsertw 7, 63, 15
+0xf0 0xef 0xfa 0xd6
+
+# CHECK: xsxexpdp 7, 63
+0xf0 0xe0 0xfd 0x6e
+
+# CHECK: xsxsigdp 7, 63
+0xf0 0xe1 0xfd 0x6e
+
+# CHECK: xsxexpqp 7, 31
+0xfc 0xe2 0xfe 0x48
+
+# CHECK: xsxsigqp 7, 31
+0xfc 0xf2 0xfe 0x48
+
+# CHECK: xvxexpdp 7, 63
+0xf0 0xe0 0xff 0x6e
+
+# CHECK: xvxexpsp 7, 63
+0xf0 0xe8 0xff 0x6e
+
+# CHECK: xvxsigdp 7, 63
+0xf0 0xe1 0xff 0x6e
+
+# CHECK: xvxsigsp 7, 63
+0xf0 0xe9 0xff 0x6e
+
+# CHECK: xststdcsp 7, 63, 127
+0xf3 0xff 0xfc 0xaa
+
+# CHECK: xststdcdp 7, 63, 127
+0xf3 0xff 0xfd 0xaa
+
+# CHECK: xststdcqp 7, 31, 127
+0xff 0xff 0xfd 0x88
+
+# CHECK: xststdcsp 7, 63, 127
+0xf3 0xff 0xfc 0xaa
+
+# CHECK: xststdcdp 7, 63, 127
+0xf3 0xff 0xfd 0xaa
+
+# CHECK: xststdcqp 7, 31, 127
+0xff 0xff 0xfd 0x88
+
+# CHECK: xsmaxcdp 7, 63, 27
+0xf0 0xff 0xdc 0x04
+
+# CHECK: xsmaxjdp 7, 63, 27
+0xf0 0xff 0xdc 0x84
+
+# CHECK: xsmincdp 7, 63, 27
+0xf0 0xff 0xdc 0x44
+
+# CHECK: xsminjdp 7, 63, 27
+0xf0 0xff 0xdc 0xc4
+
+# CHECK: xxbrh 7, 63
+0xf0 0xe7 0xff 0x6e
+
+# CHECK: xxbrw 7, 63
+0xf0 0xef 0xff 0x6e
+
+# CHECK: xxbrd 7, 63
+0xf0 0xf7 0xff 0x6e
+
+# CHECK: xxbrq 7, 63
+0xf0 0xff 0xff 0x6e
+
+# CHECK: xxperm 7, 63, 27
+0xf0 0xff 0xd8 0xd4
+
+# CHECK: xxpermr 7, 63, 27
+0xf0 0xff 0xd9 0xd4
+
+# CHECK: xxspltib 63, 255
+0xf3 0xe7 0xfa 0xd1

test/MC/PowerPC/vsx.s

 # CHECK-LE: mtvsrd 0, 3                        # encoding: [0x66,0x01,0x03,0x7c]
             mtvsrd 0, 3
 # CHECK-BE: mtvsrwa 0, 3                       # encoding: [0x7c,0x03,0x01,0xa6]
 # CHECK-LE: mtvsrwa 0, 3                       # encoding: [0xa6,0x01,0x03,0x7c]
             mtvsrwa 0, 3
 # CHECK-BE: mtvsrwz 0, 3                       # encoding: [0x7c,0x03,0x01,0xe6]
 # CHECK-LE: mtvsrwz 0, 3                       # encoding: [0xe6,0x01,0x03,0x7c]
             mtvsrwz 0, 3
+
+# Power9 Instructions:
+
+# Insert Exponent DP/QP
+# CHECK-BE: xsiexpdp 63, 3, 4                  # encoding: [0xf3,0xe3,0x27,0x2d]
+# CHECK-LE: xsiexpdp 63, 3, 4                  # encoding: [0x2d,0x27,0xe3,0xf3]
+            xsiexpdp 63, 3, 4
+# CHECK-BE: xsiexpqp 7, 31, 27                 # encoding: [0xfc,0xff,0xde,0xc8]
+# CHECK-LE: xsiexpqp 7, 31, 27                 # encoding: [0xc8,0xde,0xff,0xfc]
+            xsiexpqp 7, 31, 27
+
+# Vector Insert Exponent DP
+# CHECK-BE: xviexpdp 7, 63, 27                 # encoding: [0xf0,0xff,0xdf,0xc4]
+# CHECK-LE: xviexpdp 7, 63, 27                 # encoding: [0xc4,0xdf,0xff,0xf0]
+            xviexpdp 7, 63, 27
+# CHECK-BE: xviexpsp 7, 63, 27                 # encoding: [0xf0,0xff,0xde,0xc4]
+# CHECK-LE: xviexpsp 7, 63, 27                 # encoding: [0xc4,0xde,0xff,0xf0]
+            xviexpsp 7, 63, 27
+
+# Vector Extract Unsigned Word
+# CHECK-BE: xxextractuw 7, 63, 15              # encoding: [0xf0,0xef,0xfa,0x96]
+# CHECK-LE: xxextractuw 7, 63, 15              # encoding: [0x96,0xfa,0xef,0xf0]
+            xxextractuw 7, 63, 15
+
+# Vector Insert Word
+# CHECK-BE: xxinsertw 7, 63, 15                # encoding: [0xf0,0xef,0xfa,0xd6]
+# CHECK-LE: xxinsertw 7, 63, 15                # encoding: [0xd6,0xfa,0xef,0xf0]
+            xxinsertw 7, 63, 15
+
+# Extract Exponent/Significand DP/QP
+# CHECK-BE: xsxexpdp 7, 63                     # encoding: [0xf0,0xe0,0xfd,0x6e]
+# CHECK-LE: xsxexpdp 7, 63                     # encoding: [0x6e,0xfd,0xe0,0xf0]
+            xsxexpdp 7, 63
+# CHECK-BE: xsxsigdp 7, 63                     # encoding: [0xf0,0xe1,0xfd,0x6e]
+# CHECK-LE: xsxsigdp 7, 63                     # encoding: [0x6e,0xfd,0xe1,0xf0]
+            xsxsigdp 7, 63
+# CHECK-BE: xsxexpqp 7, 31                     # encoding: [0xfc,0xe2,0xfe,0x48]
+# CHECK-LE: xsxexpqp 7, 31                     # encoding: [0x48,0xfe,0xe2,0xfc]
+            xsxexpqp 7, 31
+# CHECK-BE: xsxsigqp 7, 31                     # encoding: [0xfc,0xf2,0xfe,0x48]
+# CHECK-LE: xsxsigqp 7, 31                     # encoding: [0x48,0xfe,0xf2,0xfc]
+            xsxsigqp 7, 31
+
+# Vector Extract Exponent/Significand DP
+# CHECK-BE: xvxexpdp 7, 63                     # encoding: [0xf0,0xe0,0xff,0x6e]
+# CHECK-LE: xvxexpdp 7, 63                     # encoding: [0x6e,0xff,0xe0,0xf0]
+            xvxexpdp 7, 63
+# CHECK-BE: xvxexpsp 7, 63                     # encoding: [0xf0,0xe8,0xff,0x6e]
+# CHECK-LE: xvxexpsp 7, 63                     # encoding: [0x6e,0xff,0xe8,0xf0]
+            xvxexpsp 7, 63
+# CHECK-BE: xvxsigdp 7, 63                     # encoding: [0xf0,0xe1,0xff,0x6e]
+# CHECK-LE: xvxsigdp 7, 63                     # encoding: [0x6e,0xff,0xe1,0xf0]
+            xvxsigdp 7, 63
+# CHECK-BE: xvxsigsp 7, 63                     # encoding: [0xf0,0xe9,0xff,0x6e]
+# CHECK-LE: xvxsigsp 7, 63                     # encoding: [0x6e,0xff,0xe9,0xf0]
+            xvxsigsp 7, 63
+
+# Test Data Class SP/DP/QP
+# CHECK-BE: xststdcsp 7, 63, 127               # encoding: [0xf3,0xff,0xfc,0xaa]
+# CHECK-LE: xststdcsp 7, 63, 127               # encoding: [0xaa,0xfc,0xff,0xf3]
+            xststdcsp 7, 63, 127
+# CHECK-BE: xststdcdp 7, 63, 127               # encoding: [0xf3,0xff,0xfd,0xaa]
+# CHECK-LE: xststdcdp 7, 63, 127               # encoding: [0xaa,0xfd,0xff,0xf3]
+            xststdcdp 7, 63, 127
+# CHECK-BE: xststdcqp 7, 31, 127               # encoding: [0xff,0xff,0xfd,0x88]
+# CHECK-LE: xststdcqp 7, 31, 127               # encoding: [0x88,0xfd,0xff,0xff]
+            xststdcqp 7, 31, 127
+
+# Vector Test Data Class SP/DP
+# CHECK-BE: xststdcsp 7, 63, 127               # encoding: [0xf3,0xff,0xfc,0xaa]
+# CHECK-LE: xststdcsp 7, 63, 127               # encoding: [0xaa,0xfc,0xff,0xf3]
+            xststdcsp 7, 63, 127
+# CHECK-BE: xststdcdp 7, 63, 127               # encoding: [0xf3,0xff,0xfd,0xaa]
+# CHECK-LE: xststdcdp 7, 63, 127               # encoding: [0xaa,0xfd,0xff,0xf3]
+            xststdcdp 7, 63, 127
+# CHECK-BE: xststdcqp 7, 31, 127               # encoding: [0xff,0xff,0xfd,0x88]
+# CHECK-LE: xststdcqp 7, 31, 127               # encoding: [0x88,0xfd,0xff,0xff]
+            xststdcqp 7, 31, 127
+
+# Maximum/Minimum Type-C/Type-J DP
+# CHECK-BE: xsmaxcdp 7, 63, 27                 # encoding: [0xf0,0xff,0xdc,0x04]
+# CHECK-LE: xsmaxcdp 7, 63, 27                 # encoding: [0x04,0xdc,0xff,0xf0]
+            xsmaxcdp 7, 63, 27
+# CHECK-BE: xsmaxjdp 7, 63, 27                 # encoding: [0xf0,0xff,0xdc,0x84]
+# CHECK-LE: xsmaxjdp 7, 63, 27                 # encoding: [0x84,0xdc,0xff,0xf0]
+            xsmaxjdp 7, 63, 27
+# CHECK-BE: xsmincdp 7, 63, 27                 # encoding: [0xf0,0xff,0xdc,0x44]
+# CHECK-LE: xsmincdp 7, 63, 27                 # encoding: [0x44,0xdc,0xff,0xf0]
+            xsmincdp 7, 63, 27
+# CHECK-BE: xsminjdp 7, 63, 27                 # encoding: [0xf0,0xff,0xdc,0xc4]
+# CHECK-LE: xsminjdp 7, 63, 27                 # encoding: [0xc4,0xdc,0xff,0xf0]
+            xsminjdp 7, 63, 27
+
+# Vector Byte-Reverse H/W/D/Q Word
+# CHECK-BE: xxbrh 7, 63                        # encoding: [0xf0,0xe7,0xff,0x6e]
+# CHECK-LE: xxbrh 7, 63                        # encoding: [0x6e,0xff,0xe7,0xf0]
+            xxbrh 7, 63
+# CHECK-BE: xxbrw 7, 63                        # encoding: [0xf0,0xef,0xff,0x6e]
+# CHECK-LE: xxbrw 7, 63                        # encoding: [0x6e,0xff,0xef,0xf0]
+            xxbrw 7, 63
+# CHECK-BE: xxbrd 7, 63                        # encoding: [0xf0,0xf7,0xff,0x6e]
+# CHECK-LE: xxbrd 7, 63                        # encoding: [0x6e,0xff,0xf7,0xf0]
+            xxbrd 7, 63
+# CHECK-BE: xxbrq 7, 63                        # encoding: [0xf0,0xff,0xff,0x6e]
+# CHECK-LE: xxbrq 7, 63                        # encoding: [0x6e,0xff,0xff,0xf0]
+            xxbrq 7, 63
+
+# Vector Permute
+# CHECK-BE: xxperm 7, 63, 27                   # encoding: [0xf0,0xff,0xd8,0xd4]
+# CHECK-LE: xxperm 7, 63, 27                   # encoding: [0xd4,0xd8,0xff,0xf0]
+            xxperm 7, 63, 27
+# CHECK-BE: xxpermr 7, 63, 27                  # encoding: [0xf0,0xff,0xd9,0xd4]
+# CHECK-LE: xxpermr 7, 63, 27                  # encoding: [0xd4,0xd9,0xff,0xf0]
+            xxpermr 7, 63, 27
+
+# Vector Splat Immediate Byte
+# CHECK-BE: xxspltib 63, 255                   # encoding: [0xf3,0xe7,0xfa,0xd1]
+# CHECK-LE: xxspltib 63, 255                   # encoding: [0xd1,0xfa,0xe7,0xf3]
+            xxspltib 63, 255