[Power9] Implement new altivec instructions: permute, count zero, extend sign, negate, parity, shift/rotate, mul10

[cycheng]

Summary

This change implements the following vector operations:

• vclzlsbb vctzlsbb vctzb vctzd vctzh vctzw
• vextsb2w vextsh2w vextsb2d vextsh2d vextsw2d
• vnegd vnegw
• vprtybd vprtybq vprtybw
• vbpermd vpermr
• vrlwnm vrlwmi vrldnm vrldmi vslv vsrv
• vmul10cuq vmul10uq vmul10ecuq vmul10euq

28 instructions

[nemanjai]

lib/Target/PowerPC/PPCInstrAltivec.td

1217

Since P9 has fewer optional features, do we need P9Altivec, P9Vector, etc.? Or perhaps we would like a single predicate and a single feature that will give us everything? I suppose that AES and DFP are still optional, but any additions therein can use the P9 predicate along with the respective predicate.

1220

Should we have a test that @llvm.ppc.altivec.vbpermd emits the correct instruction? I suppose we can't really do that at this time unless we have the target feature implemented (see comment below).

lib/Target/PowerPC/PPCSubtarget.h

95

Was the implementation of this feature in PPC.td intentionally omitted? Is the plan to implement setting this feature using -mattr at a later time?

[cycheng]

lib/Target/PowerPC/PPCInstrAltivec.td

1217

Agree. By the way, how can I know an instruction is optional instruction?

lib/Target/PowerPC/PPCSubtarget.h

95

Thanks! It looks like I have to add "FeatureP9*" in PPC.td, I didn't notice it, I will fix it later.

[nemanjai]

lib/Target/PowerPC/PPCInstrAltivec.td

1217

The text "Category:" followed by the name of the category will be part of the instruction description or the section of the ISA. This is of course very prevalent in all versions of Power ISA up to and including 2.07. It is mostly absent from ISA 3.0.

[cycheng]

• Use single predicate for power9
• Remove all intrinsics, we will implement them after finish P9 assembler/disassembler support

[cycheng]

Changes:

• Follow naming convention to rename global and local instruction forms
• Add pattern parameter for local defined instruction forms
• Fix IsP9 position
• Add new instructions (I plan to use 2 patches to cover all new p9 altivec instructions, so D15916 and D15917 will be merged.)

[cycheng]

• After discuss with Kit, we change to use multiple predicate: one predicate for one feature. Because it is convenient if we want to test single feature. We can discuss on this more if you guys have other opinions.

[kbarton]

lib/Target/PowerPC/PPCInstrAltivec.td

1231

I would prefer to keep track of the questionable TODOs in a separate file, as opposed to scattering them throughout this file.
In my experience, these have a way of entering the code, but never getting cleaned up.

We talked about creating a README_P9.txt file in the lib/Target/PowerPC directory to contain this type of (possibly) outstanding items to do.

1238

Move to separate file

1246

Move to separate file.

1258

Is this referring to adding intrinsic support for this instruction, or something else?
This should apply to almost all of these instructions being added. Again, this is something we want to track in a separate file.

[cycheng]

lib/Target/PowerPC/PPCInstrAltivec.td

1258

Yes, it is referring to adding intrinsic support.

[cycheng]

• Separate TODOs into README_P9.txt

[cycheng]

Rewrite README_P9.txt for conforming the discipline we have discussed in http://reviews.llvm.org/D16842#344765

[kbarton]

LGTM

[cycheng]

Committed r264504

lib/Target/PowerPC/PPC.td

def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
                                         "Enable POWER8 Altivec instructions",
                                         [FeatureAltivec]>;
 def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
                                        "Enable POWER8 Crypto instructions",
                                        [FeatureP8Altivec]>;
 def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
                                         "Enable POWER8 vector instructions",
                                         [FeatureVSX, FeatureP8Altivec]>;
+def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
+                                        "Enable POWER9 Altivec instructions",
+                                        [FeatureP8Altivec]>;
 def FeatureDirectMove :
   SubtargetFeature<"direct-move", "HasDirectMove", "true",
                    "Enable Power8 direct move instructions",
                    [FeatureVSX]>;
 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
                                              "HasPartwordAtomics", "true",
                                              "Enable l[bh]arx and st[bh]cx.">;
 def FeatureInvariantFunctionDescriptors :

lib/Target/PowerPC/PPCInstrAltivec.td

 def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast",
                               int_ppc_altivec_crypto_vcipherlast, v2i64>;
 def VNCIPHER : VX1_Int_Ty<1352, "vncipher",
                           int_ppc_altivec_crypto_vncipher, v2i64>;
 def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast",
                               int_ppc_altivec_crypto_vncipherlast, v2i64>;
 def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;
 } // HasP8Crypto
+
+// The following altivec instructions were introduced in Power ISA 3.0
+def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">;
+let Predicates = [HasP9Altivec] in {
+
+class VX_VT5_EO5_VB5<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>
+  : VXForm_RD5_XO5_RS5<xo, eo, (outs vrrc:$vD), (ins vrrc:$vB),
+                       !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>;
+
+// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]
+def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs g8rc:$rD), (ins vrrc:$vB),
+                                 "vclzlsbb $rD, $vB", IIC_VecGeneral, []>;
+def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs g8rc:$rD), (ins vrrc:$vB),
+                                 "vctzlsbb $rD, $vB", IIC_VecGeneral, []>;
+// Vector Count Trailing Zeros
+def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb", []>;
+def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh", []>;
+def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw", []>;
+def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd", []>;
+
+// Vector Extend Sign
+def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", []>;
+def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", []>;
+def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", []>;
+def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", []>;
+def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", []>;
+
+// Vector Integer Negate
+def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", []>;
+def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", []>;
+
+// Vector Parity Byte
+def VPRTYBW : VX_VT5_EO5_VB5<1538,  8, "vprtybw", []>;
+def VPRTYBD : VX_VT5_EO5_VB5<1538,  9, "vprtybd", []>;
+def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", []>;
+
+// Vector (Bit) Permute (Right-indexed)
+def VBPERMD : VXForm_1<1484, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+                       "vbpermd $vD, $vA, $vB", IIC_VecFP, []>;
+def VPERMR : VAForm_1a<59, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
+                       "vpermr $vD, $vA, $vB, $vC", IIC_VecFP, []>;
+
+class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern>
+  : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+             !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern>;
+
+// Vector Rotate Left Mask/Mask-Insert
+def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm", []>;
+def VRLWMI : VX1_VT5_VA5_VB5<133, "vrlwmi", []>;
+def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", []>;
+def VRLDMI : VX1_VT5_VA5_VB5<197, "vrldmi", []>;
+
+// Vector Shift Left/Right
+def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", []>;
+def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv", []>;
+
+// Vector Multiply-by-10 (& Write Carry) Unsigned Quadword
+def VMUL10UQ   : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA),
+                           "vmul10uq $vD, $vA", IIC_VecFP, []>;
+def VMUL10CUQ  : VXForm_BX<  1, (outs vrrc:$vD), (ins vrrc:$vA),
+                           "vmul10cuq $vD, $vA", IIC_VecFP, []>;
+
+// Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword
+def VMUL10EUQ  : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>;
+def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>;
+} // end HasP9Altivec

lib/Target/PowerPC/PPCInstrFormats.td

class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
   let Pattern = pattern;
   
   let Inst{6-10}  = 0;
   let Inst{11-15} = 0;
   let Inst{16-20} = VB;
   let Inst{21-31} = xo;
 }
 
+/// e.g. [PO, VRT, EO, VRB, XO]
+class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL,
+                         string asmstr, InstrItinClass itin, list<dag> pattern>
+    : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> RD;
+  bits<5> VB;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = RD;
+  let Inst{11-15} = eo;
+  let Inst{16-20} = VB;
+  let Inst{21-31} = xo;
+}
+
 /// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX"
 class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
     : I<4, OOL, IOL, asmstr, itin> {
   bits<5> VD;
   bits<5> VA;
   bits<1> ST;
   bits<4> SIX;

lib/Target/PowerPC/PPCSubtarget.h

protected:
   bool IsPPC64;
   bool HasAltivec;
   bool HasSPE;
   bool HasQPX;
   bool HasVSX;
   bool HasP8Vector;
   bool HasP8Altivec;
   bool HasP8Crypto;
+  bool HasP9Altivec;
   bool HasFCPSGN;
   bool HasFSQRT;
   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
   bool HasRecipPrec;
   bool HasSTFIWX;
   bool HasLFIWAX;
   bool HasFPRND;
   bool HasFPCVT;
public:
   bool hasFPCVT() const { return HasFPCVT; }
   bool hasAltivec() const { return HasAltivec; }
   bool hasSPE() const { return HasSPE; }
   bool hasQPX() const { return HasQPX; }
   bool hasVSX() const { return HasVSX; }
   bool hasP8Vector() const { return HasP8Vector; }
   bool hasP8Altivec() const { return HasP8Altivec; }
   bool hasP8Crypto() const { return HasP8Crypto; }
+  bool hasP9Altivec() const { return HasP9Altivec; }
   bool hasMFOCRF() const { return HasMFOCRF; }
   bool hasISEL() const { return HasISEL; }
   bool hasPOPCNTD() const { return HasPOPCNTD; }
   bool hasBPERMD() const { return HasBPERMD; }
   bool hasExtDiv() const { return HasExtDiv; }
   bool hasCMPB() const { return HasCMPB; }
   bool hasLDBRX() const { return HasLDBRX; }
   bool isBookE() const { return IsBookE; }

lib/Target/PowerPC/PPCSubtarget.cpp

void PPCSubtarget::initializeEnvironment() {
   UseSoftFloat = false;
   HasAltivec = false;
   HasSPE = false;
   HasQPX = false;
   HasVSX = false;
   HasP8Vector = false;
   HasP8Altivec = false;
   HasP8Crypto = false;
+  HasP9Altivec = false;
   HasFCPSGN = false;
   HasFSQRT = false;
   HasFRE = false;
   HasFRES = false;
   HasFRSQRTE = false;
   HasFRSQRTES = false;
   HasRecipPrec = false;
   HasSTFIWX = false;

lib/Target/PowerPC/README_P9.txt

+//===- README_P9.txt - Notes for improving Power9 code gen ----------------===//
+
+TODO: Instructions Need Implement Instrinstics or Map to LLVM IR
+
+Altivec:
+- Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]:
+  vclzlsbb vctzlsbb
+  . Use intrinsic:
+    (set i64:$rD, (int_ppc_altivec_vclzlsbb v16i8:$vB))
+    (set i64:$rD, (int_ppc_altivec_vctzlsbb v16i8:$vB))
+
+- Vector Count Trailing Zeros: vctzb vctzh vctzw vctzd
+  . Map to llvm cttz
+    (set v16i8:$vD, (cttz v16i8:$vB))     // vctzb
+    (set v8i16:$vD, (cttz v8i16:$vB))     // vctzh
+    (set v4i32:$vD, (cttz v4i32:$vB))     // vctzw
+    (set v2i64:$vD, (cttz v2i64:$vB))     // vctzd
+
+- Vector Extend Sign: vextsb2w vextsh2w vextsb2d vextsh2d vextsw2d
+  . vextsb2w:
+    (set v4i32:$vD, (sext v4i8:$vB))
+
+    // PowerISA_V3.0:
+    do i = 0 to 3
+       VR[VRT].word[i] ← EXTS32(VR[VRB].word[i].byte[3])
+    end
+
+  . vextsh2w:
+    (set v4i32:$vD, (sext v4i16:$vB))
+
+    // PowerISA_V3.0:
+    do i = 0 to 3
+       VR[VRT].word[i] ← EXTS32(VR[VRB].word[i].hword[1])
+    end
+
+  . vextsb2d
+    (set v2i64:$vD, (sext v2i8:$vB))
+
+    // PowerISA_V3.0:
+    do i = 0 to 1
+       VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].byte[7])
+    end
+
+  . vextsh2d
+    (set v2i64:$vD, (sext v2i16:$vB))
+
+    // PowerISA_V3.0:
+    do i = 0 to 1
+       VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].hword[3])
+    end
+
+  . vextsw2d
+    (set v2i64:$vD, (sext v2i32:$vB))
+
+    // PowerISA_V3.0:
+    do i = 0 to 1
+       VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].word[1])
+    end
+
+- Vector Integer Negate: vnegw vnegd
+  . Map to llvm ineg
+    (set v4i32:$rT, (ineg v4i32:$rA))       // vnegw
+    (set v2i64:$rT, (ineg v2i64:$rA))       // vnegd
+
+- Vector Parity Byte: vprtybw vprtybd vprtybq
+  . Use intrinsic:
+    (set v4i32:$rD, (int_ppc_altivec_vprtybw v4i32:$vB))
+    (set v2i64:$rD, (int_ppc_altivec_vprtybd v2i64:$vB))
+    (set v1i128:$rD, (int_ppc_altivec_vprtybq v1i128:$vB))
+
+- Vector (Bit) Permute (Right-indexed):
+  . vbpermd: Same as "vbpermq", use VX1_Int_Ty2:
+    VX1_Int_Ty2<1484, "vbpermd", int_ppc_altivec_vbpermd, v2i64, v2i64>;
+
+  . vpermr: use VA1a_Int_Ty3
+    VA1a_Int_Ty3<59, "vpermr", int_ppc_altivec_vpermr, v16i8, v16i8, v16i8>;
+
+- Vector Rotate Left Mask/Mask-Insert: vrlwnm vrlwmi vrldnm vrldmi
+  . Use intrinsic:
+    VX1_Int_Ty<389, "vrlwnm", int_ppc_altivec_vrlwnm, v4i32>;
+    VX1_Int_Ty<133, "vrlwmi", int_ppc_altivec_vrlwmi, v4i32>;
+    VX1_Int_Ty<453, "vrldnm", int_ppc_altivec_vrldnm, v2i64>;
+    VX1_Int_Ty<197, "vrldmi", int_ppc_altivec_vrldmi, v2i64>;
+
+- Vector Shift Left/Right: vslv vsrv
+  . Use intrinsic, don't map to llvm shl and lshr, because they have different
+    semantics, e.g. vslv:
+
+      do i = 0 to 15
+         sh ← VR[VRB].byte[i].bit[5:7]
+         VR[VRT].byte[i] ← src.byte[i:i+1].bit[sh:sh+7]
+      end
+
+    VR[VRT].byte[i] is composed of 2 bytes from src.byte[i:i+1]
+
+  . VX1_Int_Ty<1860, "vslv", int_ppc_altivec_vslv, v16i8>;
+    VX1_Int_Ty<1796, "vsrv", int_ppc_altivec_vsrv, v16i8>;
+
+- Vector Multiply-by-10 (& Write Carry) Unsigned Quadword:
+  vmul10uq vmul10cuq
+  . Use intrinsic:
+    VX1_Int_Ty<513, "vmul10uq",   int_ppc_altivec_vmul10uq,  v1i128>;
+    VX1_Int_Ty<  1, "vmul10cuq",  int_ppc_altivec_vmul10cuq, v1i128>;
+
+- Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword:
+  vmul10euq vmul10ecuq
+  . Use intrinsic:
+    VX1_Int_Ty<577, "vmul10euq",  int_ppc_altivec_vmul10euq, v1i128>;
+    VX1_Int_Ty< 65, "vmul10ecuq", int_ppc_altivec_vmul10ecuq, v1i128>;
+
+VSX:
+

test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt

 0x10 0x40 0x1f 0xc3
 
 # CHECK: mtvscr 2                        
 0x10 0x00 0x16 0x44
 
 # CHECK: mfvscr 2                        
 0x10 0x40 0x06 0x04
 
+# Power9 instructions
+
+# CHECK: vclzlsbb 2, 3
+0x10 0x40 0x1e 0x02
+
+# CHECK: vctzlsbb 2, 3
+0x10 0x41 0x1e 0x02
+
+# CHECK: vctzb 2, 3
+0x10 0x5c 0x1e 0x02
+
+# CHECK: vctzh 2, 3
+0x10 0x5d 0x1e 0x02
+
+# CHECK: vctzw 2, 3
+0x10 0x5e 0x1e 0x02
+
+# CHECK: vctzd 2, 3
+0x10 0x5f 0x1e 0x02
+
+# CHECK: vextsb2w 2, 3
+0x10 0x50 0x1e 0x02
+
+# CHECK: vextsh2w 2, 3
+0x10 0x51 0x1e 0x02
+
+# CHECK: vextsb2d 2, 3
+0x10 0x58 0x1e 0x02
+
+# CHECK: vextsh2d 2, 3
+0x10 0x59 0x1e 0x02
+
+# CHECK: vextsw2d 2, 3
+0x10 0x5a 0x1e 0x02
+
+# CHECK: vnegw 2, 3
+0x10 0x46 0x1e 0x02
+
+# CHECK: vnegd 2, 3
+0x10 0x47 0x1e 0x02
+
+# CHECK: vprtybw 2, 3
+0x10 0x48 0x1e 0x02
+
+# CHECK: vprtybd 2, 3
+0x10 0x49 0x1e 0x02
+
+# CHECK: vprtybq 2, 3
+0x10 0x4a 0x1e 0x02
+
+# CHECK: vbpermd 2, 5, 17
+0x10 0x45 0x8d 0xcc
+
+# CHECK: vpermr 2, 3, 4, 5
+0x10 0x43 0x21 0x7b
+
+# CHECK: vrlwnm 2, 3, 4
+0x10 0x43 0x21 0x85
+
+# CHECK: vrlwmi 2, 3, 4
+0x10 0x43 0x20 0x85
+
+# CHECK: vrldnm 2, 3, 4
+0x10 0x43 0x21 0xc5
+
+# CHECK: vrldmi 2, 3, 4
+0x10 0x43 0x20 0xc5
+
+# CHECK: vslv 2, 3, 4
+0x10 0x43 0x27 0x44
+
+# CHECK: vsrv 2, 3, 4
+0x10 0x43 0x27 0x04
+
+# CHECK: vmul10uq 2, 3
+0x10 0x43 0x02 0x01
+
+# CHECK: vmul10cuq 2, 3
+0x10 0x43 0x00 0x01
+
+# CHECK: vmul10euq 2, 3, 4
+0x10 0x43 0x22 0x41
+
+# CHECK: vmul10ecuq 2, 3, 4
+0x10 0x43 0x20 0x41

test/MC/PowerPC/ppc64-encoding-vmx.s

 
 # CHECK-BE: mtvscr 2                        # encoding: [0x10,0x00,0x16,0x44]
 # CHECK-LE: mtvscr 2                        # encoding: [0x44,0x16,0x00,0x10]
             mtvscr 2
 # CHECK-BE: mfvscr 2                        # encoding: [0x10,0x40,0x06,0x04]
 # CHECK-LE: mfvscr 2                        # encoding: [0x04,0x06,0x40,0x10]
             mfvscr 2
 
+# Power9 instructions
+
+# Vector Count Trailing Zeros
+# CHECK-BE: vctzb 2, 3                      # encoding: [0x10,0x5c,0x1e,0x02]
+# CHECK-LE: vctzb 2, 3                      # encoding: [0x02,0x1e,0x5c,0x10]
+            vctzb 2, 3
+# CHECK-BE: vctzh 2, 3                      # encoding: [0x10,0x5d,0x1e,0x02]
+# CHECK-LE: vctzh 2, 3                      # encoding: [0x02,0x1e,0x5d,0x10]
+            vctzh 2, 3
+# CHECK-BE: vctzw 2, 3                      # encoding: [0x10,0x5e,0x1e,0x02]
+# CHECK-LE: vctzw 2, 3                      # encoding: [0x02,0x1e,0x5e,0x10]
+            vctzw 2, 3
+# CHECK-BE: vctzd 2, 3                      # encoding: [0x10,0x5f,0x1e,0x02]
+# CHECK-LE: vctzd 2, 3                      # encoding: [0x02,0x1e,0x5f,0x10]
+            vctzd 2, 3
+
+# CHECK-BE: vclzlsbb 2, 3                   # encoding: [0x10,0x40,0x1e,0x02]
+# CHECK-LE: vclzlsbb 2, 3                   # encoding: [0x02,0x1e,0x40,0x10]
+            vclzlsbb 2, 3
+# CHECK-BE: vctzlsbb 2, 3                   # encoding: [0x10,0x41,0x1e,0x02]
+# CHECK-LE: vctzlsbb 2, 3                   # encoding: [0x02,0x1e,0x41,0x10]
+            vctzlsbb 2, 3
+
+# Vector Extend Sign
+# CHECK-BE: vextsb2w 2, 3                   # encoding: [0x10,0x50,0x1e,0x02]
+# CHECK-LE: vextsb2w 2, 3                   # encoding: [0x02,0x1e,0x50,0x10]
+            vextsb2w 2, 3
+# CHECK-BE: vextsh2w 2, 3                   # encoding: [0x10,0x51,0x1e,0x02]
+# CHECK-LE: vextsh2w 2, 3                   # encoding: [0x02,0x1e,0x51,0x10]
+            vextsh2w 2, 3
+# CHECK-BE: vextsb2d 2, 3                   # encoding: [0x10,0x58,0x1e,0x02]
+# CHECK-LE: vextsb2d 2, 3                   # encoding: [0x02,0x1e,0x58,0x10]
+            vextsb2d 2, 3
+# CHECK-BE: vextsh2d 2, 3                   # encoding: [0x10,0x59,0x1e,0x02]
+# CHECK-LE: vextsh2d 2, 3                   # encoding: [0x02,0x1e,0x59,0x10]
+            vextsh2d 2, 3
+# CHECK-BE: vextsw2d 2, 3                   # encoding: [0x10,0x5a,0x1e,0x02]
+# CHECK-LE: vextsw2d 2, 3                   # encoding: [0x02,0x1e,0x5a,0x10]
+            vextsw2d 2, 3
+
+# Vector Integer Negate
+# CHECK-BE: vnegw 2, 3                      # encoding: [0x10,0x46,0x1e,0x02]
+# CHECK-LE: vnegw 2, 3                      # encoding: [0x02,0x1e,0x46,0x10]
+            vnegw 2, 3
+# CHECK-BE: vnegd 2, 3                      # encoding: [0x10,0x47,0x1e,0x02]
+# CHECK-LE: vnegd 2, 3                      # encoding: [0x02,0x1e,0x47,0x10]
+            vnegd 2, 3
+
+# Vector Parity Byte
+# CHECK-BE: vprtybw 2, 3                    # encoding: [0x10,0x48,0x1e,0x02]
+# CHECK-LE: vprtybw 2, 3                    # encoding: [0x02,0x1e,0x48,0x10]
+            vprtybw 2, 3
+# CHECK-BE: vprtybd 2, 3                    # encoding: [0x10,0x49,0x1e,0x02]
+# CHECK-LE: vprtybd 2, 3                    # encoding: [0x02,0x1e,0x49,0x10]
+            vprtybd 2, 3
+# CHECK-BE: vprtybq 2, 3                    # encoding: [0x10,0x4a,0x1e,0x02]
+# CHECK-LE: vprtybq 2, 3                    # encoding: [0x02,0x1e,0x4a,0x10]
+            vprtybq 2, 3
+
+# Vector (Bit) Permute (Right-indexed)
+# CHECK-BE: vbpermd 2, 5, 17                # encoding: [0x10,0x45,0x8d,0xcc]
+# CHECK-LE: vbpermd 2, 5, 17                # encoding: [0xcc,0x8d,0x45,0x10]
+            vbpermd 2, 5, 17
+# CHECK-BE: vpermr 2, 3, 4, 5               # encoding: [0x10,0x43,0x21,0x7b]
+# CHECK-LE: vpermr 2, 3, 4, 5               # encoding: [0x7b,0x21,0x43,0x10]
+            vpermr 2, 3, 4, 5
+
+# Vector Rotate Left Mask/Mask-Insert
+# CHECK-BE: vrlwnm 2, 3, 4                  # encoding: [0x10,0x43,0x21,0x85]
+# CHECK-LE: vrlwnm 2, 3, 4                  # encoding: [0x85,0x21,0x43,0x10]
+            vrlwnm 2, 3, 4
+# CHECK-BE: vrlwmi 2, 3, 4                  # encoding: [0x10,0x43,0x20,0x85]
+# CHECK-LE: vrlwmi 2, 3, 4                  # encoding: [0x85,0x20,0x43,0x10]
+            vrlwmi 2, 3, 4
+# CHECK-BE: vrldnm 2, 3, 4                  # encoding: [0x10,0x43,0x21,0xc5]
+# CHECK-LE: vrldnm 2, 3, 4                  # encoding: [0xc5,0x21,0x43,0x10]
+            vrldnm 2, 3, 4
+# CHECK-BE: vrldmi 2, 3, 4                  # encoding: [0x10,0x43,0x20,0xc5]
+# CHECK-LE: vrldmi 2, 3, 4                  # encoding: [0xc5,0x20,0x43,0x10]
+            vrldmi 2, 3, 4
+
+# Vector Shift Left/Right
+# CHECK-BE: vslv 2, 3, 4                    # encoding: [0x10,0x43,0x27,0x44]
+# CHECK-LE: vslv 2, 3, 4                    # encoding: [0x44,0x27,0x43,0x10]
+            vslv 2, 3, 4
+# CHECK-BE: vsrv 2, 3, 4                    # encoding: [0x10,0x43,0x27,0x04]
+# CHECK-LE: vsrv 2, 3, 4                    # encoding: [0x04,0x27,0x43,0x10]
+            vsrv 2, 3, 4
+
+# Vector Multiply-by-10
+# CHECK-BE: vmul10uq 2, 3                   # encoding: [0x10,0x43,0x02,0x01]
+# CHECK-LE: vmul10uq 2, 3                   # encoding: [0x01,0x02,0x43,0x10]
+            vmul10uq 2, 3
+# CHECK-BE: vmul10cuq 2, 3                  # encoding: [0x10,0x43,0x00,0x01]
+# CHECK-LE: vmul10cuq 2, 3                  # encoding: [0x01,0x00,0x43,0x10]
+            vmul10cuq 2, 3
+# CHECK-BE: vmul10euq 2, 3, 4               # encoding: [0x10,0x43,0x22,0x41]
+# CHECK-LE: vmul10euq 2, 3, 4               # encoding: [0x41,0x22,0x43,0x10]
+            vmul10euq 2, 3, 4
+# CHECK-BE: vmul10ecuq 2, 3, 4              # encoding: [0x10,0x43,0x20,0x41]
+# CHECK-LE: vmul10ecuq 2, 3, 4              # encoding: [0x41,0x20,0x43,0x10]
+            vmul10ecuq 2, 3, 4