[Power9] The Patch is Merged to D15916

[kbarton]

Summary

No longer to review this patch.

[hfinkel]

Is this patch missing a change to lib/Target/PowerPC/PPC.td?

[cycheng]

Yes, I will submit new patch later.

Yesterday I only updated http://reviews.llvm.org/D15887 and http://reviews.llvm.org/D15916

I've read your comment, I'm fixing the placement of 'bool IsP9;' and Nemanja's comment.

[kbarton]

I'm closing this because based on the comments, this has been merged into D15916. If that is incorrect, please reopen.

[kbarton]

I'm closing this because based on the comments, this has been merged into D15916. If that is incorrect, please reopen.

lib/Target/PowerPC/PPCInstrAltivec.td

 def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast",
                               int_ppc_altivec_crypto_vcipherlast, v2i64>;
 def VNCIPHER : VX1_Int_Ty<1352, "vncipher",
                           int_ppc_altivec_crypto_vncipher, v2i64>;
 def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast",
                               int_ppc_altivec_crypto_vncipherlast, v2i64>;
 def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;
 } // HasP8Crypto
+
+def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">;
+let Predicates = [HasP9Altivec] in {
+
+// Vector Extract Unsigned
+// Its VX-Form is [PO VRT / UIM VRB XO], and we can use VXForm_1 to implement
+// it. That means we use "VRA" (5 bit) to represent "/ UIM" (1 + 4 bit)
+class VEXTR<bits<11> xo, string opc>
+  : VXForm_1<xo, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
+              !strconcat(opc, " $vD, $vB, $UIMM"), IIC_VecGeneral,
+              []>;
+
+def VEXTRACTUB : VEXTR<525, "vextractub">;
+def VEXTRACTUH : VEXTR<589, "vextractuh">;
+def VEXTRACTUW : VEXTR<653, "vextractuw">;
+def VEXTRACTD  : VEXTR<717, "vextractd">;
+
+// Vector Extract Unsigned Left/Right-Indexed
+class VEXTR_2<bits<11> xo, string opc>
+  : VXForm_1<xo, (outs g8rc:$rD), (ins g8rc:$rA, vrrc:$vB),
+             !strconcat(opc, " $rD, $rA, $vB"), IIC_VecGeneral,
+             []>;
+
+def VEXTUBLX : VEXTR_2<1549, "vextublx">;
+def VEXTUBRX : VEXTR_2<1805, "vextubrx">;
+def VEXTUHLX : VEXTR_2<1613, "vextuhlx">;
+def VEXTUHRX : VEXTR_2<1869, "vextuhrx">;
+def VEXTUWLX : VEXTR_2<1677, "vextuwlx">;
+def VEXTUWRX : VEXTR_2<1933, "vextuwrx">;
+} // end HasP9Altivec

lib/Target/PowerPC/PPCSubtarget.h

protected:
   bool IsPPC64;
   bool HasAltivec;
   bool HasSPE;
   bool HasQPX;
   bool HasVSX;
   bool HasP8Vector;
   bool HasP8Altivec;
   bool HasP8Crypto;
+  bool HasP9Altivec;
   bool HasFCPSGN;
   bool HasFSQRT;
   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
   bool HasRecipPrec;
   bool HasSTFIWX;
   bool HasLFIWAX;
   bool HasFPRND;
   bool HasFPCVT;
public:
   bool hasFPCVT() const { return HasFPCVT; }
   bool hasAltivec() const { return HasAltivec; }
   bool hasSPE() const { return HasSPE; }
   bool hasQPX() const { return HasQPX; }
   bool hasVSX() const { return HasVSX; }
   bool hasP8Vector() const { return HasP8Vector; }
   bool hasP8Altivec() const { return HasP8Altivec; }
   bool hasP8Crypto() const { return HasP8Crypto; }
+  bool hasP9Altivec() const { return HasP9Altivec; }
   bool hasMFOCRF() const { return HasMFOCRF; }
   bool hasISEL() const { return HasISEL; }
   bool hasPOPCNTD() const { return HasPOPCNTD; }
   bool hasBPERMD() const { return HasBPERMD; }
   bool hasExtDiv() const { return HasExtDiv; }
   bool hasCMPB() const { return HasCMPB; }
   bool hasLDBRX() const { return HasLDBRX; }
   bool isBookE() const { return IsBookE; }

lib/Target/PowerPC/PPCSubtarget.cpp

void PPCSubtarget::initializeEnvironment() {
   UseSoftFloat = false;
   HasAltivec = false;
   HasSPE = false;
   HasQPX = false;
   HasVSX = false;
   HasP8Vector = false;
   HasP8Altivec = false;
   HasP8Crypto = false;
+  HasP9Altivec = false;
   HasFCPSGN = false;
   HasFSQRT = false;
   HasFRE = false;
   HasFRES = false;
   HasFRSQRTE = false;
   HasFRSQRTES = false;
   HasRecipPrec = false;
   HasSTFIWX = false;

test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt

 0x10 0x40 0x1f 0xc3
 
 # CHECK: mtvscr 2                        
 0x10 0x00 0x16 0x44
 
 # CHECK: mfvscr 2                        
 0x10 0x40 0x06 0x04
 
+# CHECK: vextractub 2, 3, 15
+0x10 0x4f 0x1a 0x0d
+
+# CHECK: vextractuh 2, 3, 14
+0x10 0x4e 0x1a 0x4d
+
+# CHECK: vextractuw 2, 3, 12
+0x10 0x4c 0x1a 0x8d
+
+# CHECK: vextractd 2, 3, 8
+0x10 0x48 0x1a 0xcd
+
+# CHECK: vextublx 2, 3, 4
+0x10 0x43 0x26 0x0d
+
+# CHECK: vextubrx 2, 3, 4
+0x10 0x43 0x27 0x0d
+
+# CHECK: vextuhlx 2, 3, 4
+0x10 0x43 0x26 0x4d
+
+# CHECK: vextuhrx 2, 3, 4
+0x10 0x43 0x27 0x4d
+
+# CHECK: vextuwlx 2, 3, 4
+0x10 0x43 0x26 0x8d
+
+# CHECK: vextuwrx 2, 3, 4
+0x10 0x43 0x27 0x8d
+

test/MC/PowerPC/ppc64-encoding-vmx.s

 
 # CHECK-BE: mtvscr 2                        # encoding: [0x10,0x00,0x16,0x44]
 # CHECK-LE: mtvscr 2                        # encoding: [0x44,0x16,0x00,0x10]
             mtvscr 2
 # CHECK-BE: mfvscr 2                        # encoding: [0x10,0x40,0x06,0x04]
 # CHECK-LE: mfvscr 2                        # encoding: [0x04,0x06,0x40,0x10]
             mfvscr 2
 
+# Vector Extract Unsigned
+# CHECK-BE: vextractub 2, 3, 15             # encoding: [0x10,0x4f,0x1a,0x0d]
+# CHECK-LE: vextractub 2, 3, 15             # encoding: [0x0d,0x1a,0x4f,0x10]
+            vextractub 2, 3, 15
+# CHECK-BE: vextractuh 2, 3, 14             # encoding: [0x10,0x4e,0x1a,0x4d]
+# CHECK-LE: vextractuh 2, 3, 14             # encoding: [0x4d,0x1a,0x4e,0x10]
+            vextractuh 2, 3, 14
+# CHECK-BE: vextractuw 2, 3, 12             # encoding: [0x10,0x4c,0x1a,0x8d]
+# CHECK-LE: vextractuw 2, 3, 12             # encoding: [0x8d,0x1a,0x4c,0x10]
+            vextractuw 2, 3, 12
+# CHECK-BE: vextractd 2, 3, 8               # encoding: [0x10,0x48,0x1a,0xcd]
+# CHECK-LE: vextractd 2, 3, 8               # encoding: [0xcd,0x1a,0x48,0x10]
+            vextractd 2, 3, 8
+
+# Vector Extract Unsigned Left/Right-Indexed
+# CHECK-BE: vextublx 2, 3, 4                # encoding: [0x10,0x43,0x26,0x0d]
+# CHECK-LE: vextublx 2, 3, 4                # encoding: [0x0d,0x26,0x43,0x10]
+            vextublx 2, 3, 4
+# CHECK-BE: vextubrx 2, 3, 4                # encoding: [0x10,0x43,0x27,0x0d]
+# CHECK-LE: vextubrx 2, 3, 4                # encoding: [0x0d,0x27,0x43,0x10]
+            vextubrx 2, 3, 4
+# CHECK-BE: vextuhlx 2, 3, 4                # encoding: [0x10,0x43,0x26,0x4d]
+# CHECK-LE: vextuhlx 2, 3, 4                # encoding: [0x4d,0x26,0x43,0x10]
+            vextuhlx 2, 3, 4
+# CHECK-BE: vextuhrx 2, 3, 4                # encoding: [0x10,0x43,0x27,0x4d]
+# CHECK-LE: vextuhrx 2, 3, 4                # encoding: [0x4d,0x27,0x43,0x10]
+            vextuhrx 2, 3, 4
+# CHECK-BE: vextuwlx 2, 3, 4                # encoding: [0x10,0x43,0x26,0x8d]
+# CHECK-LE: vextuwlx 2, 3, 4                # encoding: [0x8d,0x26,0x43,0x10]
+            vextuwlx 2, 3, 4
+# CHECK-BE: vextuwrx 2, 3, 4                # encoding: [0x10,0x43,0x27,0x8d]
+# CHECK-LE: vextuwrx 2, 3, 4                # encoding: [0x8d,0x27,0x43,0x10]
+            vextuwrx 2, 3, 4
+