Add 64/128 bit arm neon register definitions on linux

[tberghammer]

Summary

Add 64/128 bit arm neon register definitions on linux

[labath]

Seems legit, but @omjavaid can probably better verify the relationships among these registers. However, I would like to request some tests for this. AFAIK, we don't have a lot of (if any) arm-specific register tests. E.g. TestRegisters is skipped for non-x86 arches, so we could use this opportunity to add some arm-specific tests there.

source/Plugins/Process/Utility/RegisterInfos_arm.h

41 ↗

(On Diff #41134)

Was removing DBG_OFFSET intentional?

[omjavaid]

Some minor typos inline comments.

I havnt applied nd tested this patch. Are you able to read these registers, i guess you need to generate neon or vfp code to test all registers properly.

There no arm register test to my knowledge currently in testsuite we can put this as a future todo to verify we are writing and reading properly.

source/Plugins/Process/Utility/RegisterInfos_arm.h

316 ↗

(On Diff #41134)

here fpu_s24 is being repeated twice instead of fpu_s26.

317 ↗

(On Diff #41134)

here fpu_s28 is being repeated twice instead of fpu_s30.

[tberghammer]

I made some of the tests in TestRegisters.py arm compatible (see D15010) and we also test register read/write in some extent with the gdb remote protocol tests (they caught several issues while I was doing this patch)

source/Plugins/Process/Utility/RegisterInfos_arm.h

41 ↗

(On Diff #41134)

Yes because we don't use it in this file

316 ↗

(On Diff #41134)

Nice catch

317 ↗

(On Diff #41134)

Nice catch

[omjavaid]

LGTM

lldb/trunk/source/Core/Scalar.cpp

switch (reg_info->encoding)
             {
                 m_integer = llvm::APInt(BITWIDTH_INT128, NUM_OF_WORDS_INT128, ((const type128 *)m_integer.getRawData())->x);
                 m_type = e_sint128;
             }
             break;
         case eEncodingIEEE754:
             if (byte_size == sizeof(float))
             {
-                m_float = llvm::APFloat(m_float.convertToFloat());
+                bool losesInfo = false;
+                m_float.convert(llvm::APFloat::IEEEsingle, llvm::APFloat::rmTowardZero, &losesInfo);
                 m_type = e_float;
             }
             else if (byte_size == sizeof(double))
             {
-                m_float = llvm::APFloat(m_float.convertToDouble());
+                bool losesInfo = false;
+                m_float.convert(llvm::APFloat::IEEEdouble, llvm::APFloat::rmTowardZero, &losesInfo);
                 m_type = e_double;
             }
             else if (byte_size == sizeof(long double))
             {
                 if(m_ieee_quad)
                      m_float = llvm::APFloat(llvm::APFloat::IEEEquad, m_float.bitcastToAPInt());
                  else
                      m_float = llvm::APFloat(llvm::APFloat::x87DoubleExtended, m_float.bitcastToAPInt());
                 m_type = e_long_double;
             }
             break;
         case eEncodingVector:
             m_type = e_void;
             break;
     }
 }

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp

static const uint32_t g_fpu_regnums_arm[] =
     fpu_s25_arm,
     fpu_s26_arm,
     fpu_s27_arm,
     fpu_s28_arm,
     fpu_s29_arm,
     fpu_s30_arm,
     fpu_s31_arm,
     fpu_fpscr_arm,
+    fpu_d0_arm,
+    fpu_d1_arm,
+    fpu_d2_arm,
+    fpu_d3_arm,
+    fpu_d4_arm,
+    fpu_d5_arm,
+    fpu_d6_arm,
+    fpu_d7_arm,
+    fpu_d8_arm,
+    fpu_d9_arm,
+    fpu_d10_arm,
+    fpu_d11_arm,
+    fpu_d12_arm,
+    fpu_d13_arm,
+    fpu_d14_arm,
+    fpu_d15_arm,
+    fpu_d16_arm,
+    fpu_d17_arm,
+    fpu_d18_arm,
+    fpu_d19_arm,
+    fpu_d20_arm,
+    fpu_d21_arm,
+    fpu_d22_arm,
+    fpu_d23_arm,
+    fpu_d24_arm,
+    fpu_d25_arm,
+    fpu_d26_arm,
+    fpu_d27_arm,
+    fpu_d28_arm,
+    fpu_d29_arm,
+    fpu_d30_arm,
+    fpu_d31_arm,
+    fpu_q0_arm,
+    fpu_q1_arm,
+    fpu_q2_arm,
+    fpu_q3_arm,
+    fpu_q4_arm,
+    fpu_q5_arm,
+    fpu_q6_arm,
+    fpu_q7_arm,
+    fpu_q8_arm,
+    fpu_q9_arm,
+    fpu_q10_arm,
+    fpu_q11_arm,
+    fpu_q12_arm,
+    fpu_q13_arm,
+    fpu_q14_arm,
+    fpu_q15_arm,
     LLDB_INVALID_REGNUM // register sets need to end with this flag
 };
 static_assert(((sizeof g_fpu_regnums_arm / sizeof g_fpu_regnums_arm[0]) - 1) == k_num_fpr_registers_arm, \
               "g_fpu_regnums_arm has wrong number of register infos");
 
 namespace {
     // Number of register sets provided by this context.
     enum
switch (reg_info->byte_size)
             reg_value.SetUInt16(*(uint16_t *)src);
             break;
         case 4:
             reg_value.SetUInt32(*(uint32_t *)src);
             break;
         case 8:
             reg_value.SetUInt64(*(uint64_t *)src);
             break;
+        case 16:
+            reg_value.SetBytes(src, 16, GetByteOrder());
+            break;
         default:
             assert(false && "Unhandled data size.");
             error.SetErrorStringWithFormat ("unhandled byte size: %" PRIu32, reg_info->byte_size);
             break;
     }
 
     return error;
 }

lldb/trunk/source/Plugins/Process/Utility/RegisterContextFreeBSD_arm.cpp

 
 using namespace lldb;
 using namespace lldb_private;
 
 // Based on RegisterContextLinux_arm.cpp and
 // http://svnweb.freebsd.org/base/head/sys/arm/include/reg.h
 #define GPR_OFFSET(idx) ((idx) * 4)
 #define FPU_OFFSET(idx) ((idx) * 4 + sizeof (RegisterContextFreeBSD_arm::GPR))
+#define FPSCR_OFFSET (LLVM_EXTENSION offsetof (RegisterContextFreeBSD_arm::FPU, fpscr) + sizeof (RegisterContextFreeBSD_arm::GPR))
 #define EXC_OFFSET(idx) ((idx) * 4 + sizeof (RegisterContextFreeBSD_arm::GPR) + sizeof (RegisterContextFreeBSD_arm::FPU))
 #define DBG_OFFSET(reg) ((LLVM_EXTENSION offsetof (RegisterContextFreeBSD_arm::DBG, reg) + sizeof (RegisterContextFreeBSD_arm::GPR) + sizeof (RegisterContextFreeBSD_arm::FPU) + sizeof (RegisterContextFreeBSD_arm::EXC)))
 
 #define DEFINE_DBG(reg, i)  #reg, NULL, sizeof(((RegisterContextFreeBSD_arm::DBG *)NULL)->reg[i]), DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, dbg_##reg##i }, NULL, NULL
 #define REG_CONTEXT_SIZE (sizeof (RegisterContextFreeBSD_arm::GPR) + sizeof (RegisterContextFreeBSD_arm::FPU) + sizeof (RegisterContextFreeBSD_arm::EXC))
 
 //-----------------------------------------------------------------------------
 // Include RegisterInfos_arm to declare our g_register_infos_arm structure.

lldb/trunk/source/Plugins/Process/Utility/RegisterContextLinux_arm.cpp

 #include "RegisterContextLinux_arm.h"
 
 using namespace lldb;
 using namespace lldb_private;
 
 // Based on RegisterContextDarwin_arm.cpp
 #define GPR_OFFSET(idx) ((idx) * 4)
 #define FPU_OFFSET(idx) ((idx) * 4 + sizeof (RegisterContextLinux_arm::GPR))
+#define FPSCR_OFFSET (LLVM_EXTENSION offsetof (RegisterContextLinux_arm::FPU, fpscr) + sizeof (RegisterContextLinux_arm::GPR))
 #define EXC_OFFSET(idx) ((idx) * 4 + sizeof (RegisterContextLinux_arm::GPR) + sizeof (RegisterContextLinux_arm::FPU))
 #define DBG_OFFSET(reg) ((LLVM_EXTENSION offsetof (RegisterContextLinux_arm::DBG, reg) + sizeof (RegisterContextLinux_arm::GPR) + sizeof (RegisterContextLinux_arm::FPU) + sizeof (RegisterContextLinux_arm::EXC)))
 
 #define DEFINE_DBG(reg, i)  #reg, NULL, sizeof(((RegisterContextLinux_arm::DBG *)NULL)->reg[i]), DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, dbg_##reg##i }, NULL, NULL
 #define REG_CONTEXT_SIZE (sizeof (RegisterContextLinux_arm::GPR) + sizeof (RegisterContextLinux_arm::FPU) + sizeof (RegisterContextLinux_arm::EXC))
 
 //-----------------------------------------------------------------------------
 // Include RegisterInfos_arm to declare our g_register_infos_arm structure.

lldb/trunk/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp

static const uint32_t g_fpu_regnums_arm[] =
     fpu_s25_arm,
     fpu_s26_arm,
     fpu_s27_arm,
     fpu_s28_arm,
     fpu_s29_arm,
     fpu_s30_arm,
     fpu_s31_arm,
     fpu_fpscr_arm,
+    fpu_d0_arm,
+    fpu_d1_arm,
+    fpu_d2_arm,
+    fpu_d3_arm,
+    fpu_d4_arm,
+    fpu_d5_arm,
+    fpu_d6_arm,
+    fpu_d7_arm,
+    fpu_d8_arm,
+    fpu_d9_arm,
+    fpu_d10_arm,
+    fpu_d11_arm,
+    fpu_d12_arm,
+    fpu_d13_arm,
+    fpu_d14_arm,
+    fpu_d15_arm,
+    fpu_d16_arm,
+    fpu_d17_arm,
+    fpu_d18_arm,
+    fpu_d19_arm,
+    fpu_d20_arm,
+    fpu_d21_arm,
+    fpu_d22_arm,
+    fpu_d23_arm,
+    fpu_d24_arm,
+    fpu_d25_arm,
+    fpu_d26_arm,
+    fpu_d27_arm,
+    fpu_d28_arm,
+    fpu_d29_arm,
+    fpu_d30_arm,
+    fpu_d31_arm,
+    fpu_q0_arm,
+    fpu_q1_arm,
+    fpu_q2_arm,
+    fpu_q3_arm,
+    fpu_q4_arm,
+    fpu_q5_arm,
+    fpu_q6_arm,
+    fpu_q7_arm,
+    fpu_q8_arm,
+    fpu_q9_arm,
+    fpu_q10_arm,
+    fpu_q11_arm,
+    fpu_q12_arm,
+    fpu_q13_arm,
+    fpu_q14_arm,
+    fpu_q15_arm,
     LLDB_INVALID_REGNUM // register sets need to end with this flag
 
 };
 static_assert(((sizeof g_fpu_regnums_arm / sizeof g_fpu_regnums_arm[0]) - 1) == k_num_fpr_registers_arm, \
               "g_fpu_regnums_arm has wrong number of register infos");
 
 // Number of register sets provided by this context.
 enum

lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_arm.h

 #ifndef GPR_OFFSET
 #error GPR_OFFSET must be defined before including this header file
 #endif
 
 #ifndef FPU_OFFSET
 #error FPU_OFFSET must be defined before including this header file
 #endif
 
-#ifndef EXC_OFFSET
-#error EXC_OFFSET_NAME must be defined before including this header file
+#ifndef FPSCR_OFFSET
+#error FPSCR_OFFSET must be defined before including this header file
 #endif
 
-#ifndef DBG_OFFSET
-#error DBG_OFFSET_NAME must be defined before including this header file
+#ifndef EXC_OFFSET
+#error EXC_OFFSET_NAME must be defined before including this header file
 #endif
 
 #ifndef DEFINE_DBG
 #error DEFINE_DBG must be defined before including this header file
 #endif
 
 enum
 {
enum
     fpu_s26,
     fpu_s27,
     fpu_s28,
     fpu_s29,
     fpu_s30,
     fpu_s31,
     fpu_fpscr,
 
+    fpu_d0,
+    fpu_d1,
+    fpu_d2,
+    fpu_d3,
+    fpu_d4,
+    fpu_d5,
+    fpu_d6,
+    fpu_d7,
+    fpu_d8,
+    fpu_d9,
+    fpu_d10,
+    fpu_d11,
+    fpu_d12,
+    fpu_d13,
+    fpu_d14,
+    fpu_d15,
+    fpu_d16,
+    fpu_d17,
+    fpu_d18,
+    fpu_d19,
+    fpu_d20,
+    fpu_d21,
+    fpu_d22,
+    fpu_d23,
+    fpu_d24,
+    fpu_d25,
+    fpu_d26,
+    fpu_d27,
+    fpu_d28,
+    fpu_d29,
+    fpu_d30,
+    fpu_d31,
+
+    fpu_q0,
+    fpu_q1,
+    fpu_q2,
+    fpu_q3,
+    fpu_q4,
+    fpu_q5,
+    fpu_q6,
+    fpu_q7,
+    fpu_q8,
+    fpu_q9,
+    fpu_q10,
+    fpu_q11,
+    fpu_q12,
+    fpu_q13,
+    fpu_q14,
+    fpu_q15,
+
     exc_exception,
     exc_fsr,
     exc_far,
 
     dbg_bvr0,
     dbg_bvr1,
     dbg_bvr2,
     dbg_bvr3,
enum
     dbg_wcr12,
     dbg_wcr13,
     dbg_wcr14,
     dbg_wcr15,
 
     k_num_registers
 };
 
+static uint32_t g_s0_invalidates[]  = { fpu_d0,  fpu_q0, LLDB_INVALID_REGNUM };
+static uint32_t g_s1_invalidates[]  = { fpu_d0,  fpu_q0, LLDB_INVALID_REGNUM };
+static uint32_t g_s2_invalidates[]  = { fpu_d1,  fpu_q0, LLDB_INVALID_REGNUM };
+static uint32_t g_s3_invalidates[]  = { fpu_d1,  fpu_q0, LLDB_INVALID_REGNUM };
+static uint32_t g_s4_invalidates[]  = { fpu_d2,  fpu_q1, LLDB_INVALID_REGNUM };
+static uint32_t g_s5_invalidates[]  = { fpu_d2,  fpu_q1, LLDB_INVALID_REGNUM };
+static uint32_t g_s6_invalidates[]  = { fpu_d3,  fpu_q1, LLDB_INVALID_REGNUM };
+static uint32_t g_s7_invalidates[]  = { fpu_d3,  fpu_q1, LLDB_INVALID_REGNUM };
+static uint32_t g_s8_invalidates[]  = { fpu_d4,  fpu_q2, LLDB_INVALID_REGNUM };
+static uint32_t g_s9_invalidates[]  = { fpu_d4,  fpu_q2, LLDB_INVALID_REGNUM };
+static uint32_t g_s10_invalidates[] = { fpu_d5,  fpu_q2, LLDB_INVALID_REGNUM };
+static uint32_t g_s11_invalidates[] = { fpu_d5,  fpu_q2, LLDB_INVALID_REGNUM };
+static uint32_t g_s12_invalidates[] = { fpu_d6,  fpu_q3, LLDB_INVALID_REGNUM };
+static uint32_t g_s13_invalidates[] = { fpu_d6,  fpu_q3, LLDB_INVALID_REGNUM };
+static uint32_t g_s14_invalidates[] = { fpu_d7,  fpu_q3, LLDB_INVALID_REGNUM };
+static uint32_t g_s15_invalidates[] = { fpu_d7,  fpu_q3, LLDB_INVALID_REGNUM };
+static uint32_t g_s16_invalidates[] = { fpu_d8,  fpu_q4, LLDB_INVALID_REGNUM };
+static uint32_t g_s17_invalidates[] = { fpu_d8,  fpu_q4, LLDB_INVALID_REGNUM };
+static uint32_t g_s18_invalidates[] = { fpu_d9,  fpu_q4, LLDB_INVALID_REGNUM };
+static uint32_t g_s19_invalidates[] = { fpu_d9,  fpu_q4, LLDB_INVALID_REGNUM };
+static uint32_t g_s20_invalidates[] = { fpu_d10, fpu_q5, LLDB_INVALID_REGNUM };
+static uint32_t g_s21_invalidates[] = { fpu_d10, fpu_q5, LLDB_INVALID_REGNUM };
+static uint32_t g_s22_invalidates[] = { fpu_d11, fpu_q5, LLDB_INVALID_REGNUM };
+static uint32_t g_s23_invalidates[] = { fpu_d11, fpu_q5, LLDB_INVALID_REGNUM };
+static uint32_t g_s24_invalidates[] = { fpu_d12, fpu_q6, LLDB_INVALID_REGNUM };
+static uint32_t g_s25_invalidates[] = { fpu_d12, fpu_q6, LLDB_INVALID_REGNUM };
+static uint32_t g_s26_invalidates[] = { fpu_d13, fpu_q6, LLDB_INVALID_REGNUM };
+static uint32_t g_s27_invalidates[] = { fpu_d13, fpu_q6, LLDB_INVALID_REGNUM };
+static uint32_t g_s28_invalidates[] = { fpu_d14, fpu_q7, LLDB_INVALID_REGNUM };
+static uint32_t g_s29_invalidates[] = { fpu_d14, fpu_q7, LLDB_INVALID_REGNUM };
+static uint32_t g_s30_invalidates[] = { fpu_d15, fpu_q7, LLDB_INVALID_REGNUM };
+static uint32_t g_s31_invalidates[] = { fpu_d15, fpu_q7, LLDB_INVALID_REGNUM };
+
+static uint32_t g_d0_contains[] =  { fpu_s0,  fpu_s1,  LLDB_INVALID_REGNUM };
+static uint32_t g_d1_contains[] =  { fpu_s2,  fpu_s3,  LLDB_INVALID_REGNUM };
+static uint32_t g_d2_contains[] =  { fpu_s4,  fpu_s5,  LLDB_INVALID_REGNUM };
+static uint32_t g_d3_contains[] =  { fpu_s6,  fpu_s7,  LLDB_INVALID_REGNUM };
+static uint32_t g_d4_contains[] =  { fpu_s8,  fpu_s9,  LLDB_INVALID_REGNUM };
+static uint32_t g_d5_contains[] =  { fpu_s10, fpu_s11, LLDB_INVALID_REGNUM };
+static uint32_t g_d6_contains[] =  { fpu_s12, fpu_s13, LLDB_INVALID_REGNUM };
+static uint32_t g_d7_contains[] =  { fpu_s14, fpu_s15, LLDB_INVALID_REGNUM };
+static uint32_t g_d8_contains[] =  { fpu_s16, fpu_s17, LLDB_INVALID_REGNUM };
+static uint32_t g_d9_contains[] =  { fpu_s18, fpu_s19, LLDB_INVALID_REGNUM };
+static uint32_t g_d10_contains[] = { fpu_s20, fpu_s21, LLDB_INVALID_REGNUM };
+static uint32_t g_d11_contains[] = { fpu_s22, fpu_s23, LLDB_INVALID_REGNUM };
+static uint32_t g_d12_contains[] = { fpu_s24, fpu_s25, LLDB_INVALID_REGNUM };
+static uint32_t g_d13_contains[] = { fpu_s26, fpu_s27, LLDB_INVALID_REGNUM };
+static uint32_t g_d14_contains[] = { fpu_s28, fpu_s29, LLDB_INVALID_REGNUM };
+static uint32_t g_d15_contains[] = { fpu_s30, fpu_s31, LLDB_INVALID_REGNUM };
+
+static uint32_t g_d0_invalidates[]  = { fpu_q0, LLDB_INVALID_REGNUM };
+static uint32_t g_d1_invalidates[]  = { fpu_q0, LLDB_INVALID_REGNUM };
+static uint32_t g_d2_invalidates[]  = { fpu_q1, LLDB_INVALID_REGNUM };
+static uint32_t g_d3_invalidates[]  = { fpu_q1, LLDB_INVALID_REGNUM };
+static uint32_t g_d4_invalidates[]  = { fpu_q2, LLDB_INVALID_REGNUM };
+static uint32_t g_d5_invalidates[]  = { fpu_q2, LLDB_INVALID_REGNUM };
+static uint32_t g_d6_invalidates[]  = { fpu_q3, LLDB_INVALID_REGNUM };
+static uint32_t g_d7_invalidates[]  = { fpu_q3, LLDB_INVALID_REGNUM };
+static uint32_t g_d8_invalidates[]  = { fpu_q4, LLDB_INVALID_REGNUM };
+static uint32_t g_d9_invalidates[]  = { fpu_q4, LLDB_INVALID_REGNUM };
+static uint32_t g_d10_invalidates[] = { fpu_q5, LLDB_INVALID_REGNUM };
+static uint32_t g_d11_invalidates[] = { fpu_q5, LLDB_INVALID_REGNUM };
+static uint32_t g_d12_invalidates[] = { fpu_q6, LLDB_INVALID_REGNUM };
+static uint32_t g_d13_invalidates[] = { fpu_q6, LLDB_INVALID_REGNUM };
+static uint32_t g_d14_invalidates[] = { fpu_q7, LLDB_INVALID_REGNUM };
+static uint32_t g_d15_invalidates[] = { fpu_q7, LLDB_INVALID_REGNUM };
+static uint32_t g_d16_invalidates[] = { fpu_q8, LLDB_INVALID_REGNUM };
+static uint32_t g_d17_invalidates[] = { fpu_q8, LLDB_INVALID_REGNUM };
+static uint32_t g_d18_invalidates[] = { fpu_q9, LLDB_INVALID_REGNUM };
+static uint32_t g_d19_invalidates[] = { fpu_q9, LLDB_INVALID_REGNUM };
+static uint32_t g_d20_invalidates[] = { fpu_q10, LLDB_INVALID_REGNUM };
+static uint32_t g_d21_invalidates[] = { fpu_q10, LLDB_INVALID_REGNUM };
+static uint32_t g_d22_invalidates[] = { fpu_q11, LLDB_INVALID_REGNUM };
+static uint32_t g_d23_invalidates[] = { fpu_q11, LLDB_INVALID_REGNUM };
+static uint32_t g_d24_invalidates[] = { fpu_q12, LLDB_INVALID_REGNUM };
+static uint32_t g_d25_invalidates[] = { fpu_q12, LLDB_INVALID_REGNUM };
+static uint32_t g_d26_invalidates[] = { fpu_q13, LLDB_INVALID_REGNUM };
+static uint32_t g_d27_invalidates[] = { fpu_q13, LLDB_INVALID_REGNUM };
+static uint32_t g_d28_invalidates[] = { fpu_q14, LLDB_INVALID_REGNUM };
+static uint32_t g_d29_invalidates[] = { fpu_q14, LLDB_INVALID_REGNUM };
+static uint32_t g_d30_invalidates[] = { fpu_q15, LLDB_INVALID_REGNUM };
+static uint32_t g_d31_invalidates[] = { fpu_q15, LLDB_INVALID_REGNUM };
+
+static uint32_t g_q0_contains[] =  { fpu_d0,  fpu_d1,  fpu_s0,  fpu_s1,  fpu_s2,  fpu_s3,  LLDB_INVALID_REGNUM };
+static uint32_t g_q1_contains[] =  { fpu_d2,  fpu_d3,  fpu_s4,  fpu_s5,  fpu_s6,  fpu_s7,  LLDB_INVALID_REGNUM };
+static uint32_t g_q2_contains[] =  { fpu_d4,  fpu_d5,  fpu_s8,  fpu_s9,  fpu_s10, fpu_s11, LLDB_INVALID_REGNUM };
+static uint32_t g_q3_contains[] =  { fpu_d6,  fpu_d7,  fpu_s12, fpu_s13, fpu_s14, fpu_s15, LLDB_INVALID_REGNUM };
+static uint32_t g_q4_contains[] =  { fpu_d8,  fpu_d9,  fpu_s16, fpu_s17, fpu_s18, fpu_s19, LLDB_INVALID_REGNUM };
+static uint32_t g_q5_contains[] =  { fpu_d10, fpu_d11, fpu_s20, fpu_s21, fpu_s22, fpu_s23, LLDB_INVALID_REGNUM };
+static uint32_t g_q6_contains[] =  { fpu_d12, fpu_d13, fpu_s24, fpu_s25, fpu_s26, fpu_s27, LLDB_INVALID_REGNUM };
+static uint32_t g_q7_contains[] =  { fpu_d14, fpu_d15, fpu_s28, fpu_s29, fpu_s30, fpu_s31, LLDB_INVALID_REGNUM };
+static uint32_t g_q8_contains[] =  { fpu_d16, fpu_d17, LLDB_INVALID_REGNUM };
+static uint32_t g_q9_contains[] =  { fpu_d18, fpu_d19, LLDB_INVALID_REGNUM };
+static uint32_t g_q10_contains[] = { fpu_d20, fpu_d21, LLDB_INVALID_REGNUM };
+static uint32_t g_q11_contains[] = { fpu_d22, fpu_d23, LLDB_INVALID_REGNUM };
+static uint32_t g_q12_contains[] = { fpu_d24, fpu_d25, LLDB_INVALID_REGNUM };
+static uint32_t g_q13_contains[] = { fpu_d26, fpu_d27, LLDB_INVALID_REGNUM };
+static uint32_t g_q14_contains[] = { fpu_d28, fpu_d29, LLDB_INVALID_REGNUM };
+static uint32_t g_q15_contains[] = { fpu_d30, fpu_d31, LLDB_INVALID_REGNUM };
+
 static RegisterInfo g_register_infos_arm[] = {
-// General purpose registers
-//  NAME        ALT     SZ  OFFSET              ENCODING        FORMAT          EH_FRAME                DWARF               GENERIC                     PROCESS PLUGIN          LLDB NATIVE   VALUE REGS    INVALIDATE REGS
-//  ======      ======= ==  =============       =============   ============    ===============         ===============     =========================   =====================   ============= ==========    ===============
-{   "r0",       nullptr, 4, GPR_OFFSET(0),      eEncodingUint,  eFormatHex,     { ehframe_r0,           dwarf_r0,           LLDB_REGNUM_GENERIC_ARG1,   LLDB_INVALID_REGNUM,    gpr_r0      },      nullptr,        nullptr},
-{   "r1",       nullptr, 4, GPR_OFFSET(1),      eEncodingUint,  eFormatHex,     { ehframe_r1,           dwarf_r1,           LLDB_REGNUM_GENERIC_ARG2,   LLDB_INVALID_REGNUM,    gpr_r1      },      nullptr,        nullptr},
-{   "r2",       nullptr, 4, GPR_OFFSET(2),      eEncodingUint,  eFormatHex,     { ehframe_r2,           dwarf_r2,           LLDB_REGNUM_GENERIC_ARG3,   LLDB_INVALID_REGNUM,    gpr_r2      },      nullptr,        nullptr},
-{   "r3",       nullptr, 4, GPR_OFFSET(3),      eEncodingUint,  eFormatHex,     { ehframe_r3,           dwarf_r3,           LLDB_REGNUM_GENERIC_ARG4,   LLDB_INVALID_REGNUM,    gpr_r3      },      nullptr,        nullptr},
-{   "r4",       nullptr, 4, GPR_OFFSET(4),      eEncodingUint,  eFormatHex,     { ehframe_r4,           dwarf_r4,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    gpr_r4      },      nullptr,        nullptr},
-{   "r5",       nullptr, 4, GPR_OFFSET(5),      eEncodingUint,  eFormatHex,     { ehframe_r5,           dwarf_r5,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    gpr_r5      },      nullptr,        nullptr},
-{   "r6",       nullptr, 4, GPR_OFFSET(6),      eEncodingUint,  eFormatHex,     { ehframe_r6,           dwarf_r6,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    gpr_r6      },      nullptr,        nullptr},
-{   "r7",       nullptr, 4, GPR_OFFSET(7),      eEncodingUint,  eFormatHex,     { ehframe_r7,           dwarf_r7,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    gpr_r7      },      nullptr,        nullptr},
-{   "r8",       nullptr, 4, GPR_OFFSET(8),      eEncodingUint,  eFormatHex,     { ehframe_r8,           dwarf_r8,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    gpr_r8      },      nullptr,        nullptr},
-{   "r9",       nullptr, 4, GPR_OFFSET(9),      eEncodingUint,  eFormatHex,     { ehframe_r9,           dwarf_r9,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    gpr_r9      },      nullptr,        nullptr},
-{   "r10",      nullptr, 4, GPR_OFFSET(10),     eEncodingUint,  eFormatHex,     { ehframe_r10,          dwarf_r10,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    gpr_r10     },      nullptr,        nullptr},
-{   "r11",      nullptr, 4, GPR_OFFSET(11),     eEncodingUint,  eFormatHex,     { ehframe_r11,          dwarf_r11,          LLDB_REGNUM_GENERIC_FP,     LLDB_INVALID_REGNUM,    gpr_r11     },      nullptr,        nullptr},
-{   "r12",      nullptr, 4, GPR_OFFSET(12),     eEncodingUint,  eFormatHex,     { ehframe_r12,          dwarf_r12,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    gpr_r12     },      nullptr,        nullptr},
-{   "sp",       "r13",   4, GPR_OFFSET(13),     eEncodingUint,  eFormatHex,     { ehframe_sp,           dwarf_sp,           LLDB_REGNUM_GENERIC_SP,     LLDB_INVALID_REGNUM,    gpr_sp      },      nullptr,        nullptr},
-{   "lr",       "r14",   4, GPR_OFFSET(14),     eEncodingUint,  eFormatHex,     { ehframe_lr,           dwarf_lr,           LLDB_REGNUM_GENERIC_RA,     LLDB_INVALID_REGNUM,    gpr_lr      },      nullptr,        nullptr},
-{   "pc",       "r15",   4, GPR_OFFSET(15),     eEncodingUint,  eFormatHex,     { ehframe_pc,           dwarf_pc,           LLDB_REGNUM_GENERIC_PC,     LLDB_INVALID_REGNUM,    gpr_pc      },      nullptr,        nullptr},
-{   "cpsr",     "psr",   4, GPR_OFFSET(16),     eEncodingUint,  eFormatHex,     { ehframe_cpsr,         dwarf_cpsr,         LLDB_REGNUM_GENERIC_FLAGS,  LLDB_INVALID_REGNUM,    gpr_cpsr    },      nullptr,        nullptr},
+//  NAME         ALT     SZ   OFFSET          ENCODING          FORMAT                  EH_FRAME             DWARF                GENERIC                     PROCESS PLUGIN       LLDB NATIVE      VALUE REGS      INVALIDATE REGS
+//  ===========  ======= ==   ==============  ================  ====================    ===================  ===================  ==========================  ===================  =============    ==============  =================
+{   "r0",        nullptr, 4,  GPR_OFFSET(0),  eEncodingUint,    eFormatHex,           { ehframe_r0,          dwarf_r0,            LLDB_REGNUM_GENERIC_ARG1,   LLDB_INVALID_REGNUM, gpr_r0        }, nullptr,        nullptr           },
+{   "r1",        nullptr, 4,  GPR_OFFSET(1),  eEncodingUint,    eFormatHex,           { ehframe_r1,          dwarf_r1,            LLDB_REGNUM_GENERIC_ARG2,   LLDB_INVALID_REGNUM, gpr_r1        }, nullptr,        nullptr           },
+{   "r2",        nullptr, 4,  GPR_OFFSET(2),  eEncodingUint,    eFormatHex,           { ehframe_r2,          dwarf_r2,            LLDB_REGNUM_GENERIC_ARG3,   LLDB_INVALID_REGNUM, gpr_r2        }, nullptr,        nullptr           },
+{   "r3",        nullptr, 4,  GPR_OFFSET(3),  eEncodingUint,    eFormatHex,           { ehframe_r3,          dwarf_r3,            LLDB_REGNUM_GENERIC_ARG4,   LLDB_INVALID_REGNUM, gpr_r3        }, nullptr,        nullptr           },
+{   "r4",        nullptr, 4,  GPR_OFFSET(4),  eEncodingUint,    eFormatHex,           { ehframe_r4,          dwarf_r4,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, gpr_r4        }, nullptr,        nullptr           },
+{   "r5",        nullptr, 4,  GPR_OFFSET(5),  eEncodingUint,    eFormatHex,           { ehframe_r5,          dwarf_r5,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, gpr_r5        }, nullptr,        nullptr           },
+{   "r6",        nullptr, 4,  GPR_OFFSET(6),  eEncodingUint,    eFormatHex,           { ehframe_r6,          dwarf_r6,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, gpr_r6        }, nullptr,        nullptr           },
+{   "r7",        nullptr, 4,  GPR_OFFSET(7),  eEncodingUint,    eFormatHex,           { ehframe_r7,          dwarf_r7,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, gpr_r7        }, nullptr,        nullptr           },
+{   "r8",        nullptr, 4,  GPR_OFFSET(8),  eEncodingUint,    eFormatHex,           { ehframe_r8,          dwarf_r8,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, gpr_r8        }, nullptr,        nullptr           },
+{   "r9",        nullptr, 4,  GPR_OFFSET(9),  eEncodingUint,    eFormatHex,           { ehframe_r9,          dwarf_r9,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, gpr_r9        }, nullptr,        nullptr           },
+{   "r10",       nullptr, 4,  GPR_OFFSET(10), eEncodingUint,    eFormatHex,           { ehframe_r10,         dwarf_r10,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, gpr_r10       }, nullptr,        nullptr           },
+{   "r11",       nullptr, 4,  GPR_OFFSET(11), eEncodingUint,    eFormatHex,           { ehframe_r11,         dwarf_r11,           LLDB_REGNUM_GENERIC_FP,     LLDB_INVALID_REGNUM, gpr_r11       }, nullptr,        nullptr           },
+{   "r12",       nullptr, 4,  GPR_OFFSET(12), eEncodingUint,    eFormatHex,           { ehframe_r12,         dwarf_r12,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, gpr_r12       }, nullptr,        nullptr           },
+{   "sp",        "r13",   4,  GPR_OFFSET(13), eEncodingUint,    eFormatHex,           { ehframe_sp,          dwarf_sp,            LLDB_REGNUM_GENERIC_SP,     LLDB_INVALID_REGNUM, gpr_sp        }, nullptr,        nullptr           },
+{   "lr",        "r14",   4,  GPR_OFFSET(14), eEncodingUint,    eFormatHex,           { ehframe_lr,          dwarf_lr,            LLDB_REGNUM_GENERIC_RA,     LLDB_INVALID_REGNUM, gpr_lr        }, nullptr,        nullptr           },
+{   "pc",        "r15",   4,  GPR_OFFSET(15), eEncodingUint,    eFormatHex,           { ehframe_pc,          dwarf_pc,            LLDB_REGNUM_GENERIC_PC,     LLDB_INVALID_REGNUM, gpr_pc        }, nullptr,        nullptr           },
+{   "cpsr",      "psr",   4,  GPR_OFFSET(16), eEncodingUint,    eFormatHex,           { ehframe_cpsr,        dwarf_cpsr,          LLDB_REGNUM_GENERIC_FLAGS,  LLDB_INVALID_REGNUM, gpr_cpsr      }, nullptr,        nullptr           },
 
-{   "s0",       nullptr, 4, FPU_OFFSET(0),      eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s0,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s0      },      nullptr,        nullptr},
-{   "s1",       nullptr, 4, FPU_OFFSET(1),      eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s1,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s1      },      nullptr,        nullptr},
-{   "s2",       nullptr, 4, FPU_OFFSET(2),      eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s2,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s2      },      nullptr,        nullptr},
-{   "s3",       nullptr, 4, FPU_OFFSET(3),      eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s3,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s3      },      nullptr,        nullptr},
-{   "s4",       nullptr, 4, FPU_OFFSET(4),      eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s4,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s4      },      nullptr,        nullptr},
-{   "s5",       nullptr, 4, FPU_OFFSET(5),      eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s5,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s5      },      nullptr,        nullptr},
-{   "s6",       nullptr, 4, FPU_OFFSET(6),      eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s6,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s6      },      nullptr,        nullptr},
-{   "s7",       nullptr, 4, FPU_OFFSET(7),      eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s7,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s7      },      nullptr,        nullptr},
-{   "s8",       nullptr, 4, FPU_OFFSET(8),      eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s8,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s8      },      nullptr,        nullptr},
-{   "s9",       nullptr, 4, FPU_OFFSET(9),      eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s9,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s9      },      nullptr,        nullptr},
-{   "s10",      nullptr, 4, FPU_OFFSET(10),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s10,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s10     },      nullptr,        nullptr},
-{   "s11",      nullptr, 4, FPU_OFFSET(11),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s11,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s11     },      nullptr,        nullptr},
-{   "s12",      nullptr, 4, FPU_OFFSET(12),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s12,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s12     },      nullptr,        nullptr},
-{   "s13",      nullptr, 4, FPU_OFFSET(13),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s13,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s13     },      nullptr,        nullptr},
-{   "s14",      nullptr, 4, FPU_OFFSET(14),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s14,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s14     },      nullptr,        nullptr},
-{   "s15",      nullptr, 4, FPU_OFFSET(15),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s15,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s15     },      nullptr,        nullptr},
-{   "s16",      nullptr, 4, FPU_OFFSET(16),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s16,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s16     },      nullptr,        nullptr},
-{   "s17",      nullptr, 4, FPU_OFFSET(17),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s17,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s17     },      nullptr,        nullptr},
-{   "s18",      nullptr, 4, FPU_OFFSET(18),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s18,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s18     },      nullptr,        nullptr},
-{   "s19",      nullptr, 4, FPU_OFFSET(19),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s19,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s19     },      nullptr,        nullptr},
-{   "s20",      nullptr, 4, FPU_OFFSET(20),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s20,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s20     },      nullptr,        nullptr},
-{   "s21",      nullptr, 4, FPU_OFFSET(21),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s21,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s21     },      nullptr,        nullptr},
-{   "s22",      nullptr, 4, FPU_OFFSET(22),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s22,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s22     },      nullptr,        nullptr},
-{   "s23",      nullptr, 4, FPU_OFFSET(23),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s23,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s23     },      nullptr,        nullptr},
-{   "s24",      nullptr, 4, FPU_OFFSET(24),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s24,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s24     },      nullptr,        nullptr},
-{   "s25",      nullptr, 4, FPU_OFFSET(25),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s25,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s25     },      nullptr,        nullptr},
-{   "s26",      nullptr, 4, FPU_OFFSET(26),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s26,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s26     },      nullptr,        nullptr},
-{   "s27",      nullptr, 4, FPU_OFFSET(27),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s27,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s27     },      nullptr,        nullptr},
-{   "s28",      nullptr, 4, FPU_OFFSET(28),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s28,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s28     },      nullptr,        nullptr},
-{   "s29",      nullptr, 4, FPU_OFFSET(29),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s29,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s29     },      nullptr,        nullptr},
-{   "s30",      nullptr, 4, FPU_OFFSET(30),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s30,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s30     },      nullptr,        nullptr},
-{   "s31",      nullptr, 4, FPU_OFFSET(31),     eEncodingIEEE754,eFormatFloat,  { LLDB_INVALID_REGNUM,  dwarf_s31,          LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_s31     },      nullptr,        nullptr},
-{   "fpscr",    nullptr, 4, FPU_OFFSET(32),     eEncodingUint,  eFormatHex,     { LLDB_INVALID_REGNUM,  LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    fpu_fpscr   },      nullptr,        nullptr},
+{   "s0",        nullptr, 4,  FPU_OFFSET(0),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s0,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s0        }, nullptr,        g_s0_invalidates  },
+{   "s1",        nullptr, 4,  FPU_OFFSET(1),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s1,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s1        }, nullptr,        g_s1_invalidates  },
+{   "s2",        nullptr, 4,  FPU_OFFSET(2),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s2,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s2        }, nullptr,        g_s2_invalidates  },
+{   "s3",        nullptr, 4,  FPU_OFFSET(3),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s3,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s3        }, nullptr,        g_s3_invalidates  },
+{   "s4",        nullptr, 4,  FPU_OFFSET(4),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s4,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s4        }, nullptr,        g_s4_invalidates  },
+{   "s5",        nullptr, 4,  FPU_OFFSET(5),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s5,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s5        }, nullptr,        g_s5_invalidates  },
+{   "s6",        nullptr, 4,  FPU_OFFSET(6),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s6,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s6        }, nullptr,        g_s6_invalidates  },
+{   "s7",        nullptr, 4,  FPU_OFFSET(7),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s7,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s7        }, nullptr,        g_s7_invalidates  },
+{   "s8",        nullptr, 4,  FPU_OFFSET(8),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s8,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s8        }, nullptr,        g_s8_invalidates  },
+{   "s9",        nullptr, 4,  FPU_OFFSET(9),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s9,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s9        }, nullptr,        g_s9_invalidates  },
+{   "s10",       nullptr, 4,  FPU_OFFSET(10), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s10,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s10       }, nullptr,        g_s10_invalidates },
+{   "s11",       nullptr, 4,  FPU_OFFSET(11), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s11,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s11       }, nullptr,        g_s11_invalidates },
+{   "s12",       nullptr, 4,  FPU_OFFSET(12), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s12,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s12       }, nullptr,        g_s12_invalidates },
+{   "s13",       nullptr, 4,  FPU_OFFSET(13), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s13,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s13       }, nullptr,        g_s13_invalidates },
+{   "s14",       nullptr, 4,  FPU_OFFSET(14), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s14,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s14       }, nullptr,        g_s14_invalidates },
+{   "s15",       nullptr, 4,  FPU_OFFSET(15), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s15,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s15       }, nullptr,        g_s15_invalidates },
+{   "s16",       nullptr, 4,  FPU_OFFSET(16), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s16,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s16       }, nullptr,        g_s16_invalidates },
+{   "s17",       nullptr, 4,  FPU_OFFSET(17), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s17,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s17       }, nullptr,        g_s17_invalidates },
+{   "s18",       nullptr, 4,  FPU_OFFSET(18), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s18,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s18       }, nullptr,        g_s18_invalidates },
+{   "s19",       nullptr, 4,  FPU_OFFSET(19), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s19,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s19       }, nullptr,        g_s19_invalidates },
+{   "s20",       nullptr, 4,  FPU_OFFSET(20), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s20,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s20       }, nullptr,        g_s20_invalidates },
+{   "s21",       nullptr, 4,  FPU_OFFSET(21), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s21,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s21       }, nullptr,        g_s21_invalidates },
+{   "s22",       nullptr, 4,  FPU_OFFSET(22), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s22,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s22       }, nullptr,        g_s22_invalidates },
+{   "s23",       nullptr, 4,  FPU_OFFSET(23), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s23,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s23       }, nullptr,        g_s23_invalidates },
+{   "s24",       nullptr, 4,  FPU_OFFSET(24), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s24,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s24       }, nullptr,        g_s24_invalidates },
+{   "s25",       nullptr, 4,  FPU_OFFSET(25), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s25,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s25       }, nullptr,        g_s25_invalidates },
+{   "s26",       nullptr, 4,  FPU_OFFSET(26), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s26,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s26       }, nullptr,        g_s26_invalidates },
+{   "s27",       nullptr, 4,  FPU_OFFSET(27), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s27,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s27       }, nullptr,        g_s27_invalidates },
+{   "s28",       nullptr, 4,  FPU_OFFSET(28), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s28,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s28       }, nullptr,        g_s28_invalidates },
+{   "s29",       nullptr, 4,  FPU_OFFSET(29), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s29,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s29       }, nullptr,        g_s29_invalidates },
+{   "s30",       nullptr, 4,  FPU_OFFSET(30), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s30,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s30       }, nullptr,        g_s30_invalidates },
+{   "s31",       nullptr, 4,  FPU_OFFSET(31), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_s31,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_s31       }, nullptr,        g_s31_invalidates },
+{   "fpscr",     nullptr, 4,  FPSCR_OFFSET,   eEncodingUint,    eFormatHex,           { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_fpscr     }, nullptr,        nullptr           },
+
+{   "d0",        nullptr, 8,  FPU_OFFSET(0),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d0,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d0        }, g_d0_contains,  g_d0_invalidates  },
+{   "d1",        nullptr, 8,  FPU_OFFSET(2),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d1,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d1        }, g_d1_contains,  g_d1_invalidates  },
+{   "d2",        nullptr, 8,  FPU_OFFSET(4),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d2,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d2        }, g_d2_contains,  g_d2_invalidates  },
+{   "d3",        nullptr, 8,  FPU_OFFSET(6),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d3,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d3        }, g_d3_contains,  g_d3_invalidates  },
+{   "d4",        nullptr, 8,  FPU_OFFSET(8),  eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d4,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d4        }, g_d4_contains,  g_d4_invalidates  },
+{   "d5",        nullptr, 8,  FPU_OFFSET(10), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d5,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d5        }, g_d5_contains,  g_d5_invalidates  },
+{   "d6",        nullptr, 8,  FPU_OFFSET(12), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d6,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d6        }, g_d6_contains,  g_d6_invalidates  },
+{   "d7",        nullptr, 8,  FPU_OFFSET(14), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d7,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d7        }, g_d7_contains,  g_d7_invalidates  },
+{   "d8",        nullptr, 8,  FPU_OFFSET(16), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d8,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d8        }, g_d8_contains,  g_d8_invalidates  },
+{   "d9",        nullptr, 8,  FPU_OFFSET(18), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d9,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d9        }, g_d9_contains,  g_d9_invalidates  },
+{   "d10",       nullptr, 8,  FPU_OFFSET(20), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d10,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d10       }, g_d10_contains, g_d10_invalidates },
+{   "d11",       nullptr, 8,  FPU_OFFSET(22), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d11,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d11       }, g_d11_contains, g_d11_invalidates },
+{   "d12",       nullptr, 8,  FPU_OFFSET(24), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d12,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d12       }, g_d12_contains, g_d12_invalidates },
+{   "d13",       nullptr, 8,  FPU_OFFSET(26), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d13,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d13       }, g_d13_contains, g_d13_invalidates },
+{   "d14",       nullptr, 8,  FPU_OFFSET(28), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d14,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d14       }, g_d14_contains, g_d14_invalidates },
+{   "d15",       nullptr, 8,  FPU_OFFSET(30), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d15,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d15       }, g_d15_contains, g_d15_invalidates },
+{   "d16",       nullptr, 8,  FPU_OFFSET(32), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d16,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d16       }, nullptr,        g_d16_invalidates },
+{   "d17",       nullptr, 8,  FPU_OFFSET(34), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d17,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d17       }, nullptr,        g_d17_invalidates },
+{   "d18",       nullptr, 8,  FPU_OFFSET(36), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d18,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d18       }, nullptr,        g_d18_invalidates },
+{   "d19",       nullptr, 8,  FPU_OFFSET(38), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d19,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d19       }, nullptr,        g_d19_invalidates },
+{   "d20",       nullptr, 8,  FPU_OFFSET(40), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d20,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d20       }, nullptr,        g_d20_invalidates },
+{   "d21",       nullptr, 8,  FPU_OFFSET(42), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d21,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d21       }, nullptr,        g_d21_invalidates },
+{   "d22",       nullptr, 8,  FPU_OFFSET(44), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d22,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d22       }, nullptr,        g_d22_invalidates },
+{   "d23",       nullptr, 8,  FPU_OFFSET(46), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d23,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d23       }, nullptr,        g_d23_invalidates },
+{   "d24",       nullptr, 8,  FPU_OFFSET(48), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d24,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d24       }, nullptr,        g_d24_invalidates },
+{   "d25",       nullptr, 8,  FPU_OFFSET(50), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d25,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d25       }, nullptr,        g_d25_invalidates },
+{   "d26",       nullptr, 8,  FPU_OFFSET(52), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d26,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d26       }, nullptr,        g_d26_invalidates },
+{   "d27",       nullptr, 8,  FPU_OFFSET(54), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d27,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d27       }, nullptr,        g_d27_invalidates },
+{   "d28",       nullptr, 8,  FPU_OFFSET(56), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d28,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d28       }, nullptr,        g_d28_invalidates },
+{   "d29",       nullptr, 8,  FPU_OFFSET(58), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d29,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d29       }, nullptr,        g_d29_invalidates },
+{   "d30",       nullptr, 8,  FPU_OFFSET(60), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d30,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d30       }, nullptr,        g_d30_invalidates },
+{   "d31",       nullptr, 8,  FPU_OFFSET(62), eEncodingIEEE754, eFormatFloat,         { LLDB_INVALID_REGNUM, dwarf_d31,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_d31       }, nullptr,        g_d31_invalidates },
+
+{   "q0",        nullptr, 16, FPU_OFFSET(0),  eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q0,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q0        }, g_q0_contains,  nullptr,          },
+{   "q1",        nullptr, 16, FPU_OFFSET(4),  eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q1,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q1        }, g_q1_contains,  nullptr,          },
+{   "q2",        nullptr, 16, FPU_OFFSET(8),  eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q2,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q2        }, g_q2_contains,  nullptr,          },
+{   "q3",        nullptr, 16, FPU_OFFSET(12), eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q3,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q3        }, g_q3_contains,  nullptr,          },
+{   "q4",        nullptr, 16, FPU_OFFSET(16), eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q4,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q4        }, g_q4_contains,  nullptr,          },
+{   "q5",        nullptr, 16, FPU_OFFSET(20), eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q5,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q5        }, g_q5_contains,  nullptr,          },
+{   "q6",        nullptr, 16, FPU_OFFSET(24), eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q6,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q6        }, g_q6_contains,  nullptr,          },
+{   "q7",        nullptr, 16, FPU_OFFSET(28), eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q7,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q7        }, g_q7_contains,  nullptr,          },
+{   "q8",        nullptr, 16, FPU_OFFSET(32), eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q8,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q8        }, g_q8_contains,  nullptr,          },
+{   "q9",        nullptr, 16, FPU_OFFSET(36), eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q9,            LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q9        }, g_q9_contains,  nullptr,          },
+{   "q10",       nullptr, 16, FPU_OFFSET(40), eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q10,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q10       }, g_q10_contains, nullptr,          },
+{   "q11",       nullptr, 16, FPU_OFFSET(44), eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q11,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q11       }, g_q11_contains, nullptr,          },
+{   "q12",       nullptr, 16, FPU_OFFSET(48), eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q12,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q12       }, g_q12_contains, nullptr,          },
+{   "q13",       nullptr, 16, FPU_OFFSET(52), eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q13,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q13       }, g_q13_contains, nullptr,          },
+{   "q14",       nullptr, 16, FPU_OFFSET(56), eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q14,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q14       }, g_q14_contains, nullptr,          },
+{   "q15",       nullptr, 16, FPU_OFFSET(60), eEncodingVector,  eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_q15,           LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, fpu_q15       }, g_q15_contains, nullptr,          },
 
-{   "exception",nullptr, 4, EXC_OFFSET(0),      eEncodingUint,  eFormatHex,     { LLDB_INVALID_REGNUM,  LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    exc_exception },    nullptr,        nullptr},
-{   "fsr",      nullptr, 4, EXC_OFFSET(1),      eEncodingUint,  eFormatHex,     { LLDB_INVALID_REGNUM,  LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    exc_fsr       },    nullptr,        nullptr},
-{   "far",      nullptr, 4, EXC_OFFSET(2),      eEncodingUint,  eFormatHex,     { LLDB_INVALID_REGNUM,  LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM,    exc_far       },    nullptr,        nullptr},
+{   "exception", nullptr, 4,  EXC_OFFSET(0),  eEncodingUint,    eFormatHex,           { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, exc_exception }, nullptr,           nullptr        },
+{   "fsr",       nullptr, 4,  EXC_OFFSET(1),  eEncodingUint,    eFormatHex,           { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, exc_fsr       }, nullptr,           nullptr        },
+{   "far",       nullptr, 4,  EXC_OFFSET(2),  eEncodingUint,    eFormatHex,           { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,        LLDB_INVALID_REGNUM, exc_far       }, nullptr,           nullptr        },
 
 {   DEFINE_DBG (bvr, 0) },
 {   DEFINE_DBG (bvr, 1) },
 {   DEFINE_DBG (bvr, 2) },
 {   DEFINE_DBG (bvr, 3) },
 {   DEFINE_DBG (bvr, 4) },
 {   DEFINE_DBG (bvr, 5) },
 {   DEFINE_DBG (bvr, 6) },

lldb/trunk/source/Plugins/Process/Utility/lldb-arm-register-enums.h

enum
         fpu_s25_arm,
         fpu_s26_arm,
         fpu_s27_arm,
         fpu_s28_arm,
         fpu_s29_arm,
         fpu_s30_arm,
         fpu_s31_arm,
         fpu_fpscr_arm,
-        k_last_fpr_arm = fpu_fpscr_arm,
+        fpu_d0_arm,
+        fpu_d1_arm,
+        fpu_d2_arm,
+        fpu_d3_arm,
+        fpu_d4_arm,
+        fpu_d5_arm,
+        fpu_d6_arm,
+        fpu_d7_arm,
+        fpu_d8_arm,
+        fpu_d9_arm,
+        fpu_d10_arm,
+        fpu_d11_arm,
+        fpu_d12_arm,
+        fpu_d13_arm,
+        fpu_d14_arm,
+        fpu_d15_arm,
+        fpu_d16_arm,
+        fpu_d17_arm,
+        fpu_d18_arm,
+        fpu_d19_arm,
+        fpu_d20_arm,
+        fpu_d21_arm,
+        fpu_d22_arm,
+        fpu_d23_arm,
+        fpu_d24_arm,
+        fpu_d25_arm,
+        fpu_d26_arm,
+        fpu_d27_arm,
+        fpu_d28_arm,
+        fpu_d29_arm,
+        fpu_d30_arm,
+        fpu_d31_arm,
+        fpu_q0_arm,
+        fpu_q1_arm,
+        fpu_q2_arm,
+        fpu_q3_arm,
+        fpu_q4_arm,
+        fpu_q5_arm,
+        fpu_q6_arm,
+        fpu_q7_arm,
+        fpu_q8_arm,
+        fpu_q9_arm,
+        fpu_q10_arm,
+        fpu_q11_arm,
+        fpu_q12_arm,
+        fpu_q13_arm,
+        fpu_q14_arm,
+        fpu_q15_arm,
+        k_last_fpr_arm = fpu_q15_arm,
         exc_exception_arm,
         exc_fsr_arm,
         exc_far_arm,
 
         dbg_bvr0_arm,
         dbg_bvr1_arm,
         dbg_bvr2_arm,
         dbg_bvr3_arm,