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Differential D13578

Allow generic arm ArchSpec to merge with specific arm ArchSpec; allow Cortex M0-7's to always force thumb mode
ClosedPublic

Authored by jasonmolenda on Oct 8 2015, 7:46 PM.

Details

Reviewers
clayborg
tberghammer
Summary

This patch is to address a few issues I came up with when working on an armcc-generated ELF binary being run on a Cortex-M4 core with lldb. The first problem is that the elf binary comes in as a generic "arm" triple ("arm--") and the second is that we don't see to get any arm/thumb hints about the functions in this binary.

This is a Cortex-M4 ("armv7em") so the instructions are always thumb.

When lldb calls the instruction unwinder (FuncUnwinders::GetUnwindAssemblyProfiler) it gets the object file's arch and merges in the Target's arch via ArchSpec::MergeFrom. The object file has "arm--", the target has "armv7em-unknown-unknown". The changes to MergeFrom allow us to replace the "arm" cpu part of the triple with the Target's "armv7em".

I wanted to centralize the "Cortex M0-M7 are always thumb" special knowledge a little better - we already had two examples where we were checking against specific core types (armv6m, armv7m, armv7em) in the disassembler. So I added a method to ArchSpec to check that. It's a very arm specific method name, but it seems a bit of an arm specific problem that we're trying to identify here.

Down in the instruction emulation I use the ArchSpec method to make sure we don't try to emulate anything as arm because we're missing the arm/thumb hints from the ObjectFile.

I imagine at some point I'll want to do something in SysV-Arm ABI plugin for the DefaultUnwindPlan to say that if this core is always running thumb instructions, the frame pointer is r7 for instance. That default UnwindPlan which uses the arm r11 as a frame pointer is a problem for the unwinder's behavior in a real mixed arm/thumb environment - we sidestep it inside Apple be using r7 as the frame pointer for both types of code.

Tamas, I put you as the reviewer because this is closest to what you work on regularly. Please let me know what you think when you have a chance.

Diff Detail

Repository
rL LLVM

Event Timeline

jasonmolenda updated this revision to Diff 36921.Oct 8 2015, 7:46 PM
jasonmolenda retitled this revision from to Allow generic arm ArchSpec to merge with specific arm ArchSpec; allow Cortex M0-7's to always force thumb mode.
jasonmolenda updated this object.
jasonmolenda added a reviewer: tberghammer.
jasonmolenda set the repository for this revision to rL LLVM.
jasonmolenda added subscribers: lldb-commits, clayborg.
Herald added subscribers: rengolin, aemerson. · View Herald TranscriptOct 8 2015, 7:46 PM
rengolin added a comment.Oct 9 2015, 1:28 AM

Hi Jason,

This has nothing to do with your patch per se, but we have accurate target descriptions in LLVM, and the parser for all the triples and extra options is now publicly available, so I was wondering if (probably after this go in), you could have a look at using these libraries.

I'm of course assuming you already use other LLVM libraries in LLDB, as it would make sense to use the same target description classes to understand about the target without re-writing everything.

Just a thought.

cheers,
--renato

tberghammer edited edge metadata.Oct 9 2015, 5:30 AM

In general I like the approach you are taking and creating IsAlwaysThumbInstructions sounds like a good idea, but I would implement it a bit differently.

llvm::Triple already contains a SubArch field what is filled in from the first part of the triple in case of arm so I would prefer to use that instead because then we update the architecture information inside the Triple also what is used in many places (I would expect that the information you put into the core field will get lost at some place).

Just for curiosity, how do you debug a Cortex-M4 processor? Do you have PlatformJTAG/ProcessJTAG implementations or do you use debugserver on them?

jasonmolenda added a comment.Oct 9 2015, 5:32 PM

Hi Renato & Tamas, thanks for the feedback.

I'm trying to rewrite IsAlwaysThumbInstructions() to use the information that llvm already has, as per Renato's suggestion. The MCSubtargetInfo has a getFeatureBits() method which can indicate ARM::FeatureNoARM. I'm still having a little bit of trouble getting it to build, the ARMFeatures.h is in an unusual location and it indirectly pulls in ARMGenRegisterInfo.inc, ARMGenInstrInfo.inc, and ARMGenSubtargetInfo.inc from the build dir - I'll need to update xcode and cmake to add the $(llvm-build-dir)/lib/Target/ARM/ to the include path for these to be found. I might not have time to finish this tonight, we'll see.

I'm not sure how expensive it is to make an llvm::Target and get the MCSubtargetInfo out of that every call; I may need to save something in an ArchSpec ivar. Maybe just the results of the FeatureBits check.

Tamas, in this case the people developing this are using an apple internal JTAG interface. But I was working with a group a while ago doing some work with a Cortex-M0 generic board using the Segger J-Link jtag device. In both cases, the JTAG speaks generic gdb-remote protocol. lldb doesn't have anything JTAG specific - it's using ProcessGDBRemote and the generic "host" platform. There's no DynamicLoad plugin activated - developers in these environments need to specify where their binaries are loaded to lldb.

rengolin added a comment.Oct 10 2015, 5:18 AM
In D13578#264072, @jasonmolenda wrote:

I'm trying to rewrite IsAlwaysThumbInstructions() to use the information that llvm already has, as per Renato's suggestion. The MCSubtargetInfo has a getFeatureBits() method which can indicate ARM::FeatureNoARM. I'm still having a little bit of trouble getting it to build, the ARMFeatures.h is in an unusual location and it indirectly pulls in ARMGenRegisterInfo.inc, ARMGenInstrInfo.inc, and ARMGenSubtargetInfo.inc from the build dir - I'll need to update xcode and cmake to add the $(llvm-build-dir)/lib/Target/ARM/ to the include path for these to be found. I might not have time to finish this tonight, we'll see.

The target information classes depend on table-generated files, so if you were not building them before, you'll need to do that now. I though LLDB was doing this already, that's why I suggested lightly. But ultimately, I believe you *don't* want to have your own target description anyway, so it's a move that you'd have to do anyway.

I'm not sure how expensive it is to make an llvm::Target and get the MCSubtargetInfo out of that every call; I may need to save something in an ArchSpec ivar. Maybe just the results of the FeatureBits check.

I'm not sure you should be doing that. Those calls normally involve traversing tables and correlating information. Even though that gets optimised pretty well, it's not something that you want to be delaying delicate hardware handling of breakpoints, run states etc.

I'd guess you could have a local cache with only the information you need, and you initialise it from the target description classes once. You may end up with some duplication, but hopefully, it won't be too much and it'll be a lot faster.

--renato

jasonmolenda updated this revision to Diff 37210.Oct 12 2015, 6:54 PM
jasonmolenda edited edge metadata.

Quick update of the patch using the llvm target information. Builds and works correctly on macosx with xcodebuild. Doesn't build with cmake yet; I don't have the includes set up correctly for the llvm build-dir lib/Target/ARM directory yet. Also doesn't cache the result of the llvm target features check.

clayborg accepted this revision.Oct 13 2015, 9:53 AM
clayborg added a reviewer: clayborg.
This revision is now accepted and ready to land.Oct 13 2015, 9:53 AM
tberghammer added inline comments.Oct 13 2015, 9:58 AM
source/Core/ArchSpec.cpp
859–870

I would like to see this part of the code to be replaced with something like this so we store the sub-architecture inside the triple and we don't have to special case arm (it is already done in llvm::Triple):

if (GetTriple().getSubArch() == llvm::Triple::NoSubArch)
    GetTriple().setSubArch(other.GetTriple().getSubArch());
Eugene.Zelenko closed this revision.Sep 26 2016, 5:50 PM
Eugene.Zelenko added a subscriber: Eugene.Zelenko.

Committed in rL265377.

Revision Contents

PathSize
1 line
include/
lldb/
Core/
16 lines
lldb.xcodeproj/
46 lines
source/
Core/
37 lines
5 lines
Plugins/
Disassembler/
llvm/
14 lines
Instruction/
ARM/
18 lines

Diff 37210

Makefile

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# Include LLVM common makefile. # Include LLVM common makefile.
include $(LEVEL)/Makefile.common include $(LEVEL)/Makefile.common
# Set common LLDB build flags. # Set common LLDB build flags.
CPP.Flags += -I$(PROJ_SRC_DIR)/$(LLDB_LEVEL)/include CPP.Flags += -I$(PROJ_SRC_DIR)/$(LLDB_LEVEL)/include
CPP.Flags += -I$(PROJ_OBJ_DIR)/$(LLDB_LEVEL)/include CPP.Flags += -I$(PROJ_OBJ_DIR)/$(LLDB_LEVEL)/include
CPP.Flags += -I$(LLVM_SRC_ROOT)/tools/clang/include CPP.Flags += -I$(LLVM_SRC_ROOT)/tools/clang/include
CPP.Flags += -I$(LLVM_OBJ_ROOT)/tools/clang/include CPP.Flags += -I$(LLVM_OBJ_ROOT)/tools/clang/include
CPP.Flags += -I$(LLVM_OBJ_ROOT)/lib/Target/ARM
CPP.Flags += -I$(PROJ_SRC_DIR)/$(LLDB_LEVEL)/source CPP.Flags += -I$(PROJ_SRC_DIR)/$(LLDB_LEVEL)/source
CPP.Flags += -I$(PROJ_SRC_DIR)/$(LLDB_LEVEL)/source/Utility CPP.Flags += -I$(PROJ_SRC_DIR)/$(LLDB_LEVEL)/source/Utility
CPP.Flags += -I$(PROJ_SRC_DIR)/$(LLDB_LEVEL)/source/Plugins/Process/Utility CPP.Flags += -I$(PROJ_SRC_DIR)/$(LLDB_LEVEL)/source/Plugins/Process/Utility
CPP.Flags += -I$(PROJ_SRC_DIR)/$(LLDB_LEVEL)/source/Plugins/Process/POSIX CPP.Flags += -I$(PROJ_SRC_DIR)/$(LLDB_LEVEL)/source/Plugins/Process/POSIX
# Disable python and curses on mingw build # Disable python and curses on mingw build
ifeq ($(HOST_OS),MingW) ifeq ($(HOST_OS),MingW)
CXXFLAGS += -DLLDB_DISABLE_PYTHON -DLLDB_DISABLE_CURSES CXXFLAGS += -DLLDB_DISABLE_PYTHON -DLLDB_DISABLE_CURSES
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include/lldb/Core/ArchSpec.h

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} }
void void
SetFlags (uint32_t flags) SetFlags (uint32_t flags)
{ {
m_flags = flags; m_flags = flags;
} }
//------------------------------------------------------------------
/// Detect whether this architecture uses thumb code exclusively
///
/// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can
/// only execute the Thumb instructions, never Arm. We should normally
/// pick up arm/thumbness from their the processor status bits (cpsr/xpsr)
/// or hints on each function - but when doing bare-boards low level
/// debugging (especially common with these embedded processors), we may
/// not have those things easily accessible.
///
/// @return true if this is an arm ArchSpec which can only execute Thumb
/// instructions
//------------------------------------------------------------------
bool
IsAlwaysThumbInstructions () const;
protected: protected:
bool bool
IsEqualTo (const ArchSpec& rhs, bool exact_match) const; IsEqualTo (const ArchSpec& rhs, bool exact_match) const;
llvm::Triple m_triple; llvm::Triple m_triple;
Core m_core; Core m_core;
lldb::ByteOrder m_byte_order; lldb::ByteOrder m_byte_order;
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lldb.xcodeproj/project.pbxproj

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name = DebugClang; name = DebugClang;
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isa = XCBuildConfiguration; isa = XCBuildConfiguration;
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CLANG_LINK_OBJC_RUNTIME = NO; CLANG_LINK_OBJC_RUNTIME = NO;
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"$(LLVM_BUILD_DIR)/archives.txt", "$(LLVM_BUILD_DIR)/archives.txt",
"-lxml2", "-lxml2",
"-framework", "-framework",
Foundation, Foundation,
); );
PRODUCT_NAME = "$(TARGET_NAME)"; PRODUCT_NAME = "$(TARGET_NAME)";
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name = Debug; name = Debug;
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isa = XCBuildConfiguration; isa = XCBuildConfiguration;
buildSettings = { buildSettings = {
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"$(LLVM_BUILD_DIR)/archives.txt", "$(LLVM_BUILD_DIR)/archives.txt",
"-lxml2", "-lxml2",
"-framework", "-framework",
Foundation, Foundation,
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PRODUCT_NAME = "$(TARGET_NAME)"; PRODUCT_NAME = "$(TARGET_NAME)";
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"$(LLVM_BUILD_DIR)/archives.txt", "$(LLVM_BUILD_DIR)/archives.txt",
"-lxml2", "-lxml2",
"-framework", "-framework",
Foundation, Foundation,
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PRODUCT_NAME = "$(TARGET_NAME)"; PRODUCT_NAME = "$(TARGET_NAME)";
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buildSettings = { buildSettings = {
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"-lxml2", "-lxml2",
"-framework", "-framework",
Foundation, Foundation,
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PRODUCT_NAME = "$(TARGET_NAME)"; PRODUCT_NAME = "$(TARGET_NAME)";
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CLANG_LINK_OBJC_RUNTIME = NO; CLANG_LINK_OBJC_RUNTIME = NO;
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source/Core/ArchSpec.cpp

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#include "lldb/Target/Process.h" #include "lldb/Target/Process.h"
#include "lldb/Target/RegisterContext.h" #include "lldb/Target/RegisterContext.h"
#include "lldb/Target/Thread.h" #include "lldb/Target/Thread.h"
#include "lldb/Utility/NameMatches.h" #include "lldb/Utility/NameMatches.h"
#include "lldb/Utility/SafeMachO.h" #include "lldb/Utility/SafeMachO.h"
#include "Plugins/Process/Utility/ARMDefines.h" #include "Plugins/Process/Utility/ARMDefines.h"
#include "Plugins/Process/Utility/InstructionUtils.h" #include "Plugins/Process/Utility/InstructionUtils.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/../../lib/Target/ARM/ARMGenRegisterInfo.inc"
#include "llvm/../../lib/Target/ARM/ARMFeatures.h"
using namespace lldb; using namespace lldb;
using namespace lldb_private; using namespace lldb_private;
#define ARCH_SPEC_SEPARATOR_CHAR '-' #define ARCH_SPEC_SEPARATOR_CHAR '-'
static bool cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match); static bool cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match);
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ArchSpec::MergeFrom(const ArchSpec &other) ArchSpec::MergeFrom(const ArchSpec &other)
{ {
if (GetTriple().getVendor() == llvm::Triple::UnknownVendor && !TripleVendorWasSpecified()) if (GetTriple().getVendor() == llvm::Triple::UnknownVendor && !TripleVendorWasSpecified())
GetTriple().setVendor(other.GetTriple().getVendor()); GetTriple().setVendor(other.GetTriple().getVendor());
if (GetTriple().getOS() == llvm::Triple::UnknownOS && !TripleOSWasSpecified()) if (GetTriple().getOS() == llvm::Triple::UnknownOS && !TripleOSWasSpecified())
GetTriple().setOS(other.GetTriple().getOS()); GetTriple().setOS(other.GetTriple().getOS());
if (GetTriple().getArch() == llvm::Triple::UnknownArch) if (GetTriple().getArch() == llvm::Triple::UnknownArch)
GetTriple().setArch(other.GetTriple().getArch()); GetTriple().setArch(other.GetTriple().getArch());
// If this and other are both arm ArchSpecs and this ArchSpec is a generic "some kind of arm"
// spec but the other ArchSpec is a specific arm core, adopt the specific arm core.
if (GetTriple().getArch() == llvm::Triple::arm
&& other.GetTriple().getArch() == llvm::Triple::arm
&& IsCompatibleMatch (other)
&& GetCore() == ArchSpec::eCore_arm_generic
&& other.GetCore() != ArchSpec::eCore_arm_generic)
{
m_core = other.GetCore();
CoreUpdated (true);
}
tberghammerUnsubmitted
Not Done
ReplyInline Actions

I would like to see this part of the code to be replaced with something like this so we store the sub-architecture inside the triple and we don't have to special case arm (it is already done in llvm::Triple):

if (GetTriple().getSubArch() == llvm::Triple::NoSubArch)
    GetTriple().setSubArch(other.GetTriple().getSubArch());
tberghammer: I would like to see this part of the code to be replaced with something like this so we store…
if (GetTriple().getEnvironment() == llvm::Triple::UnknownEnvironment) if (GetTriple().getEnvironment() == llvm::Triple::UnknownEnvironment)
GetTriple().setEnvironment(other.GetTriple().getEnvironment()); GetTriple().setEnvironment(other.GetTriple().getEnvironment());
} }
bool bool
ArchSpec::SetArchitecture (ArchitectureType arch_type, uint32_t cpu, uint32_t sub, uint32_t os) ArchSpec::SetArchitecture (ArchitectureType arch_type, uint32_t cpu, uint32_t sub, uint32_t os)
{ {
m_core = kCore_invalid; m_core = kCore_invalid;
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ArchSpec::StopInfoOverrideCallbackType ArchSpec::StopInfoOverrideCallbackType
ArchSpec::GetStopInfoOverrideCallback () const ArchSpec::GetStopInfoOverrideCallback () const
{ {
const llvm::Triple::ArchType machine = GetMachine(); const llvm::Triple::ArchType machine = GetMachine();
if (machine == llvm::Triple::arm) if (machine == llvm::Triple::arm)
return StopInfoOverrideCallbackTypeARM; return StopInfoOverrideCallbackTypeARM;
return NULL; return NULL;
} }
bool
ArchSpec::IsAlwaysThumbInstructions () const
{
std::string Error;
if (GetTriple().getArch() == llvm::Triple::arm || GetTriple().getArch() == llvm::Triple::thumb)
{
std::string triple (GetTriple().getTriple());
const char *cpu = "";
const char *features_str = "";
const llvm::Target *curr_target = llvm::TargetRegistry::lookupTarget(triple.c_str(), Error);
std::unique_ptr<llvm::MCSubtargetInfo> subtarget_info_up (curr_target->createMCSubtargetInfo(triple.c_str(), cpu, features_str));
if (subtarget_info_up->getFeatureBits()[llvm::ARM::FeatureNoARM])
{
return true;
}
}
return false;
}
Context not available.

source/Core/Disassembler.cpp

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if (flavor == NULL) if (flavor == NULL)
m_flavor.assign("default"); m_flavor.assign("default");
else else
m_flavor.assign(flavor); m_flavor.assign(flavor);
// If this is an arm variant that can only include thumb (T16, T32) // If this is an arm variant that can only include thumb (T16, T32)
// instructions, force the arch triple to be "thumbv.." instead of // instructions, force the arch triple to be "thumbv.." instead of
// "armv..." // "armv..."
if ((arch.GetTriple().getArch() == llvm::Triple::arm || arch.GetTriple().getArch() == llvm::Triple::thumb) if (arch.IsAlwaysThumbInstructions())
&& (arch.GetCore() == ArchSpec::Core::eCore_arm_armv7m
|| arch.GetCore() == ArchSpec::Core::eCore_arm_armv7em
|| arch.GetCore() == ArchSpec::Core::eCore_arm_armv6m))
{ {
std::string thumb_arch_name (arch.GetTriple().getArchName().str()); std::string thumb_arch_name (arch.GetTriple().getArchName().str());
// Replace "arm" with "thumb" so we get all thumb variants correct // Replace "arm" with "thumb" so we get all thumb variants correct
if (thumb_arch_name.size() > 3) if (thumb_arch_name.size() > 3)
{ {
thumb_arch_name.erase(0, 3); thumb_arch_name.erase(0, 3);
thumb_arch_name.insert(0, "thumb"); thumb_arch_name.insert(0, "thumb");
} }
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source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp

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// disassembler will return all instruction. Without it we will see a lot of unknow opcode // disassembler will return all instruction. Without it we will see a lot of unknow opcode
// in case the code uses instructions which are not available in the oldest arm version // in case the code uses instructions which are not available in the oldest arm version
// (used when no sub architecture is specified) // (used when no sub architecture is specified)
if (triple.getArch() == llvm::Triple::arm && triple.getSubArch() == llvm::Triple::NoSubArch) if (triple.getArch() == llvm::Triple::arm && triple.getSubArch() == llvm::Triple::NoSubArch)
triple.setArchName("armv8.1a"); triple.setArchName("armv8.1a");
const char *triple_str = triple.getTriple().c_str(); const char *triple_str = triple.getTriple().c_str();
// v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization // ARM Cortex M0-M7 devices only execute thumb instructions
// if (arch.IsAlwaysThumbInstructions ())
// Cortex-M3 devices (e.g. armv7m) can only execute thumb (T2) instructions,
// so hardcode the primary disassembler to thumb mode. Same for Cortex-M4 (armv7em).
//
// Handle the Cortex-M0 (armv6m) the same; the ISA is a subset of the T and T32
// instructions defined in ARMv7-A.
if ((triple.getArch() == llvm::Triple::arm || triple.getArch() == llvm::Triple::thumb)
&& (arch.GetCore() == ArchSpec::Core::eCore_arm_armv7m
|| arch.GetCore() == ArchSpec::Core::eCore_arm_armv7em
|| arch.GetCore() == ArchSpec::Core::eCore_arm_armv6m))
{ {
triple_str = thumb_arch.GetTriple().getTriple().c_str(); triple_str = thumb_arch.GetTriple().getTriple().c_str();
} }
const char *cpu = ""; const char *cpu = "";
switch (arch.GetCore()) switch (arch.GetCore())
{ {
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source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp

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return m_arm_isa != 0; return m_arm_isa != 0;
} }
bool bool
EmulateInstructionARM::SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target) EmulateInstructionARM::SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target)
{ {
if (EmulateInstruction::SetInstruction (insn_opcode, inst_addr, target)) if (EmulateInstruction::SetInstruction (insn_opcode, inst_addr, target))
{ {
if (m_arch.GetTriple().getArch() == llvm::Triple::thumb) if (m_arch.GetTriple().getArch() == llvm::Triple::thumb || m_arch.IsAlwaysThumbInstructions ())
{
m_opcode_mode = eModeThumb; m_opcode_mode = eModeThumb;
}
else else
{ {
AddressClass addr_class = inst_addr.GetAddressClass(); AddressClass addr_class = inst_addr.GetAddressClass();
if ((addr_class == eAddressClassCode) || (addr_class == eAddressClassUnknown)) if ((addr_class == eAddressClassCode) || (addr_class == eAddressClassUnknown))
m_opcode_mode = eModeARM; m_opcode_mode = eModeARM;
else if (addr_class == eAddressClassCodeAlternateISA) else if (addr_class == eAddressClassCodeAlternateISA)
m_opcode_mode = eModeThumb; m_opcode_mode = eModeThumb;
Show All 18 Lines
{ {
addr_t pc = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS, &success); addr_t pc = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS, &success);
if (success) if (success)
{ {
Context read_inst_context; Context read_inst_context;
read_inst_context.type = eContextReadOpcode; read_inst_context.type = eContextReadOpcode;
read_inst_context.SetNoArgs (); read_inst_context.SetNoArgs ();
if (m_opcode_cpsr & MASK_CPSR_T) if (m_opcode_cpsr & MASK_CPSR_T || m_arch.IsAlwaysThumbInstructions())
{ {
m_opcode_mode = eModeThumb; m_opcode_mode = eModeThumb;
uint32_t thumb_opcode = MemARead(read_inst_context, pc, 2, 0, &success); uint32_t thumb_opcode = MemARead(read_inst_context, pc, 2, 0, &success);
if (success) if (success)
{ {
if ((thumb_opcode & 0xe000) != 0xe000 || ((thumb_opcode & 0x1800u) == 0)) if ((thumb_opcode & 0xe000) != 0xe000 || ((thumb_opcode & 0x1800u) == 0))
{ {
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uint32_t test_opcode; uint32_t test_opcode;
if ((value_sp.get() == NULL) || (value_sp->GetType() != OptionValue::eTypeUInt64)) if ((value_sp.get() == NULL) || (value_sp->GetType() != OptionValue::eTypeUInt64))
{ {
out_stream->Printf ("TestEmulation: Error reading opcode from test file.\n"); out_stream->Printf ("TestEmulation: Error reading opcode from test file.\n");
return false; return false;
} }
test_opcode = value_sp->GetUInt64Value (); test_opcode = value_sp->GetUInt64Value ();
if (arch.GetTriple().getArch() == llvm::Triple::arm) if (arch.GetTriple().getArch() == llvm::Triple::thumb || arch.IsAlwaysThumbInstructions ())
{
m_opcode_mode = eModeARM;
m_opcode.SetOpcode32 (test_opcode, GetByteOrder());
}
else if (arch.GetTriple().getArch() == llvm::Triple::thumb)
{ {
m_opcode_mode = eModeThumb; m_opcode_mode = eModeThumb;
if (test_opcode < 0x10000) if (test_opcode < 0x10000)
m_opcode.SetOpcode16 (test_opcode, GetByteOrder()); m_opcode.SetOpcode16 (test_opcode, GetByteOrder());
else else
m_opcode.SetOpcode32 (test_opcode, GetByteOrder()); m_opcode.SetOpcode32 (test_opcode, GetByteOrder());
} else if (arch.GetTriple().getArch() == llvm::Triple::arm)
{
m_opcode_mode = eModeARM;
m_opcode.SetOpcode32 (test_opcode, GetByteOrder());
} }
else else
{ {
out_stream->Printf ("TestEmulation: Invalid arch.\n"); out_stream->Printf ("TestEmulation: Invalid arch.\n");
return false; return false;
} }
EmulationStateARM before_state; EmulationStateARM before_state;
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