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[AArch64] Lower READCYCLECOUNTER using MRS PMCCTNR_EL0.
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Authored by ab on Aug 27 2015, 6:52 PM.

Details

Summary

This matches the ARM behavior. However, here the lowering isn't guarded
by a "PerfMon" feature: while it is indeed optional on AArch64 as well,
all of the CPUs we support have it, so why pretend.

Diff Detail

Event Timeline

ab updated this revision to Diff 33391.Aug 27 2015, 6:52 PM
ab retitled this revision from to [AArch64] Lower READCYCLECOUNTER using MRS PMCCTNR_EL0..
ab updated this object.
ab added reviewers: jmolloy, t.p.northover.
ab added a subscriber: llvm-commits.
jmolloy requested changes to this revision.Aug 30 2015, 5:54 AM
jmolloy edited edge metadata.

Hi Ahmed,

I'd really prefer this to be predicated on a new feature. I'm happy for the feature to be enabled by default though.

Cheers,

James

lib/Target/AArch64/AArch64ISelLowering.cpp
405

I'd really prefer that this is predicated on a feature.

This revision now requires changes to proceed.Aug 30 2015, 5:54 AM
ab updated this revision to Diff 33646.Aug 31 2015, 4:46 PM
ab edited edge metadata.

Fair enough; here's an updated patch.

jmolloy accepted this revision.Sep 1 2015, 8:34 AM
jmolloy edited edge metadata.

Thanks for making that change Ahmed, LGTM.

James

This revision is now accepted and ready to land.Sep 1 2015, 8:34 AM
This revision was automatically updated to reflect the committed changes.
ab marked an inline comment as done.

Hi @ab,
I was checking this code and I believe that it would be better for the readcyclecounter function to use the CNTVCT_EL0 register (Counter-timer Virtual Count register) instead of the PMCCNTR_EL0 (Performance Monitors Cycle Count Register) because the current one is a PMU register which, depending on PMU configuration, it might always return zeroes and it doesn't guaranteed to always be increased.

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