This matches the ARM behavior. However, here the lowering isn't guarded
by a "PerfMon" feature: while it is indeed optional on AArch64 as well,
all of the CPUs we support have it, so why pretend.
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Hi Ahmed,
I'd really prefer this to be predicated on a new feature. I'm happy for the feature to be enabled by default though.
Cheers,
James
lib/Target/AArch64/AArch64ISelLowering.cpp | ||
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405 ↗ | (On Diff #33391) | I'd really prefer that this is predicated on a feature. |
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Hi @ab,
I was checking this code and I believe that it would be better for the readcyclecounter function to use the CNTVCT_EL0 register (Counter-timer Virtual Count register) instead of the PMCCNTR_EL0 (Performance Monitors Cycle Count Register) because the current one is a PMU register which, depending on PMU configuration, it might always return zeroes and it doesn't guaranteed to always be increased.