[DebugInfo] Fix ARM/AArch64 prologue_end position

[kubamracek]

Summary

It seems that DWARF prologue_end flag, which should be placed right after the function prologue, is often placed at the function entry point for ARM and AArch64. I filed https://llvm.org/bugs/show_bug.cgi?id=24117 about it, where I thought this was a recent regression for -O1, but in fact I found an even easier test case which reproduces this bug with basically all versions of LLVM and at -O0:

int func(void);
void prologue_end_test() {
  func();
  func();
}

compiles to (with -g -O0 -armv7):

_prologue_end_test:
Lfunc_begin0:
    .file   1 "foo.c"
    .loc    1 2 0                   @ foo.c:2:0
    .cfi_startproc
@ BB#0:                                 @ %entry
    .loc    1 3 3 prologue_end      @ foo.c:3:3
    push    {r7, lr}
    mov r7, sp
    sub sp, #8
    bl  _func
    .loc    1 4 3                   @ foo.c:4:3
    str r0, [sp, #4]            @ 4-byte Spill
    bl  _func
    ...

Obviously, the prologue isn't empty, and the prologue_end line should actually be placed before the first bl _func call.

This bug is not present on x86/x86_64. The reason why this happens is that the ARM and AArch64 backends emit line number information for the prologue's MIs. When generating the prologue, the DebugLoc from the first MI is copied to all the instructions of the prologue (but the first MI's DebugLoc can be empty in which case things are fine). The X86 backend doesn't do that and it never assigns line information to the prologue. The DWARF debug info writer attaches the prologue_end flag to the first instruction that has a non-empty debug location.

This patch changes the ARM and AArch64 prologues not to have line information.

[aprantl]

There should be a comment explaining that the DebugLocs are dropped because of the LLVM convention that the prologue end is marked by the first instruction with a non-empty DebugLoc.

[kubamracek]

In D11268#206453, @aprantl wrote:

There should be a comment explaining that the DebugLocs are dropped because of the LLVM convention that the prologue end is marked by the first instruction with a non-empty DebugLoc.

In the test cases or in the backend changes? (Sorry, I'm not really familiar with these parts of LLVM)

[iid_iunknown]

ARM and AArch64 appear to be not the only backends with this problem.
Mips, SystemZ and Sparc backends similarly place prologue_end at the function entry point.

[kubamracek]

BTW, I think this is why ASan test cases, such as https://github.com/llvm-mirror/compiler-rt/blob/master/test/asan/TestCases/use-after-free.cc need to be currently XFAIL'd on ARM.

[kubamracek]

Extending the fix to all backends that attach debug locations to generated prologue. Added test cases for all these targets. Added a comment explaining why we want to use empty/invalid location (actually, I found that comment in the XCore backend, and just copied it).

[asl]

lib/Target/Mips/Mips16InstrInfo.cpp

448

Wow. Looks like MIPS backend certainly deserves a good run of clang-format! (unrelated to this patch :) )

[asl]

In general, LGTM. But we certainly need to ping the maintainers of the backends :)

[kubamracek]

In D11268#209702, @asl wrote:

In general, LGTM. But we certainly need to ping the maintainers of the backends :)

Could you please CC them on this patch?

[rengolin]

LGTM.

[echristo]

One inline comment. My general preference would be an explicit DebugLoc in all of these uses, but maybe it doesn't matter that much. The inline comment does :)

-eric

lib/Target/ARM/ARMFrameLowering.cpp

331–332

The DebugLoc for all uses of emitSPUpdate is now just DebugLoc so you can remove the parameter.

[kubamracek]

lib/Target/ARM/ARMFrameLowering.cpp

331–332

Hm, but emitSPUpdate is also used from emitEpilogue and eliminateCallFramePseudoInstr, where some debug location is still used (and it's not relevant to the bug I'm trying to fix, which is wrong prologue_end in DWARF).

[echristo]

Sure, if you could look at that and write it in a way that doesn't it'd be appreciated because it's mostly dead at this point, but please go ahead here.

-eric

[iid_iunknown]

Hi Kuba,

This review has been hold for some time.
There are merge conflicts with the current trunk now. I rebased your changes, solved the conflicts and updated the patch for your convenience. It is not possible to update someone else's patch so I created a new request: http://reviews.llvm.org/D14338.

Please note that the changes in MipsSEFrameLowering.cpp, MipsSEInstrInfo.cpp, Mips/prologue_end.ll and delay-slot.ll are no longer needed as they have been done in r246309.

The prologue_end.ll tests fail as the subprogram definitions are required to be distinct. They have been marked distinct to make the tests pass.

Would you take a look at the new patch and let me know if you were going to commit your changes, please? I could commit it for you if this would be more convenient.

Thank you.

[kubamracek]

Thanks for doing this! Please go ahead and commit (this patch was already LGTM'd so I think it's okay). Please note that when you commit, you might see a buildbot failure in ARM/AArch64 tests in compiler-rt/sanitizers/ASan/TSan -- this might actually be okay, IIRC there are a few XFAILs because of this bug. Let me know if you see such a test failure.

[iid_iunknown]

Thank you for your review and remarks!
D14338 has been committed. I will let you know if such problems with the tests arise.

lib/Target/AArch64/AArch64FrameLowering.cpp

void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
   const Function *Fn = MF.getFunction();
   const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
       MF.getSubtarget().getRegisterInfo());
   const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
   MachineModuleInfo &MMI = MF.getMMI();
   AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
   bool needsFrameMoves = MMI.hasDebugInfo() || Fn->needsUnwindTableEntry();
   bool HasFP = hasFP(MF);
-  DebugLoc DL = MBB.findDebugLoc(MBBI);
+
+  // Debug location must be unknown since the first debug location is used
+  // to determine the end of the prologue.
+  DebugLoc DL;
 
   // All calls are tail calls in GHC calling conv, and functions have no
   // prologue/epilogue.
   if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
     return;
 
   int NumBytes = (int)MFI->getStackSize();
   if (!AFI->hasStackFrame()) {
bool AArch64FrameLowering::spillCalleeSavedRegisters(
     const std::vector<CalleeSavedInfo> &CSI,
     const TargetRegisterInfo *TRI) const {
   MachineFunction &MF = *MBB.getParent();
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
   unsigned Count = CSI.size();
   DebugLoc DL;
   assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
 
-  if (MI != MBB.end())
-    DL = MI->getDebugLoc();
-
   for (unsigned i = 0; i < Count; i += 2) {
     unsigned idx = Count - i - 2;
     unsigned Reg1 = CSI[idx].getReg();
     unsigned Reg2 = CSI[idx + 1].getReg();
     // GPRs and FPRs are saved in pairs of 64-bit regs. We expect the CSI
     // list to come in sorted by frame index so that we can issue the store
     // pair instructions directly. Assert if we see anything otherwise.
     //

lib/Target/ARM/ARMFrameLowering.cpp

void ARMFrameLowering::emitPrologue(MachineFunction &MF,
   const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
   assert(!AFI->isThumb1OnlyFunction() &&
          "This emitPrologue does not support Thumb1!");
   bool isARM = !AFI->isThumbFunction();
   unsigned Align = STI.getFrameLowering()->getStackAlignment();
   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
   unsigned NumBytes = MFI->getStackSize();
   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
-  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+
+  // Debug location must be unknown since the first debug location is used
+  // to determine the end of the prologue.
+  DebugLoc dl;
+  
   unsigned FramePtr = RegInfo->getFrameRegister(MF);
 
   // Determine the sizes of each callee-save spill areas and record which frame
   // belongs to which callee-save spill areas.
   unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
   int FramePtrSpillFI = 0;
   int D8SpillFI = 0;
 
   // All calls are tail calls in GHC calling conv, and functions have no
   // prologue/epilogue.
   if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
     return;
 
   StackAdjustingInsts DefCFAOffsetCandidates;
   bool HasFP = hasFP(MF);
 
   // Allocate the vararg register save area.
   if (ArgRegsSaveSize) {
     emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
                  MachineInstr::FrameSetup);
     DefCFAOffsetCandidates.addInst(std::prev(MBBI), ArgRegsSaveSize, true);
   }
 
   if (!AFI->hasStackFrame() &&
       (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) {
     if (NumBytes - ArgRegsSaveSize != 0) {
       emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize),
                    MachineInstr::FrameSetup);
void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
                                     bool NoGap,
                                     bool(*Func)(unsigned, bool),
                                     unsigned NumAlignedDPRCS2Regs,
                                     unsigned MIFlags) const {
   MachineFunction &MF = *MBB.getParent();
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
 
   DebugLoc DL;
-  if (MI != MBB.end()) DL = MI->getDebugLoc();
 
   SmallVector<std::pair<unsigned,bool>, 4> Regs;
   unsigned i = CSI.size();
   while (i != 0) {
     unsigned LastReg = 0;
     for (; i != 0; --i) {
       unsigned Reg = CSI[i-1].getReg();
       if (!(Func)(Reg, STI.isTargetDarwin())) continue;

lib/Target/ARM/Thumb1FrameLowering.cpp

void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
   const Thumb1InstrInfo &TII =
       *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
 
   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
   unsigned NumBytes = MFI->getStackSize();
   assert(NumBytes >= ArgRegsSaveSize &&
          "ArgRegsSaveSize is included in NumBytes");
   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
-  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+
+  // Debug location must be unknown since the first debug location is used
+  // to determine the end of the prologue.
+  DebugLoc dl;
+  
   unsigned FramePtr = RegInfo->getFrameRegister(MF);
   unsigned BasePtr = RegInfo->getBaseRegister();
   int CFAOffset = 0;
 
   // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
   NumBytes = (NumBytes + 3) & ~3;
   MFI->setStackSize(NumBytes);
 
case ARM::LR:
       break;
     default:
       DPRCSSize += 8;
     }
   }
 
   if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
     ++MBBI;
-    if (MBBI != MBB.end())
-      dl = MBBI->getDebugLoc();
   }
 
   // Determine starting offsets of spill areas.
   unsigned DPRCSOffset  = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
   unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
   unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
   bool HasFP = hasFP(MF);
   if (HasFP)
spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                           const std::vector<CalleeSavedInfo> &CSI,
                           const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;
 
   DebugLoc DL;
   const TargetInstrInfo &TII = *STI.getInstrInfo();
 
-  if (MI != MBB.end()) DL = MI->getDebugLoc();
-
   MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
   AddDefaultPred(MIB);
   for (unsigned i = CSI.size(); i != 0; --i) {
     unsigned Reg = CSI[i-1].getReg();
     bool isKill = true;
 
     // Add the callee-saved register as live-in unless it's LR and
     // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress

lib/Target/Mips/Mips16FrameLowering.cpp

 
 void Mips16FrameLowering::emitPrologue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
   assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
   MachineFrameInfo *MFI = MF.getFrameInfo();
   const Mips16InstrInfo &TII =
       *static_cast<const Mips16InstrInfo *>(STI.getInstrInfo());
   MachineBasicBlock::iterator MBBI = MBB.begin();
-  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+
+  // Debug location must be unknown since the first debug location is used
+  // to determine the end of the prologue.
+  DebugLoc dl;
+
   uint64_t StackSize = MFI->getStackSize();
 
   // No need to allocate space on the stack.
   if (StackSize == 0 && !MFI->adjustsStack()) return;
 
   MachineModuleInfo &MMI = MF.getMMI();
   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
   MachineLocation DstML, SrcML;

lib/Target/Mips/Mips16ISelDAGToDAG.cpp

void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
 
   if (!MipsFI->globalBaseRegSet())
     return;
 
   MachineBasicBlock &MBB = MF.front();
   MachineBasicBlock::iterator I = MBB.begin();
   MachineRegisterInfo &RegInfo = MF.getRegInfo();
   const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
-  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
+  DebugLoc DL;
   unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
   const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
 
   V0 = RegInfo.createVirtualRegister(RC);
   V1 = RegInfo.createVirtualRegister(RC);
   V2 = RegInfo.createVirtualRegister(RC);
 
   BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0).

lib/Target/Mips/Mips16InstrInfo.cpp

for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
 
     }
   }
 }
 // Adjust SP by FrameSize bytes. Save RA, S0, S1
 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
                                 MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator I) const {
-  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
+  DebugLoc DL;
   MachineFunction &MF = *MBB.getParent();
   MachineFrameInfo *MFI    = MF.getFrameInfo();
   const BitVector Reserved = RI.getReservedRegs(MF);
   bool SaveS2 = Reserved[Mips::S2];
   MachineInstrBuilder MIB;
   unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;
   MIB = BuildMI(MBB, I, DL, get(Opc));
   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();

 // This can only be called at times that we know that there is at least one free
 // register.
 // This is clearly safe at prologue and epilogue.
 //
 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
                                         MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator I,
                                         unsigned Reg1, unsigned Reg2) const {
-  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
+  DebugLoc DL;
   //
   // li reg1, constant
   // move reg2, sp
   // add reg1, reg1, reg2
   // move sp, reg1
   //
   //
   MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);

 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
   if (validSpImm8(Imm))
     return get(Mips::AddiuSpImm16);
   else
     return get(Mips::AddiuSpImmX16);
 }
 
 void Mips16InstrInfo::BuildAddiuSpImm
   (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
-  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
+  DebugLoc DL;
   BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
 }
 
 const MipsInstrInfo *llvm::createMips16InstrInfo(const MipsSubtarget &STI) {
   return new Mips16InstrInfo(STI);
 }
 
 bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,

lib/Target/Mips/MipsSEFrameLowering.cpp

void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 
   const MipsSEInstrInfo &TII =
       *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
   const MipsRegisterInfo &RegInfo =
       *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
 
   MachineBasicBlock::iterator MBBI = MBB.begin();
-  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+
+  // Debug location must be unknown since the first debug location is used
+  // to determine the end of the prologue.
+  DebugLoc dl;
+
   MipsABIInfo ABI = STI.getABI();
   unsigned SP = ABI.GetStackPtr();
   unsigned FP = ABI.GetFramePtr();
   unsigned ZERO = ABI.GetNullPtr();
   unsigned ADDu = ABI.GetPtrAdduOp();
   unsigned ADDiu = ABI.GetPtrAddiuOp();
   unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND;
 

lib/Target/Mips/MipsSEInstrInfo.cpp

unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
   }
 }
 
 /// Adjust SP by Amount bytes.
 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
                                      MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator I) const {
   MipsABIInfo ABI = Subtarget.getABI();
-  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
+  DebugLoc DL;
   unsigned ADDu = ABI.GetPtrAdduOp();
   unsigned ADDiu = ABI.GetPtrAddiuOp();
 
   if (Amount == 0)
     return;
 
   if (isInt<16>(Amount))// addi sp, sp, amount
     BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);

lib/Target/Sparc/SparcFrameLowering.cpp

 
 void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
                                           MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator MBBI,
                                           int NumBytes,
                                           unsigned ADDrr,
                                           unsigned ADDri) const {
 
-  DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
+  DebugLoc dl;
   const SparcInstrInfo &TII =
       *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
 
   if (NumBytes >= -4096 && NumBytes < 4096) {
     BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
       .addReg(SP::O6).addImm(NumBytes);
     return;
   }
void SparcFrameLowering::emitPrologue(MachineFunction &MF,
                                       MachineBasicBlock &MBB) const {
   SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
 
   assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
   MachineFrameInfo *MFI = MF.getFrameInfo();
   const SparcInstrInfo &TII =
       *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
   MachineBasicBlock::iterator MBBI = MBB.begin();
-  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+
+  // Debug location must be unknown since the first debug location is used
+  // to determine the end of the prologue.
+  DebugLoc dl;
 
   // Get the number of bytes to allocate from the FrameInfo
   int NumBytes = (int) MFI->getStackSize();
 
   unsigned SAVEri = SP::SAVEri;
   unsigned SAVErr = SP::SAVErr;
   if (FuncInfo->isLeafProc()) {
     if (NumBytes == 0)

lib/Target/SystemZ/SystemZFrameLowering.cpp

spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                           const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;
 
   MachineFunction &MF = *MBB.getParent();
   const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
   SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
   bool IsVarArg = MF.getFunction()->isVarArg();
-  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+  DebugLoc DL;
 
   // Scan the call-saved GPRs and find the bounds of the register spill area.
   unsigned LowGPR = 0;
   unsigned HighGPR = SystemZ::R15D;
   unsigned StartOffset = -1U;
   for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
     unsigned Reg = CSI[I].getReg();
     if (SystemZ::GR64BitRegClass.contains(Reg)) {
void SystemZFrameLowering::emitPrologue(MachineFunction &MF,
   auto *ZII =
       static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
   SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
   MachineBasicBlock::iterator MBBI = MBB.begin();
   MachineModuleInfo &MMI = MF.getMMI();
   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
   const std::vector<CalleeSavedInfo> &CSI = MFFrame->getCalleeSavedInfo();
   bool HasFP = hasFP(MF);
-  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+
+  // Debug location must be unknown since the first debug location is used
+  // to determine the end of the prologue.
+  DebugLoc DL;
 
   // The current offset of the stack pointer from the CFA.
   int64_t SPOffsetFromCFA = -SystemZMC::CFAOffsetFromInitialSP;
 
   if (ZFI->getLowSavedGPR()) {
     // Skip over the GPR saves.
     if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
       ++MBBI;

lib/Target/X86/X86FrameLowering.cpp

void X86FrameLowering::emitPrologue(MachineFunction &MF,
   bool NeedsDwarfCFI =
       !IsWin64Prologue && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
   unsigned FramePtr = TRI->getFrameRegister(MF);
   const unsigned MachineFramePtr =
       STI.isTarget64BitILP32()
           ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
           : FramePtr;
   unsigned BasePtr = TRI->getBaseRegister();
+  
+  // Debug location must be unknown since the first debug location is used
+  // to determine the end of the prologue.
   DebugLoc DL;
 
   // Add RETADDR move area to callee saved frame size.
   int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
   if (TailCallReturnAddrDelta && IsWin64Prologue)
     report_fatal_error("Can't handle guaranteed tail call under win64 yet");
 
   if (TailCallReturnAddrDelta < 0)

test/DebugInfo/AArch64/prologue_end.ll

+; RUN: llc -disable-fp-elim -O0 %s -mtriple aarch64-apple-darwin -o - | FileCheck %s
+
+; int func(void);
+; void prologue_end_test() {
+;   func();
+;   func();
+; }
+
+define void @prologue_end_test() nounwind uwtable {
+  ; CHECK: prologue_end_test:
+  ; CHECK: .cfi_startproc
+  ; CHECK: stp x29, x30
+  ; CHECK: mov x29, sp
+  ; CHECK: sub sp, sp
+  ; CHECK: .loc 1 3 3 prologue_end
+  ; CHECK: bl _func
+  ; CHECK: bl _func
+entry:
+  %call = call i32 @func(), !dbg !11
+  %call1 = call i32 @func(), !dbg !12
+  ret void, !dbg !13
+}
+
+declare i32 @func()
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7, !8, !9}
+!llvm.ident = !{!10}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 242129)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, subprograms: !3)
+!1 = !DIFile(filename: "foo.c", directory: "/tmp")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "prologue_end_test", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, function: void ()* @prologue_end_test, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{null}
+!7 = !{i32 2, !"Dwarf Version", i32 2}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
+!9 = !{i32 1, !"PIC Level", i32 2}
+!10 = !{!"clang version 3.7.0 (trunk 242129)"}
+!11 = !DILocation(line: 3, column: 3, scope: !4)
+!12 = !DILocation(line: 4, column: 3, scope: !4)
+!13 = !DILocation(line: 5, column: 1, scope: !4)

test/DebugInfo/ARM/prologue_end.ll

+; RUN: llc -disable-fp-elim -O0 %s -mtriple armv7-apple-darwin -o - | FileCheck %s
+; RUN: llc -disable-fp-elim -O0 %s -mtriple thumbv1-apple-darwin -o - | FileCheck %s
+
+; int func(void);
+; void prologue_end_test() {
+;   func();
+;   func();
+; }
+
+define void @prologue_end_test() nounwind uwtable {
+  ; CHECK: prologue_end_test:
+  ; CHECK: .cfi_startproc
+  ; CHECK: push {r7, lr}
+  ; CHECK: {{mov r7, sp|add r7, sp}}
+  ; CHECK: sub sp
+  ; CHECK: .loc 1 3 3 prologue_end
+  ; CHECK: bl {{_func|Ltmp}}
+  ; CHECK: bl {{_func|Ltmp}}
+entry:
+  %call = call i32 @func(), !dbg !13
+  %call1 = call i32 @func(), !dbg !14
+  ret void, !dbg !15
+}
+
+declare i32 @func()
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7, !8, !9, !10, !11}
+!llvm.ident = !{!12}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 242129)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, subprograms: !3)
+!1 = !DIFile(filename: "foo.c", directory: "/tmp")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "prologue_end_test", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, function: void ()* @prologue_end_test, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{null}
+!7 = !{i32 2, !"Dwarf Version", i32 2}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
+!9 = !{i32 1, !"wchar_size", i32 4}
+!10 = !{i32 1, !"min_enum_size", i32 4}
+!11 = !{i32 1, !"PIC Level", i32 2}
+!12 = !{!"clang version 3.7.0 (trunk 242129)"}
+!13 = !DILocation(line: 3, column: 3, scope: !4)
+!14 = !DILocation(line: 4, column: 3, scope: !4)
+!15 = !DILocation(line: 5, column: 1, scope: !4)

test/DebugInfo/Mips/delay-slot.ll

 ; RUN: llc -filetype=obj -O0 < %s -mtriple mips-unknown-linux-gnu | llvm-dwarfdump - | FileCheck %s
 ; PR19815
 
 ; Generated using clang -target mips-linux-gnu -g test.c -S -o - -flto|opt -sroa -S
 ; test.c:
 ;
 ; int foo(int x) {
 ;  if (x)
 ;    return 0;
 ;  return 1;
 ; }
 
 ; CHECK: Address            Line   Column File   ISA Discriminator Flags
 ; CHECK: ------------------ ------ ------ ------ --- ------------- -------------
 ; CHECK: 0x0000000000000000      1      0      1   0             0  is_stmt
-; CHECK: 0x0000000000000000      1      0      1   0             0  is_stmt prologue_end
-; CHECK: 0x0000000000000008      2      0      1   0             0  is_stmt
+; CHECK: 0x0000000000000008      2      0      1   0             0  is_stmt prologue_end
 ; CHECK: 0x0000000000000020      3      0      1   0             0  is_stmt
 ; CHECK: 0x0000000000000030      4      0      1   0             0  is_stmt
 ; CHECK: 0x0000000000000040      5      0      1   0             0  is_stmt
 ; CHECK: 0x0000000000000050      5      0      1   0             0  is_stmt end_sequence
 
 target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
 target triple = "mips--linux-gnu"
 

test/DebugInfo/Mips/prologue_end.ll

+; RUN: llc -disable-fp-elim -O0 %s -mtriple mips-linux-gnu -mcpu mips16 -o - | FileCheck %s
+; RUN: llc -disable-fp-elim -O0 %s -mtriple mips-linux-gnu -mcpu mips32 -o - | FileCheck %s
+
+; int func(void);
+; void prologue_end_test() {
+;   func();
+;   func();
+; }
+
+define void @prologue_end_test() nounwind uwtable {
+  ; CHECK: prologue_end_test:
+  ; CHECK: .cfi_startproc
+  ; CHECK: {{lui|li}}
+  ; CHECK: addiu
+  ; CHECK: .loc 1 3 3 prologue_end
+  ; CHECK: lw {{.*}}, %call16(func)
+  ; CHECK: lw {{.*}}, %call16(func)
+entry:
+  %call = call i32 @func(), !dbg !11
+  %call1 = call i32 @func(), !dbg !12
+  ret void, !dbg !13
+}
+
+declare i32 @func()
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7, !8, !9}
+!llvm.ident = !{!10}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 242129)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, subprograms: !3)
+!1 = !DIFile(filename: "foo.c", directory: "/tmp")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "prologue_end_test", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, function: void ()* @prologue_end_test, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{null}
+!7 = !{i32 2, !"Dwarf Version", i32 2}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
+!9 = !{i32 1, !"PIC Level", i32 2}
+!10 = !{!"clang version 3.7.0 (trunk 242129)"}
+!11 = !DILocation(line: 3, column: 3, scope: !4)
+!12 = !DILocation(line: 4, column: 3, scope: !4)
+!13 = !DILocation(line: 5, column: 1, scope: !4)

test/DebugInfo/Sparc/prologue_end.ll

+; RUN: llc -disable-fp-elim -O0 %s -mtriple sparc -o - | FileCheck %s
+
+; int func(void);
+; void prologue_end_test() {
+;   func();
+;   func();
+; }
+
+define void @prologue_end_test() nounwind uwtable {
+  ; CHECK: prologue_end_test:
+  ; CHECK: .cfi_startproc
+  ; CHECK: save %sp
+  ; CHECK: .loc 1 3 3 prologue_end
+  ; CHECK: call func
+  ; CHECK: call func
+entry:
+  %call = call i32 @func(), !dbg !11
+  %call1 = call i32 @func(), !dbg !12
+  ret void, !dbg !13
+}
+
+declare i32 @func()
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7, !8, !9}
+!llvm.ident = !{!10}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 242129)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, subprograms: !3)
+!1 = !DIFile(filename: "foo.c", directory: "/tmp")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "prologue_end_test", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, function: void ()* @prologue_end_test, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{null}
+!7 = !{i32 2, !"Dwarf Version", i32 2}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
+!9 = !{i32 1, !"PIC Level", i32 2}
+!10 = !{!"clang version 3.7.0 (trunk 242129)"}
+!11 = !DILocation(line: 3, column: 3, scope: !4)
+!12 = !DILocation(line: 4, column: 3, scope: !4)
+!13 = !DILocation(line: 5, column: 1, scope: !4)

test/DebugInfo/SystemZ/prologue_end.ll

+; RUN: llc -disable-fp-elim -O0 %s -mtriple s390x-linux-gnu -o - | FileCheck %s
+
+; int func(void);
+; void prologue_end_test() {
+;   func();
+;   func();
+; }
+
+define void @prologue_end_test() nounwind uwtable {
+  ; CHECK: prologue_end_test:
+  ; CHECK: .cfi_startproc
+  ; CHECK: aghi
+  ; CHECK: lgr
+  ; CHECK: .loc 1 3 3 prologue_end
+  ; CHECK: brasl {{.*}}, func
+  ; CHECK: brasl {{.*}}, func
+entry:
+  %call = call i32 @func(), !dbg !11
+  %call1 = call i32 @func(), !dbg !12
+  ret void, !dbg !13
+}
+
+declare i32 @func()
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7, !8, !9}
+!llvm.ident = !{!10}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 242129)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, subprograms: !3)
+!1 = !DIFile(filename: "foo.c", directory: "/tmp")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "prologue_end_test", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, function: void ()* @prologue_end_test, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{null}
+!7 = !{i32 2, !"Dwarf Version", i32 2}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
+!9 = !{i32 1, !"PIC Level", i32 2}
+!10 = !{!"clang version 3.7.0 (trunk 242129)"}
+!11 = !DILocation(line: 3, column: 3, scope: !4)
+!12 = !DILocation(line: 4, column: 3, scope: !4)
+!13 = !DILocation(line: 5, column: 1, scope: !4)