This is an archive of the discontinued LLVM Phabricator instance.

[MC][ARM] Reject Thumb "ror rX, #0"
ClosedPublic

Authored by rprichard on May 13 2021, 5:30 PM.

Details

Summary

The ROR instruction can only handle immediates between 1 and 31. The
would-be encoding for ROR #0 is actually the RRX instruction.

Diff Detail

Event Timeline

rprichard created this revision.May 13 2021, 5:30 PM
rprichard requested review of this revision.May 13 2021, 5:30 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 13 2021, 5:30 PM
nickdesaulniers accepted this revision.May 14 2021, 12:31 PM
F5.1.160 ROR (immediate)
ROR{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
<imm> For encoding T3: is the shift amount, in the range 1 to 31, encoded in the "imm3:imm2" field.
This revision is now accepted and ready to land.May 14 2021, 12:31 PM
This revision was landed with ongoing or failed builds.May 19 2021, 3:05 PM
This revision was automatically updated to reflect the committed changes.