neon: truncate(smin(smax(a,b),c)) --> vqmovns(a),truncate(smin(a,b)) --> vqmovnu(a)

[fantasyRqg]

Summary

• truncate(smin(smax(a,b),c)) --> vqmovns(a)
• truncate(umin(a,b)) --> vqmovnu(a)

[How to indicate LLVM use VQMOVN.s16 ](https://discuss.tvm.apache.org/t/how-to-indicate-llvm-use-vqmovn-s16/9682)

[fantasyRqg]

fix: wrong bit-width on PerformNeonTruncateMinMaxCombine::IsUnsignedSaturate

[fantasyRqg]

collect all change

[RKSimon]

X86 has some very similar code to recognise saturated trunc pattern matchers (detectUSatPattern + detectSSatPattern) - would it make sense to move them to SelectionDAG and reuse them here?

[fantasyRqg]

In D100938#2707735, @RKSimon wrote:

X86 has some very similar code to recognise saturated trunc pattern matchers (detectUSatPattern + detectSSatPattern) - would it make sense to move them to SelectionDAG and reuse them here?

I will take a look.
I need some time to understand TableGen.

[dmgreen]

Hello. Is it possible to just add a few tablegen patterns for there? As far as I can tell they are just a few nodes combined into one, and (unlike on MVE) we will not need to optimize them further.

[RKSimon]

In D100938#2707800, @fantasyRqg wrote:

In D100938#2707735, @RKSimon wrote:

X86 has some very similar code to recognise saturated trunc pattern matchers (detectUSatPattern + detectSSatPattern) - would it make sense to move them to SelectionDAG and reuse them here?

I will take a look.
I need some time to understand TableGen.

I didn't mean anything for TableGen - I just mention reusing the existing code (after moving to a generic location) instead of your IsSignedSaturate/IsUnsignedSaturate lambdas

.gitignore

 #OS X specific files.
 .DS_store
 
 # Ignore the user specified CMake presets in subproject directories.
 /*/CMakeUserPresets.json
 
 # Nested build directory
 /build*
+**/cmake-build*
 
 #==============================================================================#
 # Explicit files to ignore (only matches one).
 #==============================================================================#
 # Various tag programs
 /tags
 /TAGS
 /GPATH

llvm/lib/Target/ARM/ARMISelLowering.cpp

 //===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
     setTargetDAGCombine(ISD::ANY_EXTEND);
     setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
     setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
     setTargetDAGCombine(ISD::INTRINSIC_VOID);
     setTargetDAGCombine(ISD::VECREDUCE_ADD);
     setTargetDAGCombine(ISD::ADD);
     setTargetDAGCombine(ISD::BITCAST);
   }
+
+  if (Subtarget->hasNEON()) {
+    setTargetDAGCombine(ISD::TRUNCATE);
+  }
+
   if (Subtarget->hasMVEIntegerOps()) {
     setTargetDAGCombine(ISD::SMIN);
     setTargetDAGCombine(ISD::UMIN);
     setTargetDAGCombine(ISD::SMAX);
     setTargetDAGCombine(ISD::UMAX);
     setTargetDAGCombine(ISD::FP_EXTEND);
     setTargetDAGCombine(ISD::SELECT);
     setTargetDAGCombine(ISD::SELECT_CC);
static SDValue PerformFPExtendCombine(SDNode *N, SelectionDAG &DAG,
                                       const ARMSubtarget *ST) {
   if (ST->hasMVEFloatOps())
     if (SDValue NewLoad = PerformSplittingToWideningLoad(N, DAG))
       return NewLoad;
 
   return SDValue();
 }
 
-/// PerformMinMaxCombine - Target-specific DAG combining for creating truncating
+/// PerformNeonMinMaxCombine NEON DAG combining for creating truncating
+///// saturates.
+static SDValue PerformNeonTruncateMinMaxCombine(SDNode *N, SelectionDAG &DAG,
+                                                const ARMSubtarget *ST) {
+  EVT VT = N->getValueType(0);
+  SDValue N0 = N->getOperand(0);
+
+  if (!ST->hasNEON()) {
+    return SDValue();
+  }
+
+  if (VT != MVT::v8i8 && VT != MVT::v4i16)
+    return SDValue();
+
+  EVT VT0 = N0->getValueType(0);
+  if (!(VT == MVT::v8i8 && VT0 == MVT::v8i16) &&
+      !(VT == MVT::v4i16 && VT0 == MVT::v4i32)) {
+    return SDValue();
+  }
+
+  auto IsSignedSaturate = [&](SDNode *Min) {
+    auto *Max = N0->getOperand(0).getNode();
+
+    // Check one is a smin and the other is a smax
+    if (Min->getOpcode() != ISD::SMIN)
+      std::swap(Min, Max);
+    if (Min->getOpcode() != ISD::SMIN || Max->getOpcode() != ISD::SMAX)
+      return false;
+
+    APInt SaturateC;
+    if (VT == MVT::v8i8)
+      SaturateC = APInt(16, (1 << 7) - 1, true);
+    else // if (VT == MVT::v4i16)
+      SaturateC = APInt(32, (1 << 15) - 1, true);
+
+    APInt MinC, MaxC;
+    if (!ISD::isConstantSplatVector(Min->getOperand(1).getNode(), MinC) ||
+        MinC != SaturateC)
+      return false;
+    if (!ISD::isConstantSplatVector(Max->getOperand(1).getNode(), MaxC) ||
+        MaxC != ~SaturateC)
+      return false;
+    return true;
+  };
+
+  if (IsSignedSaturate(N0.getNode())) {
+    SDValue N00 = N0->getOperand(0);
+    //  t26: v8i8 = truncate t25
+    //    t25: v8i16 = smax t20, t22
+    //      t20: v8i16 = smin t62, t17
+    //  ----> vqmovn.s16 d0, q1
+
+    SDLoc DL(N);
+    return DAG.getNode(
+        ISD::INTRINSIC_WO_CHAIN, DL, VT,
+        DAG.getConstant(Intrinsic::arm_neon_vqmovns, DL, MVT::i32),
+        N00->getOperand(0));
+  }
+
+  auto IsUnsignedSaturate = [&](SDNode *Min) {
+    // For unsigned, we just need to check for <= 0xffff
+    if (Min->getOpcode() != ISD::UMIN)
+      return false;
+
+    APInt SaturateC;
+    if (VT == MVT::v8i8)
+      SaturateC = APInt(16, (1 << 8) - 1, true);
+    else // if (VT == MVT::v4i16)
+      SaturateC = APInt(32, (1 << 16) - 1, true);
+
+    APInt MinC;
+    if (!ISD::isConstantSplatVector(Min->getOperand(1).getNode(), MinC) ||
+        MinC != SaturateC)
+      return false;
+    return true;
+  };
+
+  if (IsUnsignedSaturate(N0.getNode())) {
+    //  t26: v8i8 = truncate t25
+    //      t20: v8i16 = umin t62, t17
+    //  ----> vqmovn.u16 d0, q1
+    SDLoc DL(N);
+    return DAG.getNode(
+        ISD::INTRINSIC_WO_CHAIN, DL, VT,
+        DAG.getConstant(Intrinsic::arm_neon_vqmovnu, DL, MVT::i32),
+        N0->getOperand(0));
+  }
+
+  return SDValue();
+}
+
+/// PerformMVEMinMaxCombine - MVE DAG combining for creating truncating
 /// saturates.
-static SDValue PerformMinMaxCombine(SDNode *N, SelectionDAG &DAG,
+static SDValue PerformMVEMinMaxCombine(SDNode *N, SelectionDAG &DAG,
                                        const ARMSubtarget *ST) {
   EVT VT = N->getValueType(0);
   SDValue N0 = N->getOperand(0);
   if (!ST->hasMVEIntegerOps())
     return SDValue();
 
   if (SDValue V = PerformVQDMULHCombine(N, DAG))
     return V;
 
SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
   case ISD::ANY_EXTEND:
     return PerformExtendCombine(N, DCI.DAG, Subtarget);
   case ISD::FP_EXTEND:
     return PerformFPExtendCombine(N, DCI.DAG, Subtarget);
   case ISD::SMIN:
   case ISD::UMIN:
   case ISD::SMAX:
   case ISD::UMAX:
-    return PerformMinMaxCombine(N, DCI.DAG, Subtarget);
+    return PerformMVEMinMaxCombine(N, DCI.DAG, Subtarget);
+  case ISD::TRUNCATE:
+    return PerformNeonTruncateMinMaxCombine(N, DCI.DAG, Subtarget);
   case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
   case ARMISD::BRCOND: return PerformBRCONDCombine(N, DCI.DAG);
   case ISD::LOAD:       return PerformLOADCombine(N, DCI);
   case ARMISD::VLD1DUP:
   case ARMISD::VLD2DUP:
   case ARMISD::VLD3DUP:
   case ARMISD::VLD4DUP:
     return PerformVLDCombine(N, DCI);

llvm/test/CodeGen/ARM/neon-truncate-min-max.ll

+; RUN: llc < %s -mtriple=armv7-none-linux-gnueabihf -mattr=+neon | FileCheck %s
+
+; test PerformNeonTruncateMinMaxCombine
+
+
+; Test truncate(smin(smax(a,b),c)) ---> vqmovns(a)
+
+
+; CHECK-LABEL: @t0
+; CHECK: vqmovn.s16 d{{[0-9]+}}, q{{[0-9]+}}
+; CHECK: bx lr
+define <8 x i8> @t0(<8 x i16> %in) {
+  %slt.i = icmp slt <8 x i16> %in, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
+  %min.i = select <8 x i1> %slt.i, <8 x i16> %in, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
+  %slt.j = icmp sgt <8 x i16> %min.i, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
+  %max.i = select <8 x i1> %slt.j, <8 x i16> %min.i, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
+  %trunc.i = trunc <8 x i16> %max.i to <8 x i8>
+  ret <8 x i8> %trunc.i
+}
+
+; CHECK-LABEL: @t1
+; CHECK: vqmovn.s32 d{{[0-9]+}}, q{{[0-9]+}}
+; CHECK: bx lr
+define <4 x i16> @t1(<4 x i32> %in) {
+  %slt.i = icmp slt <4 x i32> %in, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %min.i = select <4 x i1> %slt.i, <4 x i32> %in, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
+  %slt.j = icmp sgt <4 x i32> %min.i, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
+  %max.i = select <4 x i1> %slt.j, <4 x i32> %min.i, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
+  %trunc.i = trunc <4 x i32> %max.i to <4 x i16>
+  ret <4 x i16> %trunc.i
+}
+
+
+
+; Test truncate(umin(a,b)) ---> vqmovnu(a)
+
+; CHECK-LABEL: @t2
+; CHECK: vqmovn.u16 d{{[0-9]+}}, q{{[0-9]+}}
+; CHECK: bx lr
+define <8 x i8> @t2(<8 x i16> %in) {
+  %slt.i = icmp ult <8 x i16> %in, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  %min.i = select <8 x i1> %slt.i, <8 x i16> %in, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  %trunc.i = trunc <8 x i16> %min.i to <8 x i8>
+  ret <8 x i8> %trunc.i
+}
+
+
+; Test truncate(umin(a,b)) ---> vqmovnu(a)
+
+; CHECK-LABEL: @t3
+; CHECK: vqmovn.u32 d{{[0-9]+}}, q{{[0-9]+}}
+; CHECK: bx lr
+define <4 x i16> @t3(<4 x i32> %in) {
+  %slt.i = icmp ult <4 x i32> %in, <i32 65535, i32 65535, i32 65535, i32 65535>
+  %min.i = select <4 x i1> %slt.i, <4 x i32> %in, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
+  %trunc.i = trunc <4 x i32> %min.i to <4 x i16>
+  ret <4 x i16> %trunc.i
+}
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