[Thumb1][MachineOutliner] Add Machine Outliner support for Thumb1

[pestctrl]

Summary

MachineOutliner support was previously added for Thumb2 and ARM modes.
Thumb1 support was left out, because there is no simple way to push
the LR onto the stack and then restore it back into the LR. Such an
idiom is required when:

• A repeated sequence contains a call, which requires the LR to be saved and restored at the frame site.
• MachineOutlinerDefault, where the LR needs to be saved and restored at the call site.

Besides the two situations described above, Thumb1 machine outlining
should be able to reuse all of the code introduced for machine
outlining in Thumb2, since all instructions generated fall in the
Thumb1 subset.

This patch enables Thumb1 support for the outliner, and introduces an
idiom for saving and restoring the LR. The LR can only be saved and
restored if there is an unused register in a repeated sequence. If
this is the case, then the machine outliner can generate this sequence
of instructions to save the LR:

PUSH R4     ;; Free up an auxilary register
PUSH LR     ;; LR must go on the top of the stack

......      ;; Original sequence of instructions

POP R4      ;; Pop LR off the stack into R4
            ;; (Cannot be directly popped into LR)
MOV LR, R4  ;; Move LR into the correct register
POP R4      ;; Pop the original value of R4 into R4

[pestctrl]

Incorrect comment

[yroux]

Hi and Thanks for working on this,

I've a couple of embedded comments, and can you add some tests to check SP-relative loads and stores handling ?

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

6375

since there is not much logic in saveLROnsStack and restoreLRFromStack function what about removing them and creating the MIs here ?

llvm/lib/Target/ARM/Thumb1InstrInfo.cpp

360

why not adding FreeReg to MBB's LiveIns instead of spilling LR twice ?

llvm/test/CodeGen/ARM/machine-outliner-default.mir

167

I think that $r4 is not needed

[pestctrl]

Fixed issues with clang-format

[pestctrl]

Build MI's for save/restore LR in same function.

[pestctrl]

llvm/lib/Target/ARM/Thumb1InstrInfo.cpp

360

Huh, I had no idea you could do this. This might simplify my code a lot.

[pestctrl]

Add unused register to live-ins, instead of pushing the LR twice

[pestctrl]

@yroux Hey, sorry it's been a while. I've updated this commit to fix the issues you brought up regarding saving the LR twice, could you look at this again?

Thanks!

[pestctrl]

Ping

[efriedma]

tTAILJMPdND isn't generally available in Thumb mode, only in Thumb2 or armv8m.base.

PUSH R4     ;; Free up an auxilary register
PUSH LR     ;; LR must go on the top of the stack

......      ;; Original sequence of instructions

POP R4      ;; Pop LR off the stack into R4
            ;; (Cannot be directly popped into LR)
MOV LR, R4  ;; Move LR into the correct register
POP R4      ;; Pop the original value of R4 into R4

Can we instead do something like:

push lr
.... ; Original sequence
mov ip, r4
pop r4
mov lr, r4
mov r4, ip

llvm/lib/Target/ARM/Thumb1InstrInfo.cpp

257

BeforeSequence is unused here?

[pestctrl]

Oh, that's pretty neat! I would've never thought of that.

Wouldn't I still need to push 2 registers to the stack, to maintain stack alignment? Or could I just push one register?

[efriedma]

ARM ABI rules say the stack has to be aligned to 8 bytes at ABI boundaries, 4 bytes otherwise. So it might be an issue in some cases?

llvm/include/llvm/CodeGen/MachineOutliner.h

public:
 
   /// Contains the accumulated register liveness information for the
   /// instructions in this \p Candidate.
   ///
   /// This is optionally used by the target to determine which registers have
   /// been used across the sequence.
   LiveRegUnits UsedInSequence;
 
+  /// Contains the accumulated register liveness information for the
+  /// instructions before this \p Candidate.
+  ///
+  /// This is optionally used by the target to determine which registers have
+  /// been used before the sequence.
+  LiveRegUnits BeforeSequence;
+
   /// Target-specific flags for this Candidate's MBB.
   unsigned Flags = 0x0;
 
   /// True if initLRU has been called on this Candidate.
   bool LRUWasSet = false;
 
   /// Return the number of instructions in this Candidate.
   unsigned getLength() const { return Len; }
public:
   void setCallInfo(unsigned CID, unsigned CO) {
     CallConstructionID = CID;
     CallOverhead = CO;
   }
 
   /// Returns the call overhead of this candidate if it is in the list.
   unsigned getCallOverhead() const { return CallOverhead; }
 
-  MachineBasicBlock::iterator &front() { return FirstInst; }
-  MachineBasicBlock::iterator &back() { return LastInst; }
+  const MachineBasicBlock::iterator &front() const { return FirstInst; }
+  const MachineBasicBlock::iterator &back() const { return LastInst; }
   MachineFunction *getMF() const { return MBB->getParent(); }
   MachineBasicBlock *getMBB() const { return MBB; }
 
   /// The number of instructions that would be saved by outlining every
   /// candidate of this type.
   ///
   /// This is a fixed value which is not updated during the candidate pruning
   /// process. It is only used for deciding which candidate to keep if two
void initLRU(const TargetRegisterInfo &TRI) {
     std::for_each(MBB->rbegin(), (MachineBasicBlock::reverse_iterator)front(),
                   [this](MachineInstr &MI) { LRU.stepBackward(MI); });
 
     // Walk over the sequence itself and figure out which registers were used
     // in the sequence.
     UsedInSequence.init(TRI);
     std::for_each(front(), std::next(back()),
                   [this](MachineInstr &MI) { UsedInSequence.accumulate(MI); });
+
+    // Walk from the start of the machine basic block up until the start of the
+    // outlining candidate.
+    BeforeSequence.init(TRI);
+    BeforeSequence.addLiveIns(*MBB);
+    std::for_each(MBB->begin(), front(),
+                  [this](MachineInstr &MI) { BeforeSequence.accumulate(MI); });
   }
 };
 
 /// The information necessary to create an outlined function for some
 /// class of candidate.
 struct OutlinedFunction {
 
 public:

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

public:
   bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
 
   bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override {
     return MI->getOpcode() == ARM::t2LoopEndDec ||
            MI->getOpcode() == ARM::t2DoLoopStartTP ||
            MI->getOpcode() == ARM::t2WhileLoopStartLR;
   }
 
+protected:
+  /// Returns true if Target is able to save the LR to the stack, given a
+  /// MachineOutliner::Candidate as context. While this is always possible in
+  /// Subtargets that are ARM32 and Thumb2, Thumb1 has additional requirements
+  /// to be able to save the LR to the stack. The Thumb1InstrInfo will override
+  /// this function and provide more constraints.
+  virtual bool canSaveLRToStack(const outliner::Candidate &C) const {
+    return true;
+  }
+
+  /// Combine the saving and restoring of LR into one operation, as well as
+  /// emitting the CFI instructions. Thumb1 does this operation differently, so
+  /// this function will be overridden in Thumb1InstrInfo.
+
+  /// This function will take two iterators that indicate Front and Back of a
+  /// region, and emit a save to the front as well as a restore to the
+  /// back. Both iterators will be advanced forward, and the return value will
+  /// be an iterator pointing to the back of the save of the LR.
+  virtual MachineBasicBlock::iterator
+  saveAndRestoreLR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &Front,
+                   MachineBasicBlock::iterator &Back,
+                   const outliner::Candidate &C) const;
+
 private:
   /// Returns an unused general-purpose register which can be used for
   /// constructing an outlined call if one exists. Returns 0 otherwise.
   unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const;
 
-  // Adds an instruction which saves the link register on top of the stack into
+  /// Adds an instruction which saves the link register on top of the stack into
   /// the MachineBasicBlock \p MBB at position \p It.
   void saveLROnStack(MachineBasicBlock &MBB,
                      MachineBasicBlock::iterator It) const;
 
   /// Adds an instruction which restores the link register from the top the
   /// stack into the MachineBasicBlock \p MBB at position \p It.
   void restoreLRFromStack(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator It) const;

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

 ///
 /// That is,
 ///
 /// I1                                OUTLINED_FUNCTION:
 /// I2    --> B OUTLINED_FUNCTION     I1
 /// BX LR                             I2
 ///                                   BX LR
 ///
-/// +-------------------------+--------+-----+
-/// |                         | Thumb2 | ARM |
-/// +-------------------------+--------+-----+
-/// | Call overhead in Bytes  |      4 |   4 |
-/// | Frame overhead in Bytes |      0 |   0 |
-/// | Stack fixup required    |     No |  No |
-/// +-------------------------+--------+-----+
+/// +-------------------------+--------+--------+-----+
+/// |                         | Thumb1 | Thumb2 | ARM |
+/// +-------------------------+--------+--------+-----+
+/// | Call overhead in Bytes  |      4 |      4 |   4 |
+/// | Frame overhead in Bytes |      0 |      0 |   0 |
+/// | Stack fixup required    |     No |     No |  No |
+/// +-------------------------+--------+--------+-----+
 ///
 /// \p MachineOutlinerThunk implies that the function is being created from
 /// a sequence of instructions ending in a call. The outlined function is
 /// called with a BL instruction, and the outlined function tail-calls the
 /// original call destination.
 ///
 /// That is,
 ///
 /// I1                                OUTLINED_FUNCTION:
 /// I2   --> BL OUTLINED_FUNCTION     I1
 /// BL f                              I2
 ///                                   B f
 ///
-/// +-------------------------+--------+-----+
-/// |                         | Thumb2 | ARM |
-/// +-------------------------+--------+-----+
-/// | Call overhead in Bytes  |      4 |   4 |
-/// | Frame overhead in Bytes |      0 |   0 |
-/// | Stack fixup required    |     No |  No |
-/// +-------------------------+--------+-----+
+/// +-------------------------+--------+--------+-----+
+/// |                         | Thumb1 | Thumb2 | ARM |
+/// +-------------------------+--------+--------+-----+
+/// | Call overhead in Bytes  |      4 |      4 |   4 |
+/// | Frame overhead in Bytes |      0 |      0 |   0 |
+/// | Stack fixup required    |     No |     No |  No |
+/// +-------------------------+--------+--------+-----+
 ///
 /// \p MachineOutlinerNoLRSave implies that the function should be called using
 /// a BL instruction, but doesn't require LR to be saved and restored. This
 /// happens when LR is known to be dead.
 ///
 /// That is,
 ///
 /// I1                                OUTLINED_FUNCTION:
 /// I2 --> BL OUTLINED_FUNCTION       I1
 /// I3                                I2
 ///                                   I3
 ///                                   BX LR
 ///
-/// +-------------------------+--------+-----+
-/// |                         | Thumb2 | ARM |
-/// +-------------------------+--------+-----+
-/// | Call overhead in Bytes  |      4 |   4 |
-/// | Frame overhead in Bytes |      4 |   4 |
-/// | Stack fixup required    |     No |  No |
-/// +-------------------------+--------+-----+
+/// +-------------------------+--------+--------+-----+
+/// |                         | Thumb1 | Thumb2 | ARM |
+/// +-------------------------+--------+--------+-----+
+/// | Call overhead in Bytes  |      4 |      4 |   4 |
+/// | Frame overhead in Bytes |      4 |      4 |   4 |
+/// | Stack fixup required    |     No |     No |  No |
+/// +-------------------------+--------+--------+-----+
 ///
 /// \p MachineOutlinerRegSave implies that the function should be called with a
 /// save and restore of LR to an available register. This allows us to avoid
 /// stack fixups. Note that this outlining variant is compatible with the
 /// NoLRSave case.
 ///
 /// That is,
 ///
 /// I1     Save LR                    OUTLINED_FUNCTION:
 /// I2 --> BL OUTLINED_FUNCTION       I1
 /// I3     Restore LR                 I2
 ///                                   I3
 ///                                   BX LR
 ///
-/// +-------------------------+--------+-----+
-/// |                         | Thumb2 | ARM |
-/// +-------------------------+--------+-----+
-/// | Call overhead in Bytes  |      8 |  12 |
-/// | Frame overhead in Bytes |      2 |   4 |
-/// | Stack fixup required    |     No |  No |
-/// +-------------------------+--------+-----+
+/// +-------------------------+--------+--------+-----+
+/// |                         | Thumb1 | Thumb2 | ARM |
+/// +-------------------------+--------+--------+-----+
+/// | Call overhead in Bytes  |      8 |      8 |  12 |
+/// | Frame overhead in Bytes |      2 |      2 |   4 |
+/// | Stack fixup required    |     No |     No |  No |
+/// +-------------------------+--------+--------+-----+
 ///
 /// \p MachineOutlinerDefault implies that the function should be called with
 /// a save and restore of LR to the stack.
 ///
 /// That is,
 ///
 /// I1     Save LR                    OUTLINED_FUNCTION:
 /// I2 --> BL OUTLINED_FUNCTION       I1
 /// I3     Restore LR                 I2
 ///                                   I3
 ///                                   BX LR
 ///
-/// +-------------------------+--------+-----+
-/// |                         | Thumb2 | ARM |
-/// +-------------------------+--------+-----+
-/// | Call overhead in Bytes  |      8 |  12 |
-/// | Frame overhead in Bytes |      2 |   4 |
-/// | Stack fixup required    |    Yes | Yes |
-/// +-------------------------+--------+-----+
+/// +-------------------------+--------+--------+-----+
+/// |                         | Thumb1 | Thumb2 | ARM |
+/// +-------------------------+--------+--------+-----+
+/// | Call overhead in Bytes  |     14 |      8 |  12 |
+/// | Frame overhead in Bytes |      2 |      2 |   4 |
+/// | Stack fixup required    |    Yes |    Yes | Yes |
+/// +-------------------------+--------+--------+-----+
 
 enum MachineOutlinerClass {
   MachineOutlinerTailCall,
   MachineOutlinerThunk,
   MachineOutlinerNoLRSave,
   MachineOutlinerRegSave,
   MachineOutlinerDefault
 };
struct OutlinerCosts {
   const int CallNoLRSave;
   const int FrameNoLRSave;
   const int CallRegSave;
   const int FrameRegSave;
   const int CallDefault;
   const int FrameDefault;
   const int SaveRestoreLROnStack;
 
+  // This enum encodes the various costs of performing certain aspects of
+  // outlining. The cost of an outline is f + n * c + r, where:
+  //
+  // - f is the cost of the frame construction.
+  // - n is the number of repeated sequences, and c is the cost of a call.
+  //   (This is a simplification, as each repeated sequence can have a different
+  //   call cost)
+  // - r is the cost of an extra save and restore of the LR in the frame. This
+  //   is optional, if the frame doesn't require saving and restoring the LR.
+  //
+  // For more details, see ARMBaseInstrInfo::getOutliningCandidateInfo and
+  // llvm::outliner::Candidate.
   OutlinerCosts(const ARMSubtarget &target)
       : CallTailCall(target.isThumb() ? 4 : 4),
         FrameTailCall(target.isThumb() ? 0 : 0),
         CallThunk(target.isThumb() ? 4 : 4),
         FrameThunk(target.isThumb() ? 0 : 0),
         CallNoLRSave(target.isThumb() ? 4 : 4),
         FrameNoLRSave(target.isThumb() ? 4 : 4),
         CallRegSave(target.isThumb() ? 8 : 12),
         FrameRegSave(target.isThumb() ? 2 : 4),
-        CallDefault(target.isThumb() ? 8 : 12),
+        CallDefault(target.isThumb1Only() ? 14 : (target.isThumb() ? 8 : 12)),
         FrameDefault(target.isThumb() ? 2 : 4),
-        SaveRestoreLROnStack(target.isThumb() ? 8 : 8) {}
+        SaveRestoreLROnStack(
+            target.isThumb1Only() ? 10 : (target.isThumb() ? 8 : 8)) {}
 };
 
 unsigned
 ARMBaseInstrInfo::findRegisterToSaveLRTo(const outliner::Candidate &C) const {
   assert(C.LRUWasSet && "LRU wasn't set?");
   MachineFunction *MF = C.getMF();
   const ARMBaseRegisterInfo *ARI = static_cast<const ARMBaseRegisterInfo *>(
       MF->getSubtarget().getRegisterInfo());
if (RepeatedSequenceLocs[0].back()->isTerminator()) {
     // have to update the stack. Otherwise, give every candidate the default
     // call type
     if (NumBytesNoStackCalls <=
         RepeatedSequenceLocs.size() * Costs.CallDefault) {
       RepeatedSequenceLocs = CandidatesWithoutStackFixups;
       FrameID = MachineOutlinerNoLRSave;
     } else
       SetCandidateCallInfo(MachineOutlinerDefault, Costs.CallDefault);
+
+    // Thumb1 requires an extra register in order to restore the LR from the
+    // stack for MachineOutlinerDefault. This register needs to be liveout of
+    // the repeated sequence. It can be live, but must be unused in the
+    // repeated sequence. If we cannot find such a register, then all
+    // MachineOutlinerDefault candidates cannot be outlined.
+    if (Subtarget.isThumb1Only() && !canSaveLRToStack(FirstCand)) {
+      llvm::erase_if(RepeatedSequenceLocs, [](outliner::Candidate &C) {
+        return C.CallConstructionID == MachineOutlinerDefault;
+      });
+    }
   }
 
   // Does every candidate's MBB contain a call?  If so, then we might have a
   // call in the range.
   if (FlagsSetInAll & MachineOutlinerMBBFlags::HasCalls) {
+    bool SaveLRRequired = false;
     // check if the range contains a call.  These require a save + restore of
     // the link register.
     if (std::any_of(FirstCand.front(), FirstCand.back(),
                     [](const MachineInstr &MI) { return MI.isCall(); }))
-      NumBytesToCreateFrame += Costs.SaveRestoreLROnStack;
+      SaveLRRequired = true;
 
     // Handle the last instruction separately.  If it is tail call, then the
     // last instruction is a call, we don't want to save + restore in this
     // case.  However, it could be possible that the last instruction is a
     // call without it being valid to tail call this sequence.  We should
     // consider this as well.
     else if (FrameID != MachineOutlinerThunk &&
              FrameID != MachineOutlinerTailCall && FirstCand.back()->isCall())
+      SaveLRRequired = true;
+
+    if (SaveLRRequired) {
+      if (Subtarget.isThumb1Only() && !canSaveLRToStack(FirstCand)) {
+        return outliner::OutlinedFunction();
+      }
+
       NumBytesToCreateFrame += Costs.SaveRestoreLROnStack;
     }
+  }
 
   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
                                     NumBytesToCreateFrame, FrameID);
 }
 
 bool ARMBaseInstrInfo::checkAndUpdateStackOffset(MachineInstr *MI,
                                                  int64_t Fixup,
                                                  bool Updt) const {
bool ARMBaseInstrInfo::isFunctionSafeToOutlineFrom(
 
   // Don't outline from functions with section markings; the program could
   // expect that all the code is in the named section.
   // FIXME: Allow outlining from multiple functions with the same section
   // marking.
   if (F.hasSection())
     return false;
 
-  // FIXME: Thumb1 outlining is not handled
-  if (MF.getInfo<ARMFunctionInfo>()->isThumb1OnlyFunction())
-    return false;
-
   // It's safe to outline from MF.
   return true;
 }
 
 bool ARMBaseInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
                                               unsigned &Flags) const {
   // Check if LR is available through all of the MBB. If it's not, then set
   // a flag.
ARMBaseInstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,
   }
 
   // Don't outline if link register or program counter value are used.
   if (MI.readsRegister(ARM::LR, TRI) || MI.readsRegister(ARM::PC, TRI))
     return outliner::InstrType::Illegal;
 
   if (MI.isCall()) {
     // Get the function associated with the call.  Look at each operand and find
-    // the one that represents the calle and get its name.
+    // the one that represents the callee and get its name.
     const Function *Callee = nullptr;
     for (const MachineOperand &MOP : MI.operands()) {
       if (MOP.isGlobal()) {
         Callee = dyn_cast<Function>(MOP.getGlobal());
         break;
       }
     }
 

 }
 
 void ARMBaseInstrInfo::fixupPostOutline(MachineBasicBlock &MBB) const {
   for (MachineInstr &MI : MBB) {
     checkAndUpdateStackOffset(&MI, Subtarget.getStackAlignment().value(), true);
   }
 }
 
-void ARMBaseInstrInfo::saveLROnStack(MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator It) const {
-  unsigned Opc = Subtarget.isThumb() ? ARM::t2STR_PRE : ARM::STR_PRE_IMM;
-  int Align = -Subtarget.getStackAlignment().value();
-  BuildMI(MBB, It, DebugLoc(), get(Opc), ARM::SP)
-    .addReg(ARM::LR, RegState::Kill)
-    .addReg(ARM::SP)
-    .addImm(Align)
-    .add(predOps(ARMCC::AL));
-}
-
 void ARMBaseInstrInfo::emitCFIForLRSaveOnStack(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator It) const {
   MachineFunction &MF = *MBB.getParent();
   const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
   unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
   int Align = Subtarget.getStackAlignment().value();
   // Add a CFI saying the stack was moved down.
   int64_t StackPosEntry =
void ARMBaseInstrInfo::emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
 
   int64_t LRPosEntry = MF.addFrameInst(
       MCCFIInstruction::createRegister(nullptr, DwarfLR, DwarfReg));
   BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
       .addCFIIndex(LRPosEntry)
       .setMIFlags(MachineInstr::FrameSetup);
 }
 
-void ARMBaseInstrInfo::restoreLRFromStack(
-    MachineBasicBlock &MBB, MachineBasicBlock::iterator It) const {
-  unsigned Opc = Subtarget.isThumb() ? ARM::t2LDR_POST : ARM::LDR_POST_IMM;
-  MachineInstrBuilder MIB = BuildMI(MBB, It, DebugLoc(), get(Opc), ARM::LR)
-    .addReg(ARM::SP, RegState::Define)
-    .addReg(ARM::SP);
-  if (!Subtarget.isThumb())
-    MIB.addReg(0);
-  MIB.addImm(Subtarget.getStackAlignment().value()).add(predOps(ARMCC::AL));
-}
-
 void ARMBaseInstrInfo::emitCFIForLRRestoreFromStack(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator It) const {
   // Now stack has moved back up...
   MachineFunction &MF = *MBB.getParent();
   const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
   unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
   int64_t StackPosEntry =
       MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
void ARMBaseInstrInfo::emitCFIForLRRestoreFromReg(
 
   int64_t LRPosEntry =
       MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, DwarfLR));
   BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
       .addCFIIndex(LRPosEntry)
       .setMIFlags(MachineInstr::FrameDestroy);
 }
 
+MachineBasicBlock::iterator ARMBaseInstrInfo::saveAndRestoreLR(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator &Front,
+    MachineBasicBlock::iterator &Back, const outliner::Candidate &C) const {
+  const ARMFunctionInfo &AFI = *MBB.getParent()->getInfo<ARMFunctionInfo>();
+  unsigned saveOpc = Subtarget.isThumb() ? ARM::t2STR_PRE : ARM::STR_PRE_IMM;
+  unsigned restoreOpc =
+      Subtarget.isThumb() ? ARM::t2LDR_POST : ARM::LDR_POST_IMM;
+  int Align = Subtarget.getStackAlignment().value();
+
+  // Insert a save before the outlined region
+  BuildMI(MBB, Front, DebugLoc(), get(saveOpc), ARM::SP)
+      .addReg(ARM::LR, RegState::Kill)
+      .addReg(ARM::SP)
+      .addImm(-Align)
+      .add(predOps(ARMCC::AL));
+
+  if (!AFI.isLRSpilled())
+    emitCFIForLRSaveOnStack(MBB, Front);
+
+  // Create a copy of the Front iterator where it is now. Advance it backwards,
+  // so it does not progress, in the case where Front == Back.
+  MachineBasicBlock::iterator AfterLRSave = Front;
+  AfterLRSave--;
+
+  // Insert a restore before the terminator for the function. Restore LR.
+  MachineInstrBuilder MIB =
+      BuildMI(MBB, Back, DebugLoc(), get(restoreOpc), ARM::LR)
+          .addReg(ARM::SP, RegState::Define)
+          .addReg(ARM::SP);
+  if (!Subtarget.isThumb())
+    MIB.addReg(0);
+  MIB.addImm(Align).add(predOps(ARMCC::AL));
+
+  if (!AFI.isLRSpilled())
+    emitCFIForLRRestoreFromStack(MBB, Back);
+
+  // Move this iterator forward one, to where Front used to be, in case Front
+  // has also changed.
+  AfterLRSave++;
+  return AfterLRSave;
+}
+
 void ARMBaseInstrInfo::buildOutlinedFrame(
     MachineBasicBlock &MBB, MachineFunction &MF,
     const outliner::OutlinedFunction &OF) const {
   // For thunk outlining, rewrite the last instruction from a call to a
   // tail-call.
   if (OF.FrameConstructionID == MachineOutlinerThunk) {
     MachineInstr *Call = &*--MBB.instr_end();
     bool isThumb = Subtarget.isThumb();
if (OF.FrameConstructionID == MachineOutlinerTailCall ||
       Et = std::prev(MBB.end());
 
     // We have to save and restore LR, we need to add it to the liveins if it
     // is not already part of the set.  This is suffient since outlined
     // functions only have one block.
     if (!MBB.isLiveIn(ARM::LR))
       MBB.addLiveIn(ARM::LR);
 
-    // Insert a save before the outlined region
-    saveLROnStack(MBB, It);
-    emitCFIForLRSaveOnStack(MBB, It);
-
     // Fix up the instructions in the range, since we're going to modify the
     // stack.
     assert(OF.FrameConstructionID != MachineOutlinerDefault &&
            "Can only fix up stack references once");
     fixupPostOutline(MBB);
 
-    // Insert a restore before the terminator for the function.  Restore LR.
-    restoreLRFromStack(MBB, Et);
-    emitCFIForLRRestoreFromStack(MBB, Et);
+    // Insert a save of the LR before the outlined region, and restore it
+    // before the terminator for the function.
+    saveAndRestoreLR(MBB, It, Et, OF.Candidates[0]);
   }
 
   // If this is a tail call outlined function, then there's already a return.
   if (OF.FrameConstructionID == MachineOutlinerTailCall ||
       OF.FrameConstructionID == MachineOutlinerThunk)
     return;
 
   // Here we have to insert the return ourselves.  Get the correct opcode from
if (!AFI.isLRSpilled())
       emitCFIForLRSaveToReg(MBB, It, Reg);
     CallPt = MBB.insert(It, CallMIB);
     copyPhysReg(MBB, It, DebugLoc(), ARM::LR, Reg, true);
     if (!AFI.isLRSpilled())
       emitCFIForLRRestoreFromReg(MBB, It);
     It--;
     return CallPt;
   }
-  // We have the default case. Save and restore from SP.
+
+  // Save and restore the LR from the stack
   if (!MBB.isLiveIn(ARM::LR))
     MBB.addLiveIn(ARM::LR);
-  saveLROnStack(MBB, It);
-  if (!AFI.isLRSpilled())
-    emitCFIForLRSaveOnStack(MBB, It);
-  CallPt = MBB.insert(It, CallMIB);
-  restoreLRFromStack(MBB, It);
-  if (!AFI.isLRSpilled())
-    emitCFIForLRRestoreFromStack(MBB, It);
+
+  MachineBasicBlock::iterator AfterLRSave = saveAndRestoreLR(MBB, It, It, C);
+
+  // Insert the call right after the save, but before the restore
+  CallPt = MBB.insert(AfterLRSave, CallMIB);
+
+  // Move the pointer backwards, so the correct instructions get deleted from
+  // the basic block.
   It--;
+
   return CallPt;
 }
 
 bool ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault(
     MachineFunction &MF) const {
   return Subtarget.isMClass() && MF.getFunction().hasMinSize();
 }
 
unsigned llvm::gettBLXrOpcode(const MachineFunction &MF) {
   return (MF.getSubtarget<ARMSubtarget>().hardenSlsBlr()) ? ARM::tBLXr_noip
                                                           : ARM::tBLXr;
 }
 
 unsigned llvm::getBLXpredOpcode(const MachineFunction &MF) {
   return (MF.getSubtarget<ARMSubtarget>().hardenSlsBlr()) ? ARM::BLX_pred_noip
                                                           : ARM::BLX_pred;
 }
-

llvm/lib/Target/ARM/Thumb1InstrInfo.h

public:
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
                             Register DestReg, int FrameIndex,
                             const TargetRegisterClass *RC,
                             const TargetRegisterInfo *TRI) const override;
 
   bool canCopyGluedNodeDuringSchedule(SDNode *N) const override;
+
+protected:
+  MachineBasicBlock::iterator
+  saveAndRestoreLR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &Front,
+                   MachineBasicBlock::iterator &Back,
+                   const outliner::Candidate &C) const override;
+
+  /// For Thumb1, we can only save to the stack if there's an unused register
+  /// in the repeated sequence for outlining candidate \p C.
+  bool canSaveLRToStack(const outliner::Candidate &C) const override {
+    return findUnusedLowRegister(C).id() != 0u;
+  }
+
+private:
+  /// Returns an unused general-purpose register which can be used for
+  /// saving the LR to the stack, if one exists. Returns 0 otherwise.
+  Register findUnusedLowRegister(const outliner::Candidate &C) const;
+  Register findUnusedLowRegister(MachineFunction *MF,
+                                 LiveRegUnits UsedInSequence,
+                                 LiveRegUnits BeforeSequence) const;
+
+  /// Push the LR and an auxiliary register onto the stack, making sure the LR
+  /// is at the top of the stack.
+  void saveLRAndRegOnStack(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator &It, Register Reg) const;
+
+  /// Emit CFI instructions for the above operation, to detail where on the
+  /// stack the LR and the auxiliary register are stored.
+  void emitCFIForLRAndRegSaveOnStack(MachineBasicBlock &MBB,
+                                     MachineBasicBlock::iterator It,
+                                     Register Reg) const;
+
+  // Pop the LR off the stack, and move it into the appropriate place. Then,
+  // restore the value of the auxiliary register.
+  void restoreLRAndRegFromStack(MachineBasicBlock &MBB,
+                                MachineBasicBlock::iterator &It,
+                                Register Reg) const;
+
+  // Emit CFI instructions for freeing up stack space and restoring the LR and
+  // the auxiliary register.
+  void emitCFIForLRAndRegRestoreFromStack(MachineBasicBlock &MBB,
+                                          MachineBasicBlock::iterator It,
+                                          Register Reg) const;
+
 private:
   void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
 };
 }
 
 #endif

llvm/lib/Target/ARM/Thumb1InstrInfo.cpp

 //===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "Thumb1InstrInfo.h"
+#include "ARMMachineFunctionInfo.h"
 #include "ARMSubtarget.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstBuilder.h"
 
 using namespace llvm;
 
 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
     : ARMBaseInstrInfo(STI), RI() {}
 
bool Thumb1InstrInfo::canCopyGluedNodeDuringSchedule(SDNode *N) const {
   // FIXME. Actually implement the cross-copy where it is possible (post v6)
   // because these copies entail more spilling.
   unsigned Opcode = N->getMachineOpcode();
   if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)
     return true;
 
   return false;
 }
+
+void Thumb1InstrInfo::saveLRAndRegOnStack(MachineBasicBlock &MBB,
+                                          MachineBasicBlock::iterator &It,
+                                          Register Reg) const {
+  // Free up an unused register
+  BuildMI(MBB, It, DebugLoc(), get(ARM::tPUSH))
+      .add(predOps(ARMCC::AL))
+      .addReg(Reg);
+
+  // Ensure that the LR is pushed on top of the previously free register, by
+  // pushing it in a separate instruction.
+  BuildMI(MBB, It, DebugLoc(), get(ARM::tPUSH))
+      .add(predOps(ARMCC::AL))
+      .addReg(ARM::LR);
+}
+
+void Thumb1InstrInfo::emitCFIForLRAndRegSaveOnStack(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator It,
+    Register Reg) const {
+  MachineFunction &MF = *MBB.getParent();
+  const MCRegisterInfo *MRI = getSubtarget().getRegisterInfo();
+  int BytesPerReg = 4;
+
+  // Add a CFI saying the stack was moved down.
+  int64_t StackPosEntry = MF.addFrameInst(
+      MCCFIInstruction::cfiDefCfaOffset(nullptr, BytesPerReg * 2));
+  BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
+      .addCFIIndex(StackPosEntry)
+      .setMIFlags(MachineInstr::FrameSetup);
+
+  // Add a CFI saying that the LR that we want to find is now higher than
+  // before.
+  unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
+  int64_t LRPosEntry = MF.addFrameInst(
+      MCCFIInstruction::createOffset(nullptr, DwarfLR, BytesPerReg * -2));
+  BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
+      .addCFIIndex(LRPosEntry)
+      .setMIFlags(MachineInstr::FrameSetup);
+
+  // Emit CFI information about the unused register that was pushed to
+  // the stack.
+  unsigned SavedReg = MRI->getDwarfRegNum(Reg, true);
+  int64_t SavedRegPosEntry = MF.addFrameInst(
+      MCCFIInstruction::createOffset(nullptr, SavedReg, BytesPerReg * -1));
+  BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
+      .addCFIIndex(SavedRegPosEntry)
+      .setMIFlags(MachineInstr::FrameSetup);
+}
+
+void Thumb1InstrInfo::restoreLRAndRegFromStack(MachineBasicBlock &MBB,
+                                               MachineBasicBlock::iterator &It,
+                                               Register Reg) const {
+  // The LR should be on the top of the stack, so we pop it off into the freed
+  // register.
+  BuildMI(MBB, It, DebugLoc(), get(ARM::tPOP))
+      .add(predOps(ARMCC::AL))
+      .addReg(Reg, RegState::Define);
+
+  // Move the LR into the appropriate location.
+  copyPhysReg(MBB, It, DebugLoc(), ARM::LR, Reg, true);
+
+  // Pop the original value of the freed register.
+  BuildMI(MBB, It, DebugLoc(), get(ARM::tPOP))
+      .add(predOps(ARMCC::AL))
+      .addReg(Reg, RegState::Define);
+}
+
+void Thumb1InstrInfo::emitCFIForLRAndRegRestoreFromStack(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator It,
+    Register Reg) const {
+  // Now stack has moved back up...
+  MachineFunction &MF = *MBB.getParent();
+  const MCRegisterInfo *MRI = getSubtarget().getRegisterInfo();
+
+  int64_t StackPosEntry =
+      MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
+  BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
+      .addCFIIndex(StackPosEntry)
+      .setMIFlags(MachineInstr::FrameDestroy);
+
+  // ... and we have restored LR.
+  unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
+  int64_t LRPosEntry =
+      MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, DwarfLR));
+  BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
+      .addCFIIndex(LRPosEntry)
+      .setMIFlags(MachineInstr::FrameDestroy);
+
+  // ... and we have restored the freed register.
+  unsigned SavedReg = MRI->getDwarfRegNum(Reg, true);
+  int64_t SavedRegPosEntry =
+      MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, SavedReg));
+  BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
+      .addCFIIndex(SavedRegPosEntry)
+      .setMIFlags(MachineInstr::FrameDestroy);
+}
+
+Register Thumb1InstrInfo::findUnusedLowRegister(MachineFunction *MF,
+                                                LiveRegUnits UsedInSequence,
+                                                LiveRegUnits BeforeSequence) const {
+  const ARMBaseRegisterInfo *ARI = static_cast<const ARMBaseRegisterInfo *>(
+      MF->getSubtarget().getRegisterInfo());
+
+  BitVector regsReserved = ARI->getReservedRegs(*MF);
+
+  // Check if there is an available register across the sequence that we can
+  // use.
+  Register DeadReg = 0u;
+
+  for (Register Reg : ARM::rGPRRegClass) {
+    if (!(Reg < regsReserved.size() && regsReserved.test(Reg)) &&
+        Reg != ARM::LR &&        // LR is not reserved, but don't use it.
+        Reg != ARM::R12 &&       // R12 is not guaranteed to be preserved.
+        isARMLowRegister(Reg) && // Pop's destination register must be Lo
+        UsedInSequence.available(Reg)) {
+      return Reg;
+    }
+  }
+
+  // No unused register found
+  return 0u;
+}
+
+Register Thumb1InstrInfo::findUnusedLowRegister(const outliner::Candidate &C) const {
+  assert(C.LRUWasSet &&
+         "Outlining Candidate LRU information wasn't initialized.");
+  return findUnusedLowRegister(C.getMF(), C.UsedInSequence, C.BeforeSequence);
+}
+
+/// Thumb1 will need to save and restore the LR differently than Thumb2 and
+/// ARM32. The additional requirements are extracted from an outlining
+/// candidate, as well as a region of instructions specified by \p Front and \p
+/// Back. Requirements for saving and restoring the LR are that the region of
+/// instructions must have an unused register. If there exists such a register,
+/// say R4, then to save and restore the LR, we do the following:
+
+/// PUSH R4     ;; Free up an auxilary register
+/// PUSH LR     ;; LR must go on the top of the stack
+
+/// ......      ;; Original sequence of instructions
+
+/// POP R4      ;; Pop LR off the stack into R4
+///             ;; (Cannot be directly popped into LR)
+/// MOV LR, R4  ;; Move LR into the correct register
+/// POP R4      ;; Pop the original value of R4 into R4
+MachineBasicBlock::iterator Thumb1InstrInfo::saveAndRestoreLR(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator &Front,
+    MachineBasicBlock::iterator &Back, const outliner::Candidate &C) const {
+  const ARMFunctionInfo &AFI = *MBB.getParent()->getInfo<ARMFunctionInfo>();
+
+  // Find a register that has no uses in the repeated sequence
+  Register FreeReg = 0u;
+
+  // If we're inserting a call into an outlining candidate, a lot of liveness
+  // information has already been computed. Just pass the candidate.
+  if (C.front() == Front)
+    FreeReg = findUnusedLowRegister(C);
+  else {
+    // Saving the LR in an outlining frame needs a recomputed BeforeSequence
+    // LRU. The UsedInSequence can be reused.
+    LiveRegUnits BeforeSequence;
+    BeforeSequence.init(*getSubtarget().getRegisterInfo());
+    BeforeSequence.addLiveIns(MBB);
+    std::for_each(MBB.begin(), Front, [&BeforeSequence](MachineInstr &MI) {
+      BeforeSequence.accumulate(MI);
+    });
+
+    FreeReg = findUnusedLowRegister(MBB.getParent(), C.UsedInSequence,
+                                    BeforeSequence);
+  }
+
+  assert(FreeReg != 0u && "No callee-saved register available?");
+
+  // Add FreeReg as a live-in so that LLVM doesn't complain about
+  // undef'd values being pushed to the stack. Garbage values are
+  // pushed only for stack alignment.
+  if(!MBB.isLiveIn(FreeReg))
+    MBB.addLiveIn(FreeReg);
+
+  // Save the LR and an additional register.
+  saveLRAndRegOnStack(MBB, Front, FreeReg);
+  if (!AFI.isLRSpilled())
+    emitCFIForLRAndRegSaveOnStack(MBB, Front, FreeReg);
+
+  // Keep a copy of the front, and progress it backwards, in case Front ==
+  // Back.
+  MachineBasicBlock::iterator AfterLRSave = Front;
+  AfterLRSave--;
+
+  // Restore the LR and the additional register.
+  restoreLRAndRegFromStack(MBB, Back, FreeReg);
+  if (!AFI.isLRSpilled())
+    emitCFIForLRAndRegRestoreFromStack(MBB, Back, FreeReg);
+
+  // Move this forward, back to where Front used to be, or still is.
+  AfterLRSave++;
+  return AfterLRSave;
+}

llvm/test/CodeGen/ARM/machine-outliner-default.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=arm-- -run-pass=machine-outliner -verify-machineinstrs \
 # RUN: %s -o - | FileCheck %s
 
 --- |
   define void @outline_default_arm() #0 { ret void }
-  define void @outline_default_thumb() #1 { ret void }
+  define void @outline_default_thumb2() #1 { ret void }
+  define void @outline_default_thumb1() #2 { ret void }
+  define void @outline_default_no_low_registers_thumb1() #2 { ret void }
   declare void @bar()
 
   attributes #0 = { minsize optsize }
   attributes #1 = { minsize optsize "target-features"="+armv7-a,+thumb-mode" }
+  attributes #2 = { minsize optsize "target-features"="+armv6-m,+thumb-mode" }
 ...
 ---
 
 name:           outline_default_arm
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: outline_default_arm
   ; CHECK: bb.0:
bb.2:
     $r5 = MOVi 1, 14, $noreg, $noreg
   bb.3:
     liveins: $lr, $r6, $r7, $r8, $r9, $r10, $r11
     $r2 = MOVr $lr, 14, $noreg, $noreg
     BX_RET 14, $noreg
 ...
 ---
 
-name:           outline_default_thumb
+name:           outline_default_thumb2
 tracksRegLiveness: true
 body:             |
-  ; CHECK-LABEL: name: outline_default_thumb
+  ; CHECK-LABEL: name: outline_default_thumb2
   ; CHECK: bb.0:
   ; CHECK:   liveins: $lr
   ; CHECK:   early-clobber $sp = t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg
   ; CHECK:   tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_1
   ; CHECK:   $lr, $sp = t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg
   ; CHECK: bb.1:
   ; CHECK:   liveins: $lr, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
   ; CHECK:   early-clobber $sp = t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg
bb.2:
     $r0 = t2MOVi 1, 14, $noreg, $noreg
     $r1 = t2MOVi 1, 14, $noreg, $noreg
     $r2 = t2MOVi 1, 14, $noreg, $noreg
     $r3 = t2MOVi 1, 14, $noreg, $noreg
   bb.3:
     liveins: $lr, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
     $r2 = tMOVr $lr, 14, $noreg
     tBX_RET 14, $noreg
+...
+---
+
+name:           outline_default_thumb1
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: outline_default_thumb1
+  ; CHECK: bb.0:
+  ; CHECK:   liveins: $lr
+  ; CHECK:   tPUSH 14 /* CC::al */, $noreg, $r5, implicit-def $sp, implicit $sp
+  ; CHECK:   tPUSH 14 /* CC::al */, $noreg, $lr, implicit-def $sp, implicit $sp
+  ; CHECK:   tBL   14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_2
+  ; CHECK:   tPOP  14 /* CC::al */, $noreg, def $r5, implicit-def $sp, implicit $sp
+  ; CHECK:   $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg
+  ; CHECK:   tPOP  14 /* CC::al */, $noreg, def $r5, implicit-def $sp, implicit $sp
+  ; CHECK: bb.1:
+  ; CHECK:   liveins: $lr, $r0, $r1, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
+  ; CHECK:   tPUSH 14 /* CC::al */, $noreg, $r5, implicit-def $sp, implicit $sp
+  ; CHECK:   tPUSH 14 /* CC::al */, $noreg, $lr, implicit-def $sp, implicit $sp
+  ; CHECK:   tBL   14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_2
+  ; CHECK:   tPOP  14 /* CC::al */, $noreg, def $r5, implicit-def $sp, implicit $sp
+  ; CHECK:   $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg
+  ; CHECK:   tPOP  14 /* CC::al */, $noreg, def $r5, implicit-def $sp, implicit $sp
+  ; CHECK: bb.2:
+  ; CHECK:   liveins: $lr, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
+  ; CHECK:   tPUSH 14 /* CC::al */, $noreg, $r5, implicit-def $sp, implicit $sp
+  ; CHECK:   tPUSH 14 /* CC::al */, $noreg, $lr, implicit-def $sp, implicit $sp
+  ; CHECK:   tBL   14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_2
+  ; CHECK:   tPOP  14 /* CC::al */, $noreg, def $r5, implicit-def $sp, implicit $sp
+  ; CHECK:   $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg
+  ; CHECK:   tPOP  14 /* CC::al */, $noreg, def $r5, implicit-def $sp, implicit $sp
+  ; CHECK: bb.3:
+  ; CHECK:   liveins: $lr, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
+  ; CHECK:   $r2 = tMOVr $lr, 14 /* CC::al */, $noreg
+  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg
+  bb.0:
+    liveins: $lr
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r0, $cpsr = tMOVi8 2, 14, $noreg
+    $r1, $cpsr = tMOVi8 3, 14, $noreg
+    $r1, $cpsr = tMOVi8 4, 14, $noreg
+    $r2, $cpsr = tMOVi8 5, 14, $noreg
+    $r2, $cpsr = tMOVi8 6, 14, $noreg
+    $r3, $cpsr = tMOVi8 7, 14, $noreg
+    $r3, $cpsr = tMOVi8 8, 14, $noreg
+    $r4, $cpsr = tMOVi8 9, 14, $noreg
+    $r4, $cpsr = tMOVi8 10, 14, $noreg
+    $r0, $cpsr = tMOVi8 11, 14, $noreg
+    $r0, $cpsr = tMOVi8 12, 14, $noreg
+  bb.1:
+    liveins: $lr, $r0, $r1, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r0, $cpsr = tMOVi8 2, 14, $noreg
+    $r1, $cpsr = tMOVi8 3, 14, $noreg
+    $r1, $cpsr = tMOVi8 4, 14, $noreg
+    $r2, $cpsr = tMOVi8 5, 14, $noreg
+    $r2, $cpsr = tMOVi8 6, 14, $noreg
+    $r3, $cpsr = tMOVi8 7, 14, $noreg
+    $r3, $cpsr = tMOVi8 8, 14, $noreg
+    $r4, $cpsr = tMOVi8 9, 14, $noreg
+    $r4, $cpsr = tMOVi8 10, 14, $noreg
+    $r0, $cpsr = tMOVi8 11, 14, $noreg
+    $r0, $cpsr = tMOVi8 12, 14, $noreg
+  bb.2:
+    liveins: $lr, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r0, $cpsr = tMOVi8 2, 14, $noreg
+    $r1, $cpsr = tMOVi8 3, 14, $noreg
+    $r1, $cpsr = tMOVi8 4, 14, $noreg
+    $r2, $cpsr = tMOVi8 5, 14, $noreg
+    $r2, $cpsr = tMOVi8 6, 14, $noreg
+    $r3, $cpsr = tMOVi8 7, 14, $noreg
+    $r3, $cpsr = tMOVi8 8, 14, $noreg
+    $r4, $cpsr = tMOVi8 9, 14, $noreg
+    $r4, $cpsr = tMOVi8 10, 14, $noreg
+    $r0, $cpsr = tMOVi8 11, 14, $noreg
+    $r0, $cpsr = tMOVi8 12, 14, $noreg
+  bb.3:
+    liveins: $lr, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
+    $r2 = tMOVr $lr, 14, $noreg
+    tBX_RET 14, $noreg
+...
+---
+
+name:           outline_default_no_low_registers_thumb1
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: outline_default_no_low_registers_thumb1
+  ; CHECK: bb.0:
+  ; CHECK:   liveins: $lr
+  ; CHECK:   $r0, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   $r1, $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
+  ; CHECK:   $r2, $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
+  ; CHECK:   $r3, $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
+  ; CHECK:   $r4, $cpsr = tMOVi8 5, 14 /* CC::al */, $noreg
+  ; CHECK:   $r5, $cpsr = tMOVi8 6, 14 /* CC::al */, $noreg
+  ; CHECK:   $r6, $cpsr = tMOVi8 7, 14 /* CC::al */, $noreg
+  ; CHECK:   $r7, $cpsr = tMOVi8 8, 14 /* CC::al */, $noreg
+  ; CHECK:   $r0, $cpsr = tMOVi8 9, 14 /* CC::al */, $noreg
+  ; CHECK:   $r1, $cpsr = tMOVi8 10, 14 /* CC::al */, $noreg
+  ; CHECK: bb.1:
+  ; CHECK:   liveins: $lr, $r8, $r9, $r10, $r11
+  ; CHECK:   $r0, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   $r1, $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
+  ; CHECK:   $r2, $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
+  ; CHECK:   $r3, $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
+  ; CHECK:   $r4, $cpsr = tMOVi8 5, 14 /* CC::al */, $noreg
+  ; CHECK:   $r5, $cpsr = tMOVi8 6, 14 /* CC::al */, $noreg
+  ; CHECK:   $r6, $cpsr = tMOVi8 7, 14 /* CC::al */, $noreg
+  ; CHECK:   $r7, $cpsr = tMOVi8 8, 14 /* CC::al */, $noreg
+  ; CHECK:   $r0, $cpsr = tMOVi8 9, 14 /* CC::al */, $noreg
+  ; CHECK:   $r1, $cpsr = tMOVi8 10, 14 /* CC::al */, $noreg
+  ; CHECK: bb.2:
+  ; CHECK:   liveins: $lr, $r8, $r9, $r10, $r11
+  ; CHECK:   $r2 = tMOVr $lr, 14 /* CC::al */, $noreg
+  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg
+  bb.0:
+    liveins: $lr
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r1, $cpsr = tMOVi8 2, 14, $noreg
+    $r2, $cpsr = tMOVi8 3, 14, $noreg
+    $r3, $cpsr = tMOVi8 4, 14, $noreg
+    $r4, $cpsr = tMOVi8 5, 14, $noreg
+    $r5, $cpsr = tMOVi8 6, 14, $noreg
+    $r6, $cpsr = tMOVi8 7, 14, $noreg
+    $r7, $cpsr = tMOVi8 8, 14, $noreg
+    $r0, $cpsr = tMOVi8 9, 14, $noreg
+    $r1, $cpsr = tMOVi8 10, 14, $noreg
+  bb.1:
+    liveins: $lr, $r8, $r9, $r10, $r11
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r1, $cpsr = tMOVi8 2, 14, $noreg
+    $r2, $cpsr = tMOVi8 3, 14, $noreg
+    $r3, $cpsr = tMOVi8 4, 14, $noreg
+    $r4, $cpsr = tMOVi8 5, 14, $noreg
+    $r5, $cpsr = tMOVi8 6, 14, $noreg
+    $r6, $cpsr = tMOVi8 7, 14, $noreg
+    $r7, $cpsr = tMOVi8 8, 14, $noreg
+    $r0, $cpsr = tMOVi8 9, 14, $noreg
+    $r1, $cpsr = tMOVi8 10, 14, $noreg
+  bb.2:
+    liveins: $lr, $r8, $r9, $r10, $r11
+    $r2 = tMOVr $lr, 14, $noreg
+    tBX_RET 14, $noreg
 
   ; CHECK-LABEL: name: OUTLINED_FUNCTION_0
   ; CHECK: bb.0:
   ; CHECK:   liveins: $lr, $r6, $r7, $r8, $r9, $r10, $r11
   ; CHECK:   $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r1 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r2 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r3 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r4 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r5 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   MOVPCLR 14 /* CC::al */, $noreg
 
   ; CHECK-LABEL: name: OUTLINED_FUNCTION_1
   ; CHECK: bb.0:
   ; CHECK:   liveins: $lr, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
   ; CHECK:   $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r1 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r2 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r3 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   tBX_RET 14 /* CC::al */, $noreg
 
-
-
+  ; CHECK-LABEL: name: OUTLINED_FUNCTION_2
+  ; CHECK: bb.0:
+  ; CHECK:   liveins: $lr, $r11, $r5, $r6, $r7, $r8, $r9, $r10
+  ; CHECK:   $r0, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   $r0, $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
+  ; CHECK:   $r1, $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
+  ; CHECK:   $r1, $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
+  ; CHECK:   $r2, $cpsr = tMOVi8 5, 14 /* CC::al */, $noreg
+  ; CHECK:   $r2, $cpsr = tMOVi8 6, 14 /* CC::al */, $noreg
+  ; CHECK:   $r3, $cpsr = tMOVi8 7, 14 /* CC::al */, $noreg
+  ; CHECK:   $r3, $cpsr = tMOVi8 8, 14 /* CC::al */, $noreg
+  ; CHECK:   $r4, $cpsr = tMOVi8 9, 14 /* CC::al */, $noreg
+  ; CHECK:   $r4, $cpsr = tMOVi8 10, 14 /* CC::al */, $noreg
+  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg

llvm/test/CodeGen/ARM/machine-outliner-lr-regsave.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=arm-- -run-pass=machine-outliner -verify-machineinstrs \
 # RUN: %s -o - | FileCheck %s
 
 --- |
   define void @outline_save_reg_arm() #0 { ret void }
-  define void @outline_save_reg_thumb() #1 { ret void }
-  declare void @z()
+  define void @outline_save_reg_thumb2() #1 { ret void }
+  define void @outline_save_reg_thumb1() #2 { ret void }
 
   attributes #0 = { minsize optsize }
   attributes #1 = { minsize optsize "target-features"="+armv7-a,+thumb-mode" }
+  attributes #2 = { minsize optsize "target-features"="+armv6-m,+thumb-mode" }
 ...
 ---
 
 name:           outline_save_reg_arm
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: outline_save_reg_arm
   ; CHECK: bb.0:
bb.3:
     $r5 = MOVi 1, 14, $noreg, $noreg
   bb.4:
     liveins: $lr
     $r2 = MOVr $lr, 14, $noreg, $noreg
     BX_RET 14, $noreg
 ...
 ---
 
-name:           outline_save_reg_thumb
+name:           outline_save_reg_thumb2
 tracksRegLiveness: true
 body:             |
-  ; CHECK-LABEL: name: outline_save_reg_thumb
+  ; CHECK-LABEL: name: outline_save_reg_thumb2
   ; CHECK: bb.0:
   ; CHECK:   liveins: $lr
   ; CHECK:   $r6 = tMOVr killed $lr, 14 /* CC::al */, $noreg
   ; CHECK:   tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0
   ; CHECK:   $lr = tMOVr killed $r6, 14 /* CC::al */, $noreg
   ; CHECK: bb.1:
   ; CHECK:   liveins: $lr
   ; CHECK:   $r6 = tMOVr killed $lr, 14 /* CC::al */, $noreg
bb.3:
     $r2 = t2MOVi 1, 14, $noreg, $noreg
     $r3 = t2MOVi 1, 14, $noreg, $noreg
     $r4 = t2MOVi 1, 14, $noreg, $noreg
     $r5 = t2MOVi 1, 14, $noreg, $noreg
   bb.4:
     liveins: $lr
     $r2 = tMOVr $lr, 14, $noreg
     tBX_RET 14, $noreg
+...
+---
+
+name:           outline_save_reg_thumb1
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: outline_save_reg_thumb1
+  ; CHECK: bb.0:
+  ; CHECK:   liveins: $lr
+  ; CHECK:   $r7 = tMOVr killed $lr, 14 /* CC::al */, $noreg
+  ; CHECK:   tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_2
+  ; CHECK:   $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg
+  ; CHECK: bb.1:
+  ; CHECK:   liveins: $lr
+  ; CHECK:   $r7 = tMOVr killed $lr, 14 /* CC::al */, $noreg
+  ; CHECK:   tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_2
+  ; CHECK:   $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg
+  ; CHECK: bb.2:
+  ; CHECK:   liveins: $lr
+  ; CHECK:   tPUSH 14 /* CC::al */, $noreg, $r7, implicit-def $sp, implicit $sp
+  ; CHECK:   tPUSH 14 /* CC::al */, $noreg, $lr, implicit-def $sp, implicit $sp
+  ; CHECK:   tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_2
+  ; CHECK:   tPOP 14 /* CC::al */, $noreg, def $r7, implicit-def $sp, implicit $sp
+  ; CHECK:   $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg
+  ; CHECK:   tPOP 14 /* CC::al */, $noreg, def $r7, implicit-def $sp, implicit $sp
+  ; CHECK: bb.3:
+  ; CHECK:   liveins: $lr, $r0, $r6, $r7
+  ; CHECK:   $r7 = tMOVr killed $lr, 14 /* CC::al */, $noreg
+  ; CHECK:   tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_2
+  ; CHECK:   $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg
+  ; CHECK: bb.4:
+  ; CHECK:   liveins: $lr
+  ; CHECK:   $r2 = tMOVr $lr, 14 /* CC::al */, $noreg
+  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg
+  bb.0:
+    liveins: $lr
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r1, $cpsr = tMOVi8 1, 14, $noreg
+    $r2, $cpsr = tMOVi8 1, 14, $noreg
+    $r3, $cpsr = tMOVi8 1, 14, $noreg
+    $r4, $cpsr = tMOVi8 1, 14, $noreg
+    $r5, $cpsr = tMOVi8 1, 14, $noreg
+    $r6, $cpsr = tMOVi8 1, 14, $noreg
+  bb.1:
+    liveins: $lr
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r1, $cpsr = tMOVi8 1, 14, $noreg
+    $r2, $cpsr = tMOVi8 1, 14, $noreg
+    $r3, $cpsr = tMOVi8 1, 14, $noreg
+    $r4, $cpsr = tMOVi8 1, 14, $noreg
+    $r5, $cpsr = tMOVi8 1, 14, $noreg
+    $r6, $cpsr = tMOVi8 1, 14, $noreg
+  bb.2:
+    liveins: $lr
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r1, $cpsr = tMOVi8 1, 14, $noreg
+    $r2, $cpsr = tMOVi8 1, 14, $noreg
+    $r3, $cpsr = tMOVi8 1, 14, $noreg
+    $r4, $cpsr = tMOVi8 1, 14, $noreg
+    $r5, $cpsr = tMOVi8 1, 14, $noreg
+    $r6, $cpsr = tMOVi8 1, 14, $noreg
+  bb.3:
+    liveins: $lr, $r0, $r6, $r7, $r8, $r9, $r10, $r11
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r1, $cpsr = tMOVi8 1, 14, $noreg
+    $r2, $cpsr = tMOVi8 1, 14, $noreg
+    $r3, $cpsr = tMOVi8 1, 14, $noreg
+    $r4, $cpsr = tMOVi8 1, 14, $noreg
+    $r5, $cpsr = tMOVi8 1, 14, $noreg
+    $r6, $cpsr = tMOVi8 1, 14, $noreg
+  bb.4:
+    liveins: $lr
+    $r2 = tMOVr $lr, 14, $noreg
+    tBX_RET 14, $noreg
 
   ; CHECK-LABEL: name: OUTLINED_FUNCTION_0
   ; CHECK: bb.0:
   ; CHECK:   liveins: $lr
   ; CHECK:   $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r1 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r2 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r3 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r4 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r5 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   tBX_RET 14 /* CC::al */, $noreg
 
   ; CHECK-LABEL: name: OUTLINED_FUNCTION_1
   ; CHECK: bb.0:
   ; CHECK:   liveins: $lr
   ; CHECK:   $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r1 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r2 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r3 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r4 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r5 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   MOVPCLR 14 /* CC::al */, $noreg
 
+  ; CHECK-LABEL: name: OUTLINED_FUNCTION_2
+  ; CHECK: bb.0:
+  ; CHECK:   liveins: $lr
+  ; CHECK:   $r0, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   $r1, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   $r2, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   $r3, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   $r4, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   $r5, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   $r6, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg

llvm/test/CodeGen/ARM/machine-outliner-no-lr-save.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=arm-- -run-pass=machine-outliner -verify-machineinstrs \
 # RUN: %s -o - | FileCheck %s
 
 --- |
   define void @outline_no_save_ok_arm() #0 { ret void }
-  define void @outline_no_save_ok_thumb() #1 { ret void }
+  define void @outline_no_save_ok_thumb2() #1 { ret void }
+  define void @outline_no_save_ok_thumb1() #2 { ret void }
 
   declare void @foo()
 
   attributes #0 = { minsize optsize }
   attributes #1 = { minsize optsize "target-features"="+armv7-a,+thumb-mode" }
+  attributes #2 = { minsize optsize "target-features"="+armv6-m,+thumb-mode" }
 ...
 ---
 
 name:           outline_no_save_ok_arm
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: outline_no_save_ok_arm
   ; CHECK: bb.0:
bb.1:
     $r2 = MOVi 1, 14, $noreg, $noreg
     $r2 = MOVi 1, 14, $noreg, $noreg
     $r3 = LDRi12 $sp, 8, 14, $noreg
   bb.2:
     BX_RET 14, $noreg
 ...
 ---
 
-name:           outline_no_save_ok_thumb
+name:           outline_no_save_ok_thumb2
 tracksRegLiveness: true
 body:             |
-  ; CHECK-LABEL: name: outline_no_save_ok_thumb
+  ; CHECK-LABEL: name: outline_no_save_ok_thumb2
   ; CHECK: bb.0:
   ; CHECK:   tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0
   ; CHECK: bb.1:
   ; CHECK:   tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0
   ; CHECK: bb.2:
   ; CHECK:   tBX_RET 14 /* CC::al */, $noreg
   bb.0:
     $r2 = t2MOVi 1, 14, $noreg, $noreg
     $r2 = t2MOVi 1, 14, $noreg, $noreg
     $r2 = t2MOVi 1, 14, $noreg, $noreg
     $r2 = t2MOVi 1, 14, $noreg, $noreg
     t2STRi12 $r2, $sp, 0, 14, $noreg
   bb.1:
     $r2 = t2MOVi 1, 14, $noreg, $noreg
     $r2 = t2MOVi 1, 14, $noreg, $noreg
     $r2 = t2MOVi 1, 14, $noreg, $noreg
     $r2 = t2MOVi 1, 14, $noreg, $noreg
     t2STRi12 $r2, $sp, 0, 14, $noreg
   bb.2:
     tBX_RET 14, $noreg
 
+...
+---
+
+name:           outline_no_save_ok_thumb1
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: outline_no_save_ok_thumb1
+  ; CHECK: bb.0:
+  ; CHECK:   tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_2
+  ; CHECK: bb.1:
+  ; CHECK:   tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_2
+  ; CHECK: bb.2:
+  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg
+  bb.0:
+    $r2, $cpsr = tMOVi8 1, 14, $noreg
+    $r2, $cpsr = tMOVi8 1, 14, $noreg
+    $r2, $cpsr = tMOVi8 1, 14, $noreg
+    $r2, $cpsr = tMOVi8 1, 14, $noreg
+    $r2, $cpsr = tMOVi8 1, 14, $noreg
+    tSTRspi $r2, $sp, 0, 14, $noreg
+  bb.1:
+    $r2, $cpsr = tMOVi8 1, 14, $noreg
+    $r2, $cpsr = tMOVi8 1, 14, $noreg
+    $r2, $cpsr = tMOVi8 1, 14, $noreg
+    $r2, $cpsr = tMOVi8 1, 14, $noreg
+    $r2, $cpsr = tMOVi8 1, 14, $noreg
+    tSTRspi $r2, $sp, 0, 14, $noreg
+  bb.2:
+    tBX_RET 14, $noreg
+
   ; CHECK-LABEL: name: OUTLINED_FUNCTION_0
   ; CHECK: bb.0:
   ; CHECK:   $r2 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r2 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r2 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r2 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   t2STRi12 $r2, $sp, 0, 14 /* CC::al */, $noreg
   ; CHECK:   tBX_RET 14 /* CC::al */, $noreg
 
   ; CHECK-LABEL: name: OUTLINED_FUNCTION_1
   ; CHECK: bb.0:
   ; CHECK:   $r2 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r2 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r2 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r2 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $r3 = LDRi12 $sp, 8, 14 /* CC::al */, $noreg
   ; CHECK:   MOVPCLR 14 /* CC::al */, $noreg
+
+  ; CHECK-LABEL: name: OUTLINED_FUNCTION_2
+  ; CHECK: bb.0:
+  ; CHECK:   $r2, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   $r2, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   $r2, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   $r2, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   $r2, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   tSTRspi $r2, $sp, 0, 14 /* CC::al */, $noreg
+  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg

llvm/test/CodeGen/ARM/machine-outliner-tail.ll

 ; RUN: llc -enable-machine-outliner -verify-machineinstrs -mtriple=arm-- \
 ; RUN: --stop-after=machine-outliner < %s | FileCheck %s --check-prefix=ARM
 ; RUN: llc -enable-machine-outliner -verify-machineinstrs -mtriple=thumbv7-- \
-; RUN: --stop-after=machine-outliner < %s | FileCheck %s --check-prefix=THUMB
+; RUN: --stop-after=machine-outliner < %s | FileCheck %s --check-prefix=THUMB2
+; RUN: llc -verify-machineinstrs -mtriple=thumbv8m.main \
+; RUN: --stop-after=machine-outliner < %s | FileCheck %s --check-prefix=THUMB2
 ; RUN: llc -enable-machine-outliner -verify-machineinstrs \
 ; RUN: -mtriple=thumbv7-apple-darwin --stop-after=machine-outliner < %s \
 ; RUN: | FileCheck %s --check-prefix=MACHO
 ; RUN: llc -enable-machine-outliner -verify-machineinstrs -mtriple=thumbv5-- \
 ; RUN: --stop-after=machine-outliner < %s | FileCheck %s --check-prefix=THUMB1
-; RUN: llc -verify-machineinstrs -mtriple=thumbv8m.main \
-; RUN: --stop-after=machine-outliner < %s | FileCheck %s --check-prefix=THUMB
 
 ; ARM-LABEL: name:            OUTLINED_FUNCTION_0
 ; ARM: $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
 ; ARM-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
 ; ARM-NEXT: $r2 = MOVi 3, 14 /* CC::al */, $noreg, $noreg
 ; ARM-NEXT: $r3 = MOVi 4, 14 /* CC::al */, $noreg, $noreg
 ; ARM-NEXT: TAILJMPd @z
 
-; THUMB-LABEL: name:            OUTLINED_FUNCTION_0
-; THUMB: $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
-; THUMB-NEXT: $r1, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
-; THUMB-NEXT: $r2, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
-; THUMB-NEXT: $r3, dead $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
-; THUMB-NEXT: tTAILJMPdND @z, 14 /* CC::al */, $noreg
+; THUMB2-LABEL: name:            OUTLINED_FUNCTION_0
+; THUMB2: $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+; THUMB2-NEXT: $r1, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
+; THUMB2-NEXT: $r2, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
+; THUMB2-NEXT: $r3, dead $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
+; THUMB2-NEXT: tTAILJMPdND @z, 14 /* CC::al */, $noreg
+
+; THUMB1-LABEL: name:            OUTLINED_FUNCTION_0
+; THUMB1: $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+; THUMB1-NEXT: $r1, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
+; THUMB1-NEXT: $r2, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
+; THUMB1-NEXT: $r3, dead $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
+; THUMB1-NEXT: tTAILJMPdND @z, 14 /* CC::al */, $noreg
 
 ; MACHO-LABEL: name:            OUTLINED_FUNCTION_0
 ; MACHO: $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
 ; MACHO-NEXT: $r1, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
 ; MACHO-NEXT: $r2, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
 ; MACHO-NEXT: $r3, dead $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
 ; MACHO-NEXT: tTAILJMPd @z, 14 /* CC::al */, $noreg
 
-; THUMB1-NOT: OUTLINED_FUNCTION_0
-
 define void @a() #0 {
 entry:
   tail call void @z(i32 1, i32 2, i32 3, i32 4)
   ret void
 }
 
 declare void @z(i32, i32, i32, i32)
 
 define dso_local void @b(i32* nocapture readnone %p) #0 {
 entry:
   tail call void @z(i32 1, i32 2, i32 3, i32 4)
   ret void
 }
 
 attributes #0 = { minsize optsize }

llvm/test/CodeGen/ARM/machine-outliner-thumb-cfi-call.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv6-- -run-pass=machine-outliner -verify-machineinstrs \
+# RUN: %s -o - | FileCheck %s --check-prefixes=THUMB1,ALL
+# RUN: llc -mtriple=thumbv7-- -run-pass=machine-outliner -verify-machineinstrs \
+# RUN: %s -o - | FileCheck %s --check-prefixes=THUMB2,ALL
+
+--- |
+  define void @call_save_lr_to_stack() #0 { ret void }
+  define void @call_save_lr_to_register() #0 { ret void }
+
+  attributes #0 = { minsize optsize }
+...
+---
+
+name:           call_save_lr_to_stack
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $lr
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r0, $cpsr = tMOVi8 2, 14, $noreg
+    $r1, $cpsr = tMOVi8 3, 14, $noreg
+    $r1, $cpsr = tMOVi8 4, 14, $noreg
+    $r2, $cpsr = tMOVi8 5, 14, $noreg
+    $r2, $cpsr = tMOVi8 6, 14, $noreg
+    $r3, $cpsr = tMOVi8 7, 14, $noreg
+    $r3, $cpsr = tMOVi8 8, 14, $noreg
+    $r4, $cpsr = tMOVi8 9, 14, $noreg
+    $r4, $cpsr = tMOVi8 10, 14, $noreg
+    $r5, $cpsr = tMOVi8 11, 14, $noreg
+    $r5, $cpsr = tMOVi8 12, 14, $noreg
+    $r6, $cpsr = tMOVi8 13, 14, $noreg
+    $r6, $cpsr = tMOVi8 14, 14, $noreg
+    $r0, $cpsr = tMOVi8 15, 14, $noreg
+    $r0, $cpsr = tMOVi8 16, 14, $noreg
+  bb.1:
+    liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r0, $cpsr = tMOVi8 2, 14, $noreg
+    $r1, $cpsr = tMOVi8 3, 14, $noreg
+    $r1, $cpsr = tMOVi8 4, 14, $noreg
+    $r2, $cpsr = tMOVi8 5, 14, $noreg
+    $r2, $cpsr = tMOVi8 6, 14, $noreg
+    $r3, $cpsr = tMOVi8 7, 14, $noreg
+    $r3, $cpsr = tMOVi8 8, 14, $noreg
+    $r4, $cpsr = tMOVi8 9, 14, $noreg
+    $r4, $cpsr = tMOVi8 10, 14, $noreg
+    $r5, $cpsr = tMOVi8 11, 14, $noreg
+    $r5, $cpsr = tMOVi8 12, 14, $noreg
+    $r6, $cpsr = tMOVi8 13, 14, $noreg
+    $r6, $cpsr = tMOVi8 14, 14, $noreg
+    $r0, $cpsr = tMOVi8 15, 14, $noreg
+    $r0, $cpsr = tMOVi8 16, 14, $noreg
+  bb.3:
+    liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
+    tBX_RET 14, $noreg
+
+
+  ; THUMB1-LABEL: name: call_save_lr_to_stack
+  ; THUMB1: bb.0:
+  ; THUMB1:        tPUSH 14 /* CC::al */, $noreg, $r7, implicit-def $sp, implicit $sp
+  ; THUMB1-NEXT:   tPUSH 14 /* CC::al */, $noreg, $lr, implicit-def $sp, implicit $sp
+  ; THUMB1-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
+  ; THUMB1-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -8
+  ; THUMB1:        tPOP 14 /* CC::al */, $noreg, def $r7, implicit-def $sp, implicit $sp
+  ; THUMB1-NEXT:   $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg
+  ; THUMB1-NEXT:   tPOP 14 /* CC::al */, $noreg, def $r7, implicit-def $sp, implicit $sp
+  ; THUMB1-NEXT:   frame-destroy CFI_INSTRUCTION def_cfa_offset 0
+  ; THUMB1-NEXT:   frame-destroy CFI_INSTRUCTION restore $lr
+  ; THUMB1: bb.1:
+  ; THUMB1:        tPUSH 14 /* CC::al */, $noreg, $r7, implicit-def $sp, implicit $sp
+  ; THUMB1-NEXT:   tPUSH 14 /* CC::al */, $noreg, $lr, implicit-def $sp, implicit $sp
+  ; THUMB1-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
+  ; THUMB1-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -8
+  ; THUMB1-NEXT:   frame-setup CFI_INSTRUCTION offset $r7, -4
+  ; THUMB1:        tPOP 14 /* CC::al */, $noreg, def $r7, implicit-def $sp, implicit $sp
+  ; THUMB1-NEXT:   $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg
+  ; THUMB1-NEXT:   tPOP 14 /* CC::al */, $noreg, def $r7, implicit-def $sp, implicit $sp
+  ; THUMB1-NEXT:   frame-destroy CFI_INSTRUCTION def_cfa_offset 0
+  ; THUMB1-NEXT:   frame-destroy CFI_INSTRUCTION restore $lr
+  ; THUMB1-NEXT:   frame-destroy CFI_INSTRUCTION restore $r7
+
+  ; THUMB2-LABEL: name: call_save_lr_to_stack
+  ; THUMB2: bb.0:
+  ; THUMB2:        early-clobber $sp = t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg
+  ; THUMB2-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
+  ; THUMB2-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -8
+  ; THUMB2:        $lr, $sp = t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg
+  ; THUMB2-NEXT:   frame-destroy CFI_INSTRUCTION def_cfa_offset 0
+  ; THUMB2-NEXT:   frame-destroy CFI_INSTRUCTION restore $lr
+  ; THUMB2: bb.1:
+  ; THUMB2:        early-clobber $sp = t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg
+  ; THUMB2-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
+  ; THUMB2-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -8
+  ; THUMB2:        $lr, $sp = t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg
+  ; THUMB2-NEXT:   frame-destroy CFI_INSTRUCTION def_cfa_offset 0
+  ; THUMB2-NEXT:   frame-destroy CFI_INSTRUCTION restore $lr
+
+...
+---
+
+name:           call_save_lr_to_register
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $lr
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r0, $cpsr = tMOVi8 2, 14, $noreg
+    $r1, $cpsr = tMOVi8 3, 14, $noreg
+    $r1, $cpsr = tMOVi8 4, 14, $noreg
+    $r2, $cpsr = tMOVi8 5, 14, $noreg
+    $r2, $cpsr = tMOVi8 6, 14, $noreg
+    $r3, $cpsr = tMOVi8 7, 14, $noreg
+    $r3, $cpsr = tMOVi8 8, 14, $noreg
+    $r4, $cpsr = tMOVi8 9, 14, $noreg
+    $r4, $cpsr = tMOVi8 10, 14, $noreg
+  bb.1:
+    liveins: $lr, $r8, $r9, $r10, $r11
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r0, $cpsr = tMOVi8 2, 14, $noreg
+    $r1, $cpsr = tMOVi8 3, 14, $noreg
+    $r1, $cpsr = tMOVi8 4, 14, $noreg
+    $r2, $cpsr = tMOVi8 5, 14, $noreg
+    $r2, $cpsr = tMOVi8 6, 14, $noreg
+    $r3, $cpsr = tMOVi8 7, 14, $noreg
+    $r3, $cpsr = tMOVi8 8, 14, $noreg
+    $r4, $cpsr = tMOVi8 9, 14, $noreg
+    $r4, $cpsr = tMOVi8 10, 14, $noreg
+  bb.3:
+    liveins: $lr, $r8, $r9, $r10, $r11
+    tBX_RET 14, $noreg
+
+
+  ; ALL-LABEL: name: call_save_lr_to_register
+  ; ALL:       bb.0:
+  ; ALL:         $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg
+  ; ALL-NEXT:    frame-setup CFI_INSTRUCTION register $lr, $r5
+  ; ALL:         tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_
+  ; ALL-NEXT:    $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg
+  ; ALL:       bb.1:
+  ; ALL:         $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg
+  ; ALL-NEXT:    frame-setup CFI_INSTRUCTION register $lr, $r5
+  ; ALL:         tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_
+  ; ALL-NEXT:    $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg

llvm/test/CodeGen/ARM/machine-outliner-thumb-cfi-frame.mir

+# RUN: llc -mtriple=thumbv6-- -run-pass=prologepilog -run-pass=machine-outliner \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=THUMB1
+# RUN: llc -mtriple=thumbv7-- -run-pass=prologepilog -run-pass=machine-outliner \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=THUMB2
+
+--- |
+  define void @frame_save_lr_to_stack() #0 { ret void }
+  define void @bar() #0 { ret void }
+
+  attributes #0 = { minsize optsize }
+...
+---
+
+name:           bar
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    BX_RET 14, $noreg
+...
+---
+
+name:           frame_save_lr_to_stack
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    tBL 14, $noreg, @bar, implicit-def dead $lr, implicit $sp
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r1, $cpsr = tMOVi8 2, 14, $noreg
+    $r2, $cpsr = tMOVi8 3, 14, $noreg
+    $r3, $cpsr = tMOVi8 4, 14, $noreg
+    tBL 14, $noreg, @bar, implicit-def dead $lr, implicit $sp
+    $r0, $cpsr = tMOVi8 5, 14, $noreg
+    $r1, $cpsr = tMOVi8 6, 14, $noreg
+    $r2, $cpsr = tMOVi8 7, 14, $noreg
+    $r3, $cpsr = tMOVi8 8, 14, $noreg
+  bb.1:
+    tBL 14, $noreg, @bar, implicit-def dead $lr, implicit $sp
+    $r0, $cpsr = tMOVi8 1, 14, $noreg
+    $r1, $cpsr = tMOVi8 2, 14, $noreg
+    $r2, $cpsr = tMOVi8 3, 14, $noreg
+    $r3, $cpsr = tMOVi8 4, 14, $noreg
+    tBL 14, $noreg, @bar, implicit-def dead $lr, implicit $sp
+    $r0, $cpsr = tMOVi8 5, 14, $noreg
+    $r1, $cpsr = tMOVi8 6, 14, $noreg
+    $r2, $cpsr = tMOVi8 7, 14, $noreg
+    $r3, $cpsr = tMOVi8 8, 14, $noreg
+  bb.3:
+    tBX_RET 14, $noreg
+
+  ; THUMB1-LABEL: OUTLINED_FUNCTION_0
+  ; THUMB1:       bb.0:
+  ; THUMB1:         tPUSH 14 /* CC::al */, $noreg, $r4, implicit-def $sp, implicit $sp
+  ; THUMB1-NEXT:    tPUSH 14 /* CC::al */, $noreg, $lr, implicit-def $sp, implicit $sp
+  ; THUMB1-NEXT:    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+  ; THUMB1-NEXT:    frame-setup CFI_INSTRUCTION offset $lr, -8
+  ; THUMB1-NEXT:    frame-setup CFI_INSTRUCTION offset $r4, -4
+  ; THUMB1:         tPOP 14 /* CC::al */, $noreg, def $r4, implicit-def $sp, implicit $sp
+  ; THUMB1-NEXT:    $lr = tMOVr killed $r4, 14 /* CC::al */, $noreg
+  ; THUMB1-NEXT:    tPOP 14 /* CC::al */, $noreg, def $r4, implicit-def $sp, implicit $sp
+  ; THUMB1-NEXT:    frame-destroy CFI_INSTRUCTION def_cfa_offset 0
+  ; THUMB1-NEXT:    frame-destroy CFI_INSTRUCTION restore $lr
+  ; THUMB1-NEXT:    frame-destroy CFI_INSTRUCTION restore $r4
+  ; THUMB1-NEXT:    tBX_RET 14 /* CC::al */, $noreg
+
+  ; THUMB2-LABEL: OUTLINED_FUNCTION_0
+  ; THUMB2:       bb.0:
+  ; THUMB2:         early-clobber $sp = t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg
+  ; THUMB2-NEXT:    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+  ; THUMB2-NEXT:    frame-setup CFI_INSTRUCTION offset $lr, -8
+  ; THUMB2:         $lr, $sp = t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg
+  ; THUMB2-NEXT:    frame-destroy CFI_INSTRUCTION def_cfa_offset 0
+  ; THUMB2-NEXT:    frame-destroy CFI_INSTRUCTION restore $lr
+  ; THUMB2-NEXT:    tBX_RET 14 /* CC::al */, $noreg

llvm/test/CodeGen/ARM/machine-outliner-thunk.ll

 ; RUN: llc -enable-machine-outliner -verify-machineinstrs -mtriple=armv7-- \
 ; RUN: -stop-after=machine-outliner < %s | FileCheck %s --check-prefix=ARM
 ; RUN: llc -enable-machine-outliner -verify-machineinstrs -mtriple=thumbv7-- \
-; RUN: -stop-after=machine-outliner < %s | FileCheck %s --check-prefix=THUMB
+; RUN: -stop-after=machine-outliner < %s | FileCheck %s --check-prefix=THUMB2
 ; RUN: llc -enable-machine-outliner -verify-machineinstrs \
 ; RUN: -mtriple=thumbv7-apple-darwin -stop-after=machine-outliner < %s \
 ; RUN: | FileCheck %s --check-prefix=MACHO
 ; RUN: llc -enable-machine-outliner -verify-machineinstrs -mtriple=thumbv5-- \
 ; RUN: --stop-after=machine-outliner < %s | FileCheck %s --check-prefix=THUMB1
 ; RUN: llc -verify-machineinstrs -mtriple=thumbv8m.main \
-; RUN: --stop-after=machine-outliner < %s | FileCheck %s --check-prefix=THUMB
+; RUN: --stop-after=machine-outliner < %s | FileCheck %s --check-prefix=THUMB2
 
 declare i32 @thunk_called_fn(i32, i32, i32, i32)
 
 define i32 @a() #0 {
 ; ARM-LABEL: name:             a
 ; ARM:       bb.0.entry:
 ; ARM-NEXT:    liveins: $r11, $lr
 ; ARM:         $sp = frame-setup STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r11, killed $lr
 ; ARM-NEXT:    frame-setup CFI_INSTRUCTION def_cfa_offset 8
 ; ARM-NEXT:    frame-setup CFI_INSTRUCTION offset $lr, -4
 ; ARM-NEXT:    frame-setup CFI_INSTRUCTION offset $r11, -8
 ; ARM-NEXT:    BL @OUTLINED_FUNCTION_0{{.*}}
 ; ARM-NEXT:    renamable $r0 = ADDri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg
 ; ARM-NEXT:    $sp = frame-destroy LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r11, def $pc, implicit killed $r0
 
-; THUMB-LABEL: name:             a
-; THUMB:       bb.0.entry:
-; THUMB-NEXT:    liveins: $r7, $lr
-; THUMB:         frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr
-; THUMB-NEXT:    frame-setup CFI_INSTRUCTION def_cfa_offset 8
-; THUMB-NEXT:    frame-setup CFI_INSTRUCTION offset $lr, -4
-; THUMB-NEXT:    frame-setup CFI_INSTRUCTION offset $r7, -8
-; THUMB-NEXT:    tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0{{.*}}
-; THUMB-NEXT:    renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 8, 14 /* CC::al */, $noreg
-; THUMB-NEXT:    tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+; THUMB2-LABEL: name:             a
+; THUMB2:       bb.0.entry:
+; THUMB2-NEXT:    liveins: $r7, $lr
+; THUMB2:         frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr
+; THUMB2-NEXT:    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+; THUMB2-NEXT:    frame-setup CFI_INSTRUCTION offset $lr, -4
+; THUMB2-NEXT:    frame-setup CFI_INSTRUCTION offset $r7, -8
+; THUMB2-NEXT:    tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0{{.*}}
+; THUMB2-NEXT:    renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 8, 14 /* CC::al */, $noreg
+; THUMB2-NEXT:    tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+
+; THUMB1-LABEL: name:             a
+; THUMB1:       bb.0.entry:
+; THUMB1-NEXT:    liveins: $r7, $lr
+; THUMB1:         frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr
+; THUMB1-NEXT:    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+; THUMB1-NEXT:    frame-setup CFI_INSTRUCTION offset $lr, -4
+; THUMB1-NEXT:    frame-setup CFI_INSTRUCTION offset $r7, -8
+; THUMB1-NEXT:    tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0{{.*}}
+; THUMB1-NEXT:    renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 8, 14 /* CC::al */, $noreg
+; THUMB1-NEXT:    tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
 
 ; MACHO-LABEL: name:             a
 ; MACHO:       bb.0.entry:
 ; MACHO-NEXT:    liveins: $lr
 ; MACHO:         early-clobber $sp = frame-setup t2STR_PRE killed $lr, $sp, -4, 14 /* CC::al */, $noreg
 ; MACHO-NEXT:    frame-setup CFI_INSTRUCTION def_cfa_offset 4
 ; MACHO-NEXT:    frame-setup CFI_INSTRUCTION offset $lr, -4
 ; MACHO-NEXT:    tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0{{.*}}
 ; MACHO-NEXT:    renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 8, 14 /* CC::al */, $noreg
 ; MACHO-NEXT:    $lr, $sp = frame-destroy t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg
 ; MACHO-NEXT:    tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
 
-; THUMB1-NOT: OUTLINED_FUNCTION_0
-
 entry:
   %call = tail call i32 @thunk_called_fn(i32 1, i32 2, i32 3, i32 4)
   %cx = add i32 %call, 8
   ret i32 %cx
 }
 
 define i32 @b() #0 {
 ; ARM-LABEL: name:             b
 ; ARM:       bb.0.entry:
 ; ARM-NEXT:    liveins: $r11, $lr
 ; ARM:         $sp = frame-setup STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r11, killed $lr
 ; ARM-NEXT:    frame-setup CFI_INSTRUCTION def_cfa_offset 8
 ; ARM-NEXT:    frame-setup CFI_INSTRUCTION offset $lr, -4
 ; ARM-NEXT:    frame-setup CFI_INSTRUCTION offset $r11, -8
 ; ARM-NEXT:    BL @OUTLINED_FUNCTION_0{{.*}}
 ; ARM-NEXT:    renamable $r0 = ADDri killed renamable $r0, 88, 14 /* CC::al */, $noreg, $noreg
 ; ARM-NEXT:    $sp = frame-destroy LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r11, def $pc, implicit killed $r0
 
-; THUMB-LABEL: name:             b
-; THUMB:       bb.0.entry:
-; THUMB-NEXT:    liveins: $r7, $lr
-; THUMB:         frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr
-; THUMB-NEXT:    frame-setup CFI_INSTRUCTION def_cfa_offset 8
-; THUMB-NEXT:    frame-setup CFI_INSTRUCTION offset $lr, -4
-; THUMB-NEXT:    frame-setup CFI_INSTRUCTION offset $r7, -8
-; THUMB-NEXT:    tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0{{.*}}
-; THUMB-NEXT:    renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 88, 14 /* CC::al */, $noreg
-; THUMB-NEXT:    tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+; THUMB2-LABEL: name:             b
+; THUMB2:       bb.0.entry:
+; THUMB2-NEXT:    liveins: $r7, $lr
+; THUMB2:         frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr
+; THUMB2-NEXT:    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+; THUMB2-NEXT:    frame-setup CFI_INSTRUCTION offset $lr, -4
+; THUMB2-NEXT:    frame-setup CFI_INSTRUCTION offset $r7, -8
+; THUMB2-NEXT:    tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0{{.*}}
+; THUMB2-NEXT:    renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 88, 14 /* CC::al */, $noreg
+; THUMB2-NEXT:    tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+
+; THUMB1-LABEL: name:             b
+; THUMB1:       bb.0.entry:
+; THUMB1-NEXT:    liveins: $r7, $lr
+; THUMB1:         frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr
+; THUMB1-NEXT:    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+; THUMB1-NEXT:    frame-setup CFI_INSTRUCTION offset $lr, -4
+; THUMB1-NEXT:    frame-setup CFI_INSTRUCTION offset $r7, -8
+; THUMB1-NEXT:    tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0{{.*}}
+; THUMB1-NEXT:    renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 88, 14 /* CC::al */, $noreg
+; THUMB1-NEXT:    tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
 
 ; MACHO-LABEL: name:             b
 ; MACHO:       bb.0.entry:
 ; MACHO-NEXT:    liveins: $lr
 ; MACHO:         early-clobber $sp = frame-setup t2STR_PRE killed $lr, $sp, -4, 14 /* CC::al */, $noreg
 ; MACHO-NEXT:    frame-setup CFI_INSTRUCTION def_cfa_offset 4
 ; MACHO-NEXT:    frame-setup CFI_INSTRUCTION offset $lr, -4
 ; MACHO-NEXT:    tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0{{.*}}

 ; ARM:        bb.0:
 ; ARM-NEXT:   liveins: $r10, $r9, $r8, $r7, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8
 ; ARM:        $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
 ; ARM-NEXT:   $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
 ; ARM-NEXT:   $r2 = MOVi 3, 14 /* CC::al */, $noreg, $noreg
 ; ARM-NEXT:   $r3 = MOVi 4, 14 /* CC::al */, $noreg, $noreg
 ; ARM-NEXT:   TAILJMPd @thunk_called_fn, implicit $sp
 
-; THUMB-LABEL: name:            OUTLINED_FUNCTION_0
-; THUMB:        bb.0:
-; THUMB-NEXT:   liveins: $r11, $r10, $r9, $r8, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8
-; THUMB:        $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
-; THUMB-NEXT:   $r1, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
-; THUMB-NEXT:   $r2, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
-; THUMB-NEXT:   $r3, dead $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
-; THUMB-NEXT:   tTAILJMPdND @thunk_called_fn, 14 /* CC::al */, $noreg, implicit $sp
+; THUMB2-LABEL: name:            OUTLINED_FUNCTION_0
+; THUMB2:        bb.0:
+; THUMB2-NEXT:   liveins: $r11, $r10, $r9, $r8, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8
+; THUMB2:        $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+; THUMB2-NEXT:   $r1, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
+; THUMB2-NEXT:   $r2, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
+; THUMB2-NEXT:   $r3, dead $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
+; THUMB2-NEXT:   tTAILJMPdND @thunk_called_fn, 14 /* CC::al */, $noreg, implicit $sp
+
+; THUMB1-LABEL: name:            OUTLINED_FUNCTION_0
+; THUMB1:        bb.0:
+; THUMB1-NEXT:   liveins: $r6, $r5, $r4, $r11, $r10, $r9, $r8, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8
+; THUMB1:        $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+; THUMB1-NEXT:   $r1, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
+; THUMB1-NEXT:   $r2, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
+; THUMB1-NEXT:   $r3, dead $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
+; THUMB1-NEXT:   tTAILJMPdND @thunk_called_fn, 14 /* CC::al */, $noreg, implicit $sp
 
 ; MACHO-LABEL: name:            OUTLINED_FUNCTION_0
 ; MACHO:        bb.0:
 ; MACHO-NEXT:   liveins: $r7, $r6, $r5, $r4, $r11, $r10, $r8, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8
 ; MACHO:        $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
 ; MACHO-NEXT:   $r1, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
 ; MACHO-NEXT:   $r2, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
 ; MACHO-NEXT:   $r3, dead $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
 ; MACHO-NEXT:   tTAILJMPd @thunk_called_fn, 14 /* CC::al */, $noreg, implicit $sp
 
 attributes #0 = { minsize optsize }