[libc][NFC] Remove headergen for the cacheline size macro.

[sivachandra]

Summary

We want to be able to build and test the string functions in contexts
like that of Fuchsia where LLVM pieces like tablegen are not available.
Since header generation uses tablegen, we are removing the dependency on
headergen here.

[gchatelet]

libc/src/string/memory_utils/utils.h

9–10

Thx for the fix here.

26

Shall we add a supplementary else clause with an #error "unsupported platform" directive?

[sivachandra]

Add default failure case.

libc/src/string/memory_utils/CMakeLists.txt

-add_gen_header(
-  cacheline_size
-  DEF_FILE
-    cacheline_size.h.def
-  GEN_HDR
-    cacheline_size.h
-  PARAMS
-    machine_cacheline_size=cacheline_size_${LIBC_TARGET_MACHINE}.h.inc
-  DATA_FILES
-    cacheline_size_${LIBC_TARGET_MACHINE}.h.inc
-)
-
 add_header_library(
   memory_utils
   HDRS
     utils.h
     memcpy_utils.h
     memset_utils.h
-  DEPENDS
-    .cacheline_size
 )

libc/src/string/memory_utils/cacheline_size.h.def

-//===-- Cacheline Size Constant -------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIBC_SRC_MEMORY_CONSTANTS_H
-#define LLVM_LIBC_SRC_MEMORY_CONSTANTS_H
-
-// LLVM_LIBC_CACHELINE_SIZE
-//
-// Explicitly defines the size of the L1 cache for purposes of alignment.
-//
-// NOTE: this macro should be replaced with the following C++17 features, when
-// those are generally available:
-//
-//   * `std::hardware_constructive_interference_size`
-//   * `std::hardware_destructive_interference_size`
-//
-// See http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0154r1.html
-// for more information.
-
-%%include_file(${machine_cacheline_size})
-
-#endif // LLVM_LIBC_SRC_MEMORY_CONSTANTS_H

libc/src/string/memory_utils/cacheline_size_aarch64.h.inc

-// We would need to read special register ctr_el0 to find out L1 dcache size.
-// This value is a good estimate based on a real aarch64 machine.
-#define LLVM_LIBC_CACHELINE_SIZE 64

libc/src/string/memory_utils/cacheline_size_arm.h.inc

-// Cache line sizes for ARM: These values are not strictly correct since
-// cache line sizes depend on implementations, not architectures.  There
-// are even implementations with cache line sizes configurable at boot
-// time.
-#if defined(__ARM_ARCH_5T__) 
-#define LLVM_LIBC_CACHELINE_SIZE 32
-#elif defined(__ARM_ARCH_7A__)
-#define LLVM_LIBC_CACHELINE_SIZE 64
-#endif

libc/src/string/memory_utils/cacheline_size_ppc64.h.inc

-#define LLVM_LIBC_CACHELINE_SIZE 128

libc/src/string/memory_utils/cacheline_size_x86.h.inc

-#define LLVM_LIBC_CACHELINE_SIZE 64

libc/src/string/memory_utils/cacheline_size_x86_64.h.inc

-#define LLVM_LIBC_CACHELINE_SIZE 64

libc/src/string/memory_utils/utils.h

 //===-- Memory utils --------------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_LIBC_SRC_MEMORY_UTILS_H
-#define LLVM_LIBC_SRC_MEMORY_UTILS_H
+#ifndef LLVM_LIBC_SRC_MEMORY_UTILS_UTILS_H
+#define LLVM_LIBC_SRC_MEMORY_UTILS_UTILS_H
 
-#include "src/string/memory_utils/cacheline_size.h"
+// Cache line sizes for ARM: These values are not strictly correct since
+// cache line sizes depend on implementations, not architectures.  There
+// are even implementations with cache line sizes configurable at boot
+// time.
+#if defined(__aarch64__)
+#define LLVM_LIBC_CACHELINE_SIZE 64
+#elif defined(__ARM_ARCH_5T__)
+#define LLVM_LIBC_CACHELINE_SIZE 32
+#elif defined(__ARM_ARCH_7A__)
+#define LLVM_LIBC_CACHELINE_SIZE 64
+#elif defined(__PPC64__)
+#define LLVM_LIBC_CACHELINE_SIZE 128
+#elif defined(__i386__) || defined(__x86_64__)
+#define LLVM_LIBC_CACHELINE_SIZE 64
+#else
+#error "Unsupported platform for memory functions."
+#endif
 
 #include <stddef.h> // size_t
 #include <stdint.h> // intptr_t / uintptr_t
 
 namespace __llvm_libc {
 
 // Return whether `value` is zero or a power of two.
 static constexpr bool is_power2_or_zero(size_t value) {

 }
 
 template <size_t alignment, typename T> static T *assume_aligned(T *ptr) {
   return reinterpret_cast<T *>(__builtin_assume_aligned(ptr, alignment));
 }
 
 } // namespace __llvm_libc
 
-#endif // LLVM_LIBC_SRC_MEMORY_UTILS_H
+#endif // LLVM_LIBC_SRC_MEMORY_UTILS_UTILS_H