ARM: No need for 8 byte alignment of LDRD on newer CPUs

[MatzeB]

Summary

We only need to be conservative about the alignment of LDRD on older CPUs.

[t.p.northover]

Does the patch actually affect the given test-case? I would have expected thumbv7-apple-darwin to have ABIAlignment of 4 anyway.

test/CodeGen/Thumb2/thumb2-ldrd.ll

5

Is "foo" really any better than "t"? I say either go for a proper rename that gives some hint of what's being tested or leave it as-is.

The best way to check for a function start is "CHECK-LABEL: my_function:" (note the colon at the end).

[MatzeB]

Hmm indeed, I performed my original experiments with an "thumbv7--" triple which has alignment 8 and copied the code to that existing testcase later. So maybe the ABI alignment 8 is a good enough (even though very unintuitive) indicator of whether ldrd on 4 byte aligned data makes sense.

Abandoning this patch, it seems the codegen problems I am looking for are somewhere else.

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1,
   // At the moment, we ignore the memoryoperand's value.
   // If we want to use AliasAnalysis, we should check it accordingly.
   if (!Op0->hasOneMemOperand() ||
       (*Op0->memoperands_begin())->isVolatile())
     return false;
 
   unsigned Align = (*Op0->memoperands_begin())->getAlignment();
   const Function *Func = MF->getFunction();
-  unsigned ReqAlign = STI->hasV6Ops()
-    ? TD->getABITypeAlignment(Type::getInt64Ty(Func->getContext()))
-    : 8;  // Pre-v6 need 8-byte align
+  unsigned ReqAlign = STI->hasV6Ops() ? 4 : 8; // Pre-v6 need 8-byte align
+  // LDRD may actually be slower than a pair of two LDRs if the memory is not
+  // 8 byte aligned on CortexA9.
+  if (STI->isCortexA9())
+    ReqAlign = TD->getABITypeAlignment(Type::getInt64Ty(Func->getContext()));
   if (Align < ReqAlign)
     return false;
 
   // Then make sure the immediate offset fits.
   int OffImm = getMemoryOpOffset(Op0);
   if (isT2) {
     int Limit = (1 << 8) * Scale;
     if (OffImm >= Limit || (OffImm <= -Limit) || (OffImm & (Scale-1)))

test/CodeGen/Thumb2/thumb2-ldrd.ll

 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
 
 @b = external global i64*
 
-define i64 @t(i64 %a) nounwind readonly {
-entry:
+; CHECK-LABEL: foo
 ; CHECK: ldrd
 ; CHECK: umull
+define i64 @foo(i64 %a) nounwind readonly {
+entry:
   %0 = load i64*, i64** @b, align 4
   %1 = load i64, i64* %0, align 4
   %2 = mul i64 %1, %a
   ret i64 %2
 }
+
+; CHECK-LABEL: bar
+; CHECK: ldrd
+; CHECK-NEXT: add
+; CHECK-NEXT: bx
+define i32 @bar(i32* %x) {
+  %addr0 = getelementptr i32, i32* %x, i32 0
+  %addr1 = getelementptr i32, i32* %x, i32 1
+  %v0 = load i32, i32* %addr0
+  %v1 = load i32, i32* %addr1
+  %sum = add i32 %v0, %v1
+  ret i32 %sum
+}