Rename eh_sjlj_{setjmp|longjmp} intrinsic to lightweight_{setjmp|longjmp}

[MatzeB]

Summary

This should make it obvious that they are not used by llvms sjlj exception
handling code but to implement builtin_setjmp and builtin_longjmp.

This is a followup to http://reviews.llvm.org/D9313

[MatzeB]

ping

[rjmccall]

I can't review changes to LLVM targets.

I agree with not naming the intrinsics after builtin_setjmp / builtin_longjmp, because using the word "builtin" in a list of intrinsics feels wrong, but please do mention in the documentation that these intrinsics implement builtin_setjmp / builtin_longjmp and are not their own new thing.

[MatzeB]

New version which properly documents the intrinsics (also mentioning the intention to implement gcc builtin_setjmp/builtin_longjmp with them).

[MatzeB]

Thanks for the review Justin, I update the documentation in the patch and the other comments mentioned in the review, backed out the setting of returns_twice for a different patch (which may be unnecessary), and fixed several places that had strange indentation after renaming.

[ab]

Shouldn't we AutoUpgrade the old intrinsics?

docs/LangRef.rst

8091 ↗

(On Diff #26110)

implement -> implemented

[joerg]

I'd actually prefer if we didn't call them setjmp/longjmp at all. They have practically nothing to do with the libc functions and that's part of the confusion around them.

[MatzeB]

Putting this on hold as of Jörgs request, but that means http://reviews.llvm.org/D9313 should be accepted without renaming the intrinsic.

include/llvm/CodeGen/ISDOpcodes.h

enum NodeType {
     FRAME_TO_ARGS_OFFSET,
 
     /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
     /// 'eh_return' gcc dwarf builtin, which is used to return from
     /// exception. The general meaning is: adjust stack by OFFSET and pass
     /// execution to HANDLER. Many platform-related details also :)
     EH_RETURN,
 
-    /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
-    /// This corresponds to the eh.sjlj.setjmp intrinsic.
+    /// RESULT, OUTCHAIN = EH_LIGHTWEIGHT_SETJMP(INCHAIN, buffer)
+    /// This corresponds to the lightweight_setjmp intrinsic.
     /// It takes an input chain and a pointer to the jump buffer as inputs
     /// and returns an outchain.
-    EH_SJLJ_SETJMP,
+    LIGHTWEIGHT_SETJMP,
 
-    /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
+    /// OUTCHAIN = EH_LIGHTWEIGHT_LONGJMP(INCHAIN, buffer)
     /// This corresponds to the eh.sjlj.longjmp intrinsic.
     /// It takes an input chain and a pointer to the jump buffer as inputs
     /// and returns an outchain.
-    EH_SJLJ_LONGJMP,
+    LIGHTWEIGHT_LONGJMP,
 
     /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN)
     /// The target initializes the dispatch table here.
     EH_SJLJ_SETUP_DISPATCH,
 
     /// TargetConstant* - Like Constant*, but the DAG does not do any folding,
     /// simplification, or lowering of the constant. They are used for constants
     /// which are known to fit in the immediate fields of their users, or for

include/llvm/IR/Intrinsics.td

def int_stackprotectorcheck : Intrinsic<[], [llvm_ptrptr_ty],
                                         [IntrReadWriteArgMem]>;
 
 // A counter increment for instrumentation based profiling.
 def int_instrprof_increment : Intrinsic<[],
                                         [llvm_ptr_ty, llvm_i64_ty,
                                          llvm_i32_ty, llvm_i32_ty],
                                         []>;
 
+// Lightweight setjmp intrinsic like gcc __builtin_setjmp but not necessarily
+// like the libc setjmp.
+def int_lightweight_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
+// Lightweight setjmp intrinsic like gcc __builtin_longjmp but not necessarily
+// like the libc longjmp.
+def int_lightweight_longjmp : Intrinsic<[], [llvm_ptr_ty], [IntrNoReturn]>;
+
 //===------------------- Standard C Library Intrinsics --------------------===//
 //
 
 def int_memcpy  : Intrinsic<[],
                              [llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty,
                               llvm_i32_ty, llvm_i1_ty],
                             [IntrReadWriteArgMem, NoCapture<0>, NoCapture<1>,
                              ReadOnly<1>]>;

 
 def int_eh_dwarf_cfa  : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty]>;
 
 let Properties = [IntrNoMem] in {
   def int_eh_sjlj_lsda             : Intrinsic<[llvm_ptr_ty]>;
   def int_eh_sjlj_callsite         : Intrinsic<[], [llvm_i32_ty]>;
 }
 def int_eh_sjlj_functioncontext : Intrinsic<[], [llvm_ptr_ty]>;
-def int_eh_sjlj_setjmp          : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
-def int_eh_sjlj_longjmp         : Intrinsic<[], [llvm_ptr_ty], [IntrNoReturn]>;
 def int_eh_sjlj_setup_dispatch  : Intrinsic<[], []>;
 
 //===---------------- Generic Variable Attribute Intrinsics----------------===//
 //
 def int_var_annotation : Intrinsic<[],
                                    [llvm_ptr_ty, llvm_ptr_ty,
                                     llvm_ptr_ty, llvm_i32_ty],
                                    [], "llvm.var.annotation">;

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

case ISD::CALLSEQ_END:
     SimpleFinishLegalizing = false;
     break;
   case ISD::EXTRACT_ELEMENT:
   case ISD::FLT_ROUNDS_:
   case ISD::FPOWI:
   case ISD::MERGE_VALUES:
   case ISD::EH_RETURN:
   case ISD::FRAME_TO_ARGS_OFFSET:
-  case ISD::EH_SJLJ_SETJMP:
-  case ISD::EH_SJLJ_LONGJMP:
   case ISD::EH_SJLJ_SETUP_DISPATCH:
+  case ISD::LIGHTWEIGHT_SETJMP:
+  case ISD::LIGHTWEIGHT_LONGJMP:
     // These operations lie about being legal: when they claim to be legal,
     // they should actually be expanded.
     Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
     if (Action == TargetLowering::Legal)
       Action = TargetLowering::Expand;
     break;
   case ISD::INIT_TRAMPOLINE:
   case ISD::ADJUST_TRAMPOLINE:
case ISD::FRAME_TO_ARGS_OFFSET:
     break;
   case ISD::FLT_ROUNDS_:
     Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
     break;
   case ISD::EH_RETURN:
   case ISD::EH_LABEL:
   case ISD::PREFETCH:
   case ISD::VAEND:
-  case ISD::EH_SJLJ_LONGJMP:
+  case ISD::LIGHTWEIGHT_LONGJMP:
     // If the target didn't expand these, there's nothing to do, so just
     // preserve the chain and be done.
     Results.push_back(Node->getOperand(0));
     break;
-  case ISD::EH_SJLJ_SETJMP:
+  case ISD::LIGHTWEIGHT_SETJMP:
     // If the target didn't expand this, just return 'zero' and preserve the
     // chain.
     Results.push_back(DAG.getConstant(0, dl, MVT::i32));
     Results.push_back(Node->getOperand(0));
     break;
   case ISD::ATOMIC_FENCE: {
     // If the target didn't lower this, lower it to '__sync_synchronize()' call
     // FIXME: handle "fence singlethread" more efficiently.

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

case Intrinsic::eh_sjlj_functioncontext: {
     // Get and store the index of the function context.
     MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
     AllocaInst *FnCtx =
       cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
     int FI = FuncInfo.StaticAllocaMap[FnCtx];
     MFI->setFunctionContextIndex(FI);
     return nullptr;
   }
-  case Intrinsic::eh_sjlj_setjmp: {
+  case Intrinsic::lightweight_setjmp: {
     SDValue Ops[2];
     Ops[0] = getRoot();
     Ops[1] = getValue(I.getArgOperand(0));
-    SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
+    SDValue Op = DAG.getNode(ISD::LIGHTWEIGHT_SETJMP, sdl,
                              DAG.getVTList(MVT::i32, MVT::Other), Ops);
     setValue(&I, Op.getValue(0));
     DAG.setRoot(Op.getValue(1));
     return nullptr;
   }
-  case Intrinsic::eh_sjlj_longjmp: {
-    DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
+  case Intrinsic::lightweight_longjmp: {
+    DAG.setRoot(DAG.getNode(ISD::LIGHTWEIGHT_LONGJMP, sdl, MVT::Other,
                             getRoot(), getValue(I.getArgOperand(0))));
     return nullptr;
   }
   case Intrinsic::eh_sjlj_setup_dispatch: {
     DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
                             getRoot()));
     return nullptr;
   }

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

#endif
   case ISD::GLOBAL_OFFSET_TABLE:        return "GLOBAL_OFFSET_TABLE";
   case ISD::RETURNADDR:                 return "RETURNADDR";
   case ISD::FRAMEADDR:                  return "FRAMEADDR";
   case ISD::FRAME_ALLOC_RECOVER:        return "FRAME_ALLOC_RECOVER";
   case ISD::READ_REGISTER:              return "READ_REGISTER";
   case ISD::WRITE_REGISTER:             return "WRITE_REGISTER";
   case ISD::FRAME_TO_ARGS_OFFSET:       return "FRAME_TO_ARGS_OFFSET";
   case ISD::EH_RETURN:                  return "EH_RETURN";
-  case ISD::EH_SJLJ_SETJMP:             return "EH_SJLJ_SETJMP";
-  case ISD::EH_SJLJ_LONGJMP:            return "EH_SJLJ_LONGJMP";
   case ISD::EH_SJLJ_SETUP_DISPATCH:     return "EH_SJLJ_SETUP_DISPATCH";
+  case ISD::LIGHTWEIGHT_SETJMP:         return "LIGHTWEIGHT_SETJMP";
+  case ISD::LIGHTWEIGHT_LONGJMP:        return "LIGHTWEIGHT_LONGJMP";
   case ISD::ConstantPool:               return "ConstantPool";
   case ISD::TargetIndex:                return "TargetIndex";
   case ISD::ExternalSymbol:             return "ExternalSymbol";
   case ISD::BlockAddress:               return "BlockAddress";
   case ISD::INTRINSIC_WO_CHAIN:
   case ISD::INTRINSIC_VOID:
   case ISD::INTRINSIC_W_CHAIN: {
     unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;

lib/Target/ARM/ARMAsmPrinter.cpp

if (!Subtarget->isTargetMachO()) {
       //.short 57086 @ trap
       uint16_t Val = 0xdefe;
       OutStreamer->AddComment("trap");
       OutStreamer->EmitIntValue(Val, 2);
       return;
     }
     break;
   }
-  case ARM::t2Int_eh_sjlj_setjmp:
-  case ARM::t2Int_eh_sjlj_setjmp_nofp:
-  case ARM::tInt_eh_sjlj_setjmp: {
+  case ARM::t2Int_lightweight_setjmp:
+  case ARM::t2Int_lightweight_setjmp_nofp:
+  case ARM::tInt_lightweight_setjmp: {
     // Two incoming args: GPR:$src, GPR:$val
     // mov $val, pc
     // adds $val, #7
     // str $val, [$src, #4]
     // movs r0, #0
     // b 1f
     // movs r0, #1
     // 1:
EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
       .addImm(ARMCC::AL)
       .addReg(0));
 
     MCSymbol *Label = OutContext.CreateDirectionalLocalSymbol(0);
     OutStreamer->EmitLabel(Label);
     return;
   }
 
-  case ARM::Int_eh_sjlj_setjmp_nofp:
-  case ARM::Int_eh_sjlj_setjmp: {
+  case ARM::Int_lightweight_setjmp_nofp:
+  case ARM::Int_lightweight_setjmp: {
     // Two incoming args: GPR:$src, GPR:$val
     // add $val, pc, #8
     // str $val, [$src, #+4]
     // mov r0, #0
     // add pc, pc, #0
     // mov r0, #1
     unsigned SrcReg = MI->getOperand(0).getReg();
     unsigned ValReg = MI->getOperand(1).getReg();
EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
       .addImm(1)
       // Predicate.
       .addImm(ARMCC::AL)
       .addReg(0)
       // 's' bit operand (always reg0 for this).
       .addReg(0));
     return;
   }
-  case ARM::Int_eh_sjlj_longjmp: {
+  case ARM::Int_lightweight_longjmp: {
     // ldr sp, [$src, #8]
     // ldr $scratch, [$src, #4]
     // ldr r7, [$src]
     // bx $scratch
     unsigned SrcReg = MI->getOperand(0).getReg();
     unsigned ScratchReg = MI->getOperand(1).getReg();
     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
       .addReg(ARM::SP)
case ARM::Int_lightweight_longjmp: {
 
     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
       .addReg(ScratchReg)
       // Predicate.
       .addImm(ARMCC::AL)
       .addReg(0));
     return;
   }
-  case ARM::tInt_eh_sjlj_longjmp: {
+  case ARM::tInt_lightweight_longjmp: {
     // ldr $scratch, [$src, #8]
     // mov sp, $scratch
     // ldr $scratch, [$src, #4]
     // ldr r7, [$src]
     // bx $scratch
     unsigned SrcReg = MI->getOperand(0).getReg();
     unsigned ScratchReg = MI->getOperand(1).getReg();
     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)

lib/Target/ARM/ARMBaseInstrInfo.cpp

case ARM::t2MOVTi16_ga_pcrel:
     return 4;
   case ARM::MOVi32imm:
   case ARM::t2MOVi32imm:
     return 8;
   case ARM::CONSTPOOL_ENTRY:
     // If this machine instr is a constant pool entry, its size is recorded as
     // operand #2.
     return MI->getOperand(2).getImm();
-  case ARM::Int_eh_sjlj_longjmp:
+  case ARM::Int_lightweight_longjmp:
     return 16;
-  case ARM::tInt_eh_sjlj_longjmp:
+  case ARM::tInt_lightweight_longjmp:
     return 10;
-  case ARM::Int_eh_sjlj_setjmp:
-  case ARM::Int_eh_sjlj_setjmp_nofp:
+  case ARM::Int_lightweight_setjmp:
+  case ARM::Int_lightweight_setjmp_nofp:
     return 20;
-  case ARM::tInt_eh_sjlj_setjmp:
-  case ARM::t2Int_eh_sjlj_setjmp:
-  case ARM::t2Int_eh_sjlj_setjmp_nofp:
+  case ARM::tInt_lightweight_setjmp:
+  case ARM::t2Int_lightweight_setjmp:
+  case ARM::t2Int_lightweight_setjmp_nofp:
     return 12;
   case ARM::BR_JTr:
   case ARM::BR_JTm:
   case ARM::BR_JTadd:
   case ARM::tBR_JTr:
   case ARM::t2BR_JT:
   case ARM::t2TBB_JT:
   case ARM::t2TBH_JT: {

lib/Target/ARM/ARMISelLowering.h

enum NodeType : unsigned {
       ADDC,         // Add with carry
       ADDE,         // Add using carry
       SUBC,         // Sub with carry
       SUBE,         // Sub using carry
 
       VMOVRRD,      // double to two gprs.
       VMOVDRR,      // Two gprs to double.
 
-      EH_SJLJ_SETJMP,         // SjLj exception handling setjmp.
-      EH_SJLJ_LONGJMP,        // SjLj exception handling longjmp.
+      LIGHTWEIGHT_SETJMP, // __builtin_setjmp
+      LIGHTWEIGHT_LONGJMP, // __builtin_longjmp
       EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
 
       TC_RETURN,    // Tail call return pseudo.
 
       THREAD_POINTER,
 
       DYN_ALLOC,    // Dynamic allocation on the stack.
 
private:
     CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
                                             bool isVarArg) const;
     CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
                                   bool isVarArg) const;
     SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
                              SDLoc dl, SelectionDAG &DAG,
                              const CCValAssign &VA,
                              ISD::ArgFlagsTy Flags) const;
-    SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerLIGHTWEIGHT_SETJMP(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerLIGHTWEIGHT_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
                                     const ARMSubtarget *Subtarget) const;
     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;

lib/Target/ARM/ARMISelLowering.cpp

if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
     // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
     // iff target supports vfp2.
     setOperationAction(ISD::BITCAST, MVT::i64, Custom);
     setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
   }
 
   // We want to custom lower some of our intrinsics.
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
-  setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
-  setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
+  setOperationAction(ISD::LIGHTWEIGHT_SETJMP, MVT::i32, Custom);
+  setOperationAction(ISD::LIGHTWEIGHT_LONGJMP, MVT::Other, Custom);
   setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
   if (Subtarget->isTargetDarwin())
     setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
 
   setOperationAction(ISD::SETCC,     MVT::i32, Expand);
   setOperationAction(ISD::SETCC,     MVT::f32, Expand);
   setOperationAction(ISD::SETCC,     MVT::f64, Expand);
   setOperationAction(ISD::SELECT,    MVT::i32, Custom);
const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case ARMISD::ADDC:          return "ARMISD::ADDC";
   case ARMISD::ADDE:          return "ARMISD::ADDE";
   case ARMISD::SUBC:          return "ARMISD::SUBC";
   case ARMISD::SUBE:          return "ARMISD::SUBE";
 
   case ARMISD::VMOVRRD:       return "ARMISD::VMOVRRD";
   case ARMISD::VMOVDRR:       return "ARMISD::VMOVDRR";
 
-  case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
-  case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
+  case ARMISD::LIGHTWEIGHT_SETJMP: return "ARMISD::LIGHTWEIGHT_SETJMP";
+  case ARMISD::LIGHTWEIGHT_LONGJMP: return "ARMISD::LIGHTWEIGHT_LONGJMP";
 
   case ARMISD::TC_RETURN:     return "ARMISD::TC_RETURN";
 
   case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
 
   case ARMISD::DYN_ALLOC:     return "ARMISD::DYN_ALLOC";
 
   case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
   SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
                                MachinePointerInfo::getConstantPool(),
                                false, false, false, 0);
   SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
   return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
 }
 
 SDValue
-ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
+ARMTargetLowering::LowerLIGHTWEIGHT_SETJMP(SDValue Op, SelectionDAG &DAG)
+  const {
   SDLoc dl(Op);
   SDValue Val = DAG.getConstant(0, dl, MVT::i32);
-  return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
+  return DAG.getNode(ARMISD::LIGHTWEIGHT_SETJMP, dl,
                      DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
                      Op.getOperand(1), Val);
 }
 
 SDValue
-ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
+ARMTargetLowering::LowerLIGHTWEIGHT_LONGJMP(SDValue Op, SelectionDAG &DAG)
+  const {
   SDLoc dl(Op);
-  return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
-                     Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
+  return DAG.getNode(ARMISD::LIGHTWEIGHT_LONGJMP, dl, MVT::Other,
+                     Op.getOperand(0), Op.getOperand(1),
+                     DAG.getConstant(0, dl, MVT::i32));
 }
 
 SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
                                                       SelectionDAG &DAG) const {
   SDLoc dl(Op);
   return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
                      Op.getOperand(0));
 }
SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP:    return LowerINT_TO_FP(Op, DAG);
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:    return LowerFP_TO_INT(Op, DAG);
   case ISD::FCOPYSIGN:     return LowerFCOPYSIGN(Op, DAG);
   case ISD::RETURNADDR:    return LowerRETURNADDR(Op, DAG);
   case ISD::FRAMEADDR:     return LowerFRAMEADDR(Op, DAG);
   case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
-  case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
-  case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
+  case ISD::LIGHTWEIGHT_SETJMP: return LowerLIGHTWEIGHT_SETJMP(Op, DAG);
+  case ISD::LIGHTWEIGHT_LONGJMP: return LowerLIGHTWEIGHT_LONGJMP(Op, DAG);
   case ISD::EH_SJLJ_SETUP_DISPATCH: return LowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
   case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
                                                                Subtarget);
   case ISD::BITCAST:       return ExpandBITCAST(Op.getNode(), DAG);
   case ISD::SHL:
   case ISD::SRL:
   case ISD::SRA:           return LowerShift(Op.getNode(), DAG, Subtarget);
   case ISD::SHL_PARTS:     return LowerShiftLeftParts(Op, DAG);
if (isThumb2)
       AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
     else
       BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
 
     MI->eraseFromParent();   // The pseudo instruction is gone now.
     return BB;
   }
 
-  case ARM::Int_eh_sjlj_setjmp:
-  case ARM::Int_eh_sjlj_setjmp_nofp:
-  case ARM::tInt_eh_sjlj_setjmp:
-  case ARM::t2Int_eh_sjlj_setjmp:
-  case ARM::t2Int_eh_sjlj_setjmp_nofp:
+  case ARM::Int_lightweight_setjmp:
+  case ARM::Int_lightweight_setjmp_nofp:
+  case ARM::tInt_lightweight_setjmp:
+  case ARM::t2Int_lightweight_setjmp:
+  case ARM::t2Int_lightweight_setjmp_nofp:
     return BB;
 
   case ARM::Int_eh_sjlj_setup_dispatch:
     EmitSjLjDispatchBlock(MI, BB);
     return BB;
 
   case ARM::ABS:
   case ARM::t2ABS: {

lib/Target/ARM/ARMInstrInfo.td

def SDT_ARMAnd     : SDTypeProfile<1, 2,
                                     SDTCisVT<2, i32>]>;
 
 def SDT_ARMCmp     : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
 
 def SDT_ARMPICAdd  : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
                                           SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
 
 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
-def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
-                                                 SDTCisInt<2>]>;
-def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
+def SDT_ARMLIGHTWEIGHT_Setjmp : SDTypeProfile<1, 2,
+                                              [SDTCisInt<0>, SDTCisPtrTy<1>,
+def SDT_ARMLIGHTWEIGHT_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>,
+                                                     SDTCisInt<1>]>;
 def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>;
 
 def SDT_ARMMEMBARRIER     : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 
 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
                                            SDTCisInt<1>]>;
 
 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;

 
 def ARMaddc          : SDNode<"ARMISD::ADDC",  SDTBinaryArithWithFlags,
                               [SDNPCommutative]>;
 def ARMsubc          : SDNode<"ARMISD::SUBC",  SDTBinaryArithWithFlags>;
 def ARMadde          : SDNode<"ARMISD::ADDE",  SDTBinaryArithWithFlagsInOut>;
 def ARMsube          : SDNode<"ARMISD::SUBE",  SDTBinaryArithWithFlagsInOut>;
 
 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
-def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
-                               SDT_ARMEH_SJLJ_Setjmp,
+def ARMlightweight_setjmp: SDNode<"ARMISD::LIGHTWEIGHT_SETJMP",
+                                  SDT_ARMLIGHTWEIGHT_Setjmp,
                                   [SDNPHasChain, SDNPSideEffect]>;
-def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
-                               SDT_ARMEH_SJLJ_Longjmp,
+def ARMlightweight_longjmp: SDNode<"ARMISD::LIGHTWEIGHT_LONGJMP",
+                                   SDT_ARMLIGHTWEIGHT_Longjmp,
                                    [SDNPHasChain, SDNPSideEffect]>;
 def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH",
                                       SDT_ARMEH_SJLJ_SetupDispatch,
                                       [SDNPHasChain, SDNPSideEffect]>;
 
 def ARMMemBarrierMCR  : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
                                [SDNPHasChain, SDNPSideEffect]>;
 def ARMPreload        : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
                                [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;

 //   A constant value is passed in $val, and we use the location as a scratch.
 //
 // These are pseudo-instructions and are lowered to individual MC-insts, so
 // no encoding information is necessary.
 let Defs =
   [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR,
     Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
   hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
-  def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
+  def Int_lightweight_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
                                           NoItinerary,
-                         [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
+                         [(set R0, (ARMlightweight_setjmp GPR:$src,
+                                    GPR:$val))]>,
                            Requires<[IsARM, HasVFP2]>;
 }
 
 let Defs =
   [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR ],
   hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
-  def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
+  def Int_lightweight_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
                                                NoItinerary,
-                         [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
+                         [(set R0, (ARMlightweight_setjmp GPR:$src,
+                                    GPR:$val))]>,
                                 Requires<[IsARM, NoVFP]>;
 }
 
 // FIXME: Non-IOS version(s)
 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
     Defs = [ R7, LR, SP ] in {
-def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
+def Int_lightweight_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
                                          NoItinerary,
-                         [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
+                         [(ARMlightweight_longjmp GPR:$src, GPR:$scratch)]>,
                                 Requires<[IsARM]>;
 }
 
 let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in
 def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary,
             [(ARMeh_sjlj_setup_dispatch)]>;
 
 // eh.sjlj.dispatchsetup pseudo-instruction.

lib/Target/ARM/ARMInstrThumb.td

 // tromped upon when we get here from a longjmp(). We force everything out of
 // registers except for our own input by listing the relevant registers in
 // Defs. By doing so, we also cause the prologue/epilogue code to actively
 // preserve all of the callee-saved resgisters, which is exactly what we want.
 // $val is a scratch register for our use.
 let Defs = [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7, R12, CPSR ],
     hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
     usesCustomInserter = 1 in
-def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
+def tInt_lightweight_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
                                   AddrModeNone, 0, NoItinerary, "","",
-                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
+                          [(set R0, (ARMlightweight_setjmp tGPR:$src, tGPR:$val))]>;
 
 // FIXME: Non-IOS version(s)
 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
     Defs = [ R7, LR, SP ] in
-def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
+def tInt_lightweight_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
                               AddrModeNone, 0, IndexModeNone,
                               Pseudo, NoItinerary, "", "",
-                              [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
+                              [(ARMlightweight_longjmp GPR:$src, GPR:$scratch)]>,
                              Requires<[IsThumb]>;
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //
 
 // Comparisons
 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),

lib/Target/ARM/ARMInstrThumb2.td

 def : T2Pat<(and (ldaex_2 addr_offset_none:$addr), 0xffff),
             (t2LDAEXH addr_offset_none:$addr)>;
 def : T2Pat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
             (t2STLEXB GPR:$Rt, addr_offset_none:$addr)>;
 def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
             (t2STLEXH GPR:$Rt, addr_offset_none:$addr)>;
 
 //===----------------------------------------------------------------------===//
-// SJLJ Exception handling intrinsics
-//   eh_sjlj_setjmp() is an instruction sequence to store the return
+// __builtin_setjmp/__builtin_longjmp intrinsics
+//   lightweight_setjmp() is an instruction sequence to store the return
 //   address and save #0 in R0 for the non-longjmp case.
 //   Since by its nature we may be coming from some other function to get
 //   here, and we're using the stack frame for the containing function to
 //   save/restore registers, we can't keep anything live in regs across
-//   the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
-//   when we get here from a longjmp(). We force everything out of registers
-//   except for our own input by listing the relevant registers in Defs. By
-//   doing so, we also cause the prologue/epilogue code to actively preserve
-//   all of the callee-saved resgisters, which is exactly what we want.
+//   the lightweight_setjmp(), else it will almost certainly have been tromped
+//   upon when we get here from a longjmp(). We force everything out of
+//   registers except for our own input by listing the relevant registers in
+//   Defs. By doing so, we also cause the prologue/epilogue code to actively
+//   preserve all of the callee-saved resgisters, which is exactly what we want.
 //   $val is a scratch register for our use.
 let Defs =
   [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR,
     Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
   hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
   usesCustomInserter = 1 in {
-  def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
+  def t2Int_lightweight_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
                                AddrModeNone, 0, NoItinerary, "", "",
-                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
+                               [(set R0, (ARMlightweight_setjmp tGPR:$src,
+                                          tGPR:$val))]>,
                                 Requires<[IsThumb2, HasVFP2]>;
 }
 
 let Defs =
   [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR ],
   hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
   usesCustomInserter = 1 in {
-  def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
+  def t2Int_lightweight_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src,
+                                                        tGPR:$val),
                                AddrModeNone, 0, NoItinerary, "", "",
-                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
+                               [(set R0, (ARMlightweight_setjmp tGPR:$src,
+                                          tGPR:$val))]>,
                                        Requires<[IsThumb2, NoVFP]>;
 }
 
 
 //===----------------------------------------------------------------------===//
 // Control-Flow Instructions
 //
 
 // FIXME: remove when we have a way to marking a MI with these properties.

lib/Target/X86/X86ISelDAGToDAG.cpp

bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
   X86ISelAddressMode AM;
 
   if (Parent &&
       // This list of opcodes are all the nodes that have an "addr:$ptr" operand
       // that are not a MemSDNode, and thus don't have proper addrspace info.
       Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
       Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
       Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
-      Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
-      Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
+      Parent->getOpcode() != X86ISD::LIGHTWEIGHT_SETJMP && // setjmp
+      Parent->getOpcode() != X86ISD::LIGHTWEIGHT_LONGJMP) { // longjmp
     unsigned AddrSpace =
       cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
     // AddrSpace 256 -> GS, 257 -> FS.
     if (AddrSpace == 256)
       AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
     if (AddrSpace == 257)
       AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
   }

lib/Target/X86/X86ISelLowering.h

enum NodeType : unsigned {
 
       // Thread Local Storage.  When calling to an OS provided
       // thunk at the address from an earlier relocation.
       TLSCALL,
 
       // Exception Handling helpers.
       EH_RETURN,
 
-      // SjLj exception handling setjmp.
-      EH_SJLJ_SETJMP,
+      // __builtin_setjmp.
+      LIGHTWEIGHT_SETJMP,
 
-      // SjLj exception handling longjmp.
-      EH_SJLJ_LONGJMP,
+      // __builtin_longjmp.
+      LIGHTWEIGHT_LONGJMP,
 
       /// Tail call return. See X86TargetLowering::LowerCall for
       /// the list of operands.
       TC_RETURN,
 
       // Vector move to low scalar and zero higher vector elements.
       VZEXT_MOVL,
 
private:
     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
-    SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
-    SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerLIGHTWEIGHT_SETJMP(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerLIGHTWEIGHT_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
 
     SDValue
       LowerFormalArguments(SDValue Chain,
                            CallingConv::ID CallConv, bool isVarArg,
                            const SmallVectorImpl<ISD::InputArg> &Ins,
MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
                                             MachineBasicBlock *BB) const;
 
     MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
                                           MachineBasicBlock *BB) const;
 
     MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
                                           MachineBasicBlock *BB) const;
 
-    MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
+    MachineBasicBlock *emitLightweightSetJmp(MachineInstr *MI,
                                              MachineBasicBlock *MBB) const;
 
-    MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
+    MachineBasicBlock *emitLightweightLongJmp(MachineInstr *MI,
                                               MachineBasicBlock *MBB) const;
 
     MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
                                      MachineBasicBlock *MBB) const;
 
     /// Emit nodes that will be selected as "test Op0,Op0", or something
     /// equivalent, for use with the given x86 condition code.
     SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
                      SelectionDAG &DAG) const;

lib/Target/X86/X86ISelLowering.cpp

X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
   setOperationAction(ISD::SETCC           , MVT::f32  , Custom);
   setOperationAction(ISD::SETCC           , MVT::f64  , Custom);
   setOperationAction(ISD::SETCC           , MVT::f80  , Custom);
   if (Subtarget->is64Bit()) {
     setOperationAction(ISD::SELECT        , MVT::i64  , Custom);
     setOperationAction(ISD::SETCC         , MVT::i64  , Custom);
   }
   setOperationAction(ISD::EH_RETURN       , MVT::Other, Custom);
-  // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
-  // SjLj exception handling but a light-weight setjmp/longjmp replacement to
-  // support continuation, user-level threading, and etc.. As a result, no
-  // other SjLj exception interfaces are implemented and please don't build
-  // your own exception handling based on them.
+  // NOTE: LIGHTWEIGHT_SETJMP/LIGHTWEIGHT_LONGJMP supported here is NOT intended
+  // to support SjLj exception handling but a light-weight setjmp/longjmp
+  // replacement to support continuation, user-level threading, and etc.. As a
+  // result, no other SjLj exception interfaces are implemented and please don't
+  // build your own exception handling based on them.
   // LLVM/Clang supports zero-cost DWARF exception handling.
-  setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
-  setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
+  setOperationAction(ISD::LIGHTWEIGHT_SETJMP, MVT::i32, Custom);
+  setOperationAction(ISD::LIGHTWEIGHT_LONGJMP, MVT::Other, Custom);
 
   // Darwin ABI issue.
   setOperationAction(ISD::ConstantPool    , MVT::i32  , Custom);
   setOperationAction(ISD::JumpTable       , MVT::i32  , Custom);
   setOperationAction(ISD::GlobalAddress   , MVT::i32  , Custom);
   setOperationAction(ISD::GlobalTLSAddress, MVT::i32  , Custom);
   if (Subtarget->is64Bit())
     setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
   Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
                        false, false, 0);
   Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
 
   return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
                      DAG.getRegister(StoreAddrReg, PtrVT));
 }
 
-SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
+SDValue X86TargetLowering::LowerLIGHTWEIGHT_SETJMP(SDValue Op,
                                                SelectionDAG &DAG) const {
   SDLoc DL(Op);
-  return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
+  return DAG.getNode(X86ISD::LIGHTWEIGHT_SETJMP, DL,
                      DAG.getVTList(MVT::i32, MVT::Other),
                      Op.getOperand(0), Op.getOperand(1));
 }
 
-SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
+SDValue X86TargetLowering::LowerLIGHTWEIGHT_LONGJMP(SDValue Op,
                                                 SelectionDAG &DAG) const {
   SDLoc DL(Op);
-  return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
+  return DAG.getNode(X86ISD::LIGHTWEIGHT_LONGJMP, DL, MVT::Other,
                      Op.getOperand(0), Op.getOperand(1));
 }
 
 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
   return Op.getOperand(0);
 }
 
 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::INTRINSIC_VOID:
   case ISD::INTRINSIC_W_CHAIN:  return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
   case ISD::RETURNADDR:         return LowerRETURNADDR(Op, DAG);
   case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG);
   case ISD::FRAME_TO_ARGS_OFFSET:
                                 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
   case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
   case ISD::EH_RETURN:          return LowerEH_RETURN(Op, DAG);
-  case ISD::EH_SJLJ_SETJMP:     return lowerEH_SJLJ_SETJMP(Op, DAG);
-  case ISD::EH_SJLJ_LONGJMP:    return lowerEH_SJLJ_LONGJMP(Op, DAG);
+  case ISD::LIGHTWEIGHT_SETJMP: return LowerLIGHTWEIGHT_SETJMP(Op, DAG);
+  case ISD::LIGHTWEIGHT_LONGJMP:
+                                return LowerLIGHTWEIGHT_LONGJMP(Op, DAG);
   case ISD::INIT_TRAMPOLINE:    return LowerINIT_TRAMPOLINE(Op, DAG);
   case ISD::ADJUST_TRAMPOLINE:  return LowerADJUST_TRAMPOLINE(Op, DAG);
   case ISD::FLT_ROUNDS_:        return LowerFLT_ROUNDS_(Op, DAG);
   case ISD::CTLZ:               return LowerCTLZ(Op, DAG);
   case ISD::CTLZ_ZERO_UNDEF:    return LowerCTLZ_ZERO_UNDEF(Op, DAG);
   case ISD::CTTZ:               return LowerCTTZ(Op, DAG);
   case ISD::MUL:                return LowerMUL(Op, Subtarget, DAG);
   case ISD::UMUL_LOHI:
const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
   case X86ISD::FMIN:               return "X86ISD::FMIN";
   case X86ISD::FMAXC:              return "X86ISD::FMAXC";
   case X86ISD::FMINC:              return "X86ISD::FMINC";
   case X86ISD::FRSQRT:             return "X86ISD::FRSQRT";
   case X86ISD::FRCP:               return "X86ISD::FRCP";
   case X86ISD::TLSADDR:            return "X86ISD::TLSADDR";
   case X86ISD::TLSBASEADDR:        return "X86ISD::TLSBASEADDR";
   case X86ISD::TLSCALL:            return "X86ISD::TLSCALL";
-  case X86ISD::EH_SJLJ_SETJMP:     return "X86ISD::EH_SJLJ_SETJMP";
-  case X86ISD::EH_SJLJ_LONGJMP:    return "X86ISD::EH_SJLJ_LONGJMP";
+  case X86ISD::LIGHTWEIGHT_SETJMP: return "X86ISD::LIGHTWEIGHT_SETJMP";
+  case X86ISD::LIGHTWEIGHT_LONGJMP: return "X86ISD::LIGHTWEIGHT_LONGJMP";
   case X86ISD::EH_RETURN:          return "X86ISD::EH_RETURN";
   case X86ISD::TC_RETURN:          return "X86ISD::TC_RETURN";
   case X86ISD::FNSTCW16m:          return "X86ISD::FNSTCW16m";
   case X86ISD::FNSTSW16r:          return "X86ISD::FNSTSW16r";
   case X86ISD::LCMPXCHG_DAG:       return "X86ISD::LCMPXCHG_DAG";
   case X86ISD::LCMPXCHG8_DAG:      return "X86ISD::LCMPXCHG8_DAG";
   case X86ISD::LCMPXCHG16_DAG:     return "X86ISD::LCMPXCHG16_DAG";
   case X86ISD::VZEXT_MOVL:         return "X86ISD::VZEXT_MOVL";
if (Subtarget->is64Bit()) {
     MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
   }
 
   MI->eraseFromParent(); // The pseudo instruction is gone now.
   return BB;
 }
 
 MachineBasicBlock *
-X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
+X86TargetLowering::emitLightweightSetJmp(MachineInstr *MI,
                                          MachineBasicBlock *MBB) const {
   DebugLoc DL = MI->getDebugLoc();
   MachineFunction *MF = MBB->getParent();
   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
   MachineRegisterInfo &MRI = MF->getRegInfo();
 
   const BasicBlock *BB = MBB->getBasicBlock();
   MachineFunction::iterator I = MBB;
   ++I;
X86TargetLowering::emitLightweightSetJmp(MachineInstr *MI,
   BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
   restoreMBB->addSuccessor(sinkMBB);
 
   MI->eraseFromParent();
   return sinkMBB;
 }
 
 MachineBasicBlock *
-X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
+X86TargetLowering::emitLightweightLongJmp(MachineInstr *MI,
                                           MachineBasicBlock *MBB) const {
   DebugLoc DL = MI->getDebugLoc();
   MachineFunction *MF = MBB->getParent();
   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
   MachineRegisterInfo &MRI = MF->getRegInfo();
 
   // Memory Reference
   MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
   MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
case X86::XBEGIN:
     return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
 
   case X86::VASTART_SAVE_XMM_REGS:
     return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
 
   case X86::VAARG_64:
     return EmitVAARG64WithCustomInserter(MI, BB);
 
-  case X86::EH_SjLj_SetJmp32:
-  case X86::EH_SjLj_SetJmp64:
-    return emitEHSjLjSetJmp(MI, BB);
-
-  case X86::EH_SjLj_LongJmp32:
-  case X86::EH_SjLj_LongJmp64:
-    return emitEHSjLjLongJmp(MI, BB);
+  case X86::Lightweight_SetJmp32:
+  case X86::Lightweight_SetJmp64:
+    return emitLightweightSetJmp(MI, BB);
+
+  case X86::Lightweight_LongJmp32:
+  case X86::Lightweight_LongJmp64:
+    return emitLightweightLongJmp(MI, BB);
 
   case TargetOpcode::STATEPOINT:
     // As an implementation detail, STATEPOINT shares the STACKMAP format at
     // this point in the process.  We diverge later.
     return emitPatchPoint(MI, BB);
 
   case TargetOpcode::STACKMAP:
   case TargetOpcode::PATCHPOINT:

lib/Target/X86/X86InstrCompiler.td

 def EH_RETURN64   : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
                      "ret\t#eh_return, addr: $addr",
                      [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
 
 }
 
 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
     usesCustomInserter = 1 in {
-  def EH_SjLj_SetJmp32  : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
-                            "#EH_SJLJ_SETJMP32",
-                            [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
-                          Requires<[Not64BitMode]>;
-  def EH_SjLj_SetJmp64  : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
-                            "#EH_SJLJ_SETJMP64",
-                            [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
+  def Lightweight_SetJmp32  : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
+                            "#LIGHTWEIGHT_SETJMP32",
+                            [(set GR32:$dst,
+                              (X86lightweight_setjmp addr:$buf))]>,
+                          Requires<[Not64BitMode]>;
+  def Lightweight_SetJmp64  : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
+                            "#LIGHTWEIGHT_SETJMP64",
+                            [(set GR32:$dst,
+                              (X86lightweight_setjmp addr:$buf))]>,
                           Requires<[In64BitMode]>;
   let isTerminator = 1 in {
-  def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
-                            "#EH_SJLJ_LONGJMP32",
-                            [(X86eh_sjlj_longjmp addr:$buf)]>,
-                          Requires<[Not64BitMode]>;
-  def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
-                            "#EH_SJLJ_LONGJMP64",
-                            [(X86eh_sjlj_longjmp addr:$buf)]>,
+  def Lightweight_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
+                            "#LIGHTWEIGHT_LONGJMP32",
+                            [(X86lightweight_longjmp addr:$buf)]>,
+                          Requires<[Not64BitMode]>;
+  def Lightweight_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
+                            "#LIGHTWEIGHT_LONGJMP64",
+                            [(X86lightweight_longjmp addr:$buf)]>,
                           Requires<[In64BitMode]>;
   }
 }
 } // SchedRW
 
 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
   def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
                         "#EH_SjLj_Setup\t$dst", []>;

lib/Target/X86/X86InstrInfo.td

def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 
 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 
 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
                         [SDNPHasChain]>;
 
-def X86eh_sjlj_setjmp  : SDNode<"X86ISD::EH_SJLJ_SETJMP",
+def X86lightweight_setjmp  : SDNode<"X86ISD::LIGHTWEIGHT_SETJMP",
                                 SDTypeProfile<1, 1, [SDTCisInt<0>,
                                                      SDTCisPtrTy<1>]>,
                                 [SDNPHasChain, SDNPSideEffect]>;
-def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
+def X86lightweight_longjmp : SDNode<"X86ISD::LIGHTWEIGHT_LONGJMP",
                                 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
                                 [SDNPHasChain, SDNPSideEffect]>;
 
 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
                         [SDNPHasChain,  SDNPOptInGlue, SDNPVariadic]>;
 
 def X86add_flag  : SDNode<"X86ISD::ADD",  SDTBinaryArithWithFlags,
                           [SDNPCommutative]>;