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Differential D94490

[VE] Update VELIntrinsic tests
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Authored by kaz7 on Jan 12 2021, 4:46 AM.

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Reviewers
simoll
k-ishizaka
Commits
rG24faa87075ac: [VE] Update VELIntrinsic tests
Summary

Update comment and style of regression tests for VELIntrinsic

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Event Timeline

kaz7 requested review of this revision.Jan 12 2021, 4:46 AM
kaz7 created this revision.
Herald added a subscriber: llvm-commits. · View Herald TranscriptJan 12 2021, 4:46 AM
Harbormaster completed remote builds in B84820: Diff 316063.Jan 12 2021, 5:21 AM
simoll accepted this revision.Jan 12 2021, 6:02 AM
This revision is now accepted and ready to land.Jan 12 2021, 6:02 AM
Closed by commit rG24faa87075ac: [VE] Update VELIntrinsic tests (authored by kaz7). · Explain WhyJan 12 2021, 7:13 AM
This revision was automatically updated to reflect the committed changes.
kaz7 added a commit: rG24faa87075ac: [VE] Update VELIntrinsic tests.

Revision Contents

PathSize
llvm/
test/
CodeGen/
VE/
VELIntrinsics/
4 lines
130 lines

Diff 316085

llvm/test/CodeGen/VE/VELIntrinsics/vand.ll

; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s ; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
;;; Test vector and intrinsic instructions ;;; Test vector and intrinsic instructions
;;; ;;;
;;; Note: ;;; Note:
;;; We test VAND*vvl, VAND*vvl_v, VAND*rvl, VAND*rvl_v, VAND*vvml_v, ;;; We test VAND*vvl, VAND*vvl_v, VAND*rvl, VAND*rvl_v, VAND*vvml_v,
;;; VAND*rvml_v, PVAND*vvl, PVAND*vvl_v, PVAND*rvl, PVAND*rvl_v, PVAND*vvml_v, and ;;; VAND*rvml_v, PVAND*vvl, PVAND*vvl_v, PVAND*rvl, PVAND*rvl_v, PVAND*vvml_v,
;;; PVAND*rvml_v instructions. ;;; and PVAND*rvml_v instructions.
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define fastcc <256 x double> @vand_vvvl(<256 x double> %0, <256 x double> %1) { define fastcc <256 x double> @vand_vvvl(<256 x double> %0, <256 x double> %1) {
; CHECK-LABEL: vand_vvvl: ; CHECK-LABEL: vand_vvvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256 ; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0 ; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vand %v0, %v0, %v1 ; CHECK-NEXT: vand %v0, %v0, %v1
▲ Show 20 Lines • Show All 196 Lines • Show Last 20 Lines

llvm/test/CodeGen/VE/VELIntrinsics/vld.ll

; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s ; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
;;; Test vector load intrinsic instructions ;;; Test vector load intrinsic instructions
;;; ;;;
;;; Note: ;;; Note:
;;; We test VLD*rrl, VLD*irl, VLD*rrl_v, VLD*irl_v ;;; We test VLD*rrl, VLD*irl, VLD*rrl_v, and VLD*irl_v instructions.
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld_vssl(i8* %0, i64 %1) { define void @vld_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vld_vssl: ; CHECK-LABEL: vld_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vld.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vld.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld_vssvl(i8* %0, i64 %1, i8* %2) { define void @vld_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vld_vssvl: ; CHECK-LABEL: vld_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vld %v0, %s1, %s2 ; CHECK-NEXT: vld %v0, %s1, %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vld.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vld.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld_vssl_imm(i8* %0) { define void @vld_vssl_imm(i8* %0) {
; CHECK-LABEL: vld_vssl_imm: ; CHECK-LABEL: vld_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld_vssvl_imm(i8* %0, i8* %1) { define void @vld_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vld_vssvl_imm: ; CHECK-LABEL: vld_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, 8, %s1 ; CHECK-NEXT: vld %v0, 8, %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldnc_vssl(i8* %0, i64 %1) { define void @vldnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldnc_vssl: ; CHECK-LABEL: vldnc_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld.nc %v0, %s1, %s0 ; CHECK-NEXT: vld.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldnc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldnc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldnc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldnc_vssvl: ; CHECK-LABEL: vldnc_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vld.nc %v0, %s1, %s2 ; CHECK-NEXT: vld.nc %v0, %s1, %s2
; CHECK-NEXT: vld.nc %v0, %s1, %s0 ; CHECK-NEXT: vld.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldnc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldnc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldnc_vssl_imm(i8* %0) { define void @vldnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vldnc_vssl_imm: ; CHECK-LABEL: vldnc_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld.nc %v0, 8, %s0 ; CHECK-NEXT: vld.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldnc_vssvl_imm(i8* %0, i8* %1) { define void @vldnc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldnc_vssvl_imm: ; CHECK-LABEL: vldnc_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld.nc %v0, 8, %s1 ; CHECK-NEXT: vld.nc %v0, 8, %s1
; CHECK-NEXT: vld.nc %v0, 8, %s0 ; CHECK-NEXT: vld.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu_vssl(i8* %0, i64 %1) { define void @vldu_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldu_vssl: ; CHECK-LABEL: vldu_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu %v0, %s1, %s0 ; CHECK-NEXT: vldu %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldu.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldu.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldu_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldu_vssvl: ; CHECK-LABEL: vldu_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldu %v0, %s1, %s2 ; CHECK-NEXT: vldu %v0, %s1, %s2
; CHECK-NEXT: vldu %v0, %s1, %s0 ; CHECK-NEXT: vldu %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldu.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldu.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu_vssl_imm(i8* %0) { define void @vldu_vssl_imm(i8* %0) {
; CHECK-LABEL: vldu_vssl_imm: ; CHECK-LABEL: vldu_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldu %v0, 8, %s0 ; CHECK-NEXT: vldu %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu_vssvl_imm(i8* %0, i8* %1) { define void @vldu_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldu_vssvl_imm: ; CHECK-LABEL: vldu_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu %v0, 8, %s1 ; CHECK-NEXT: vldu %v0, 8, %s1
; CHECK-NEXT: vldu %v0, 8, %s0 ; CHECK-NEXT: vldu %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldunc_vssl(i8* %0, i64 %1) { define void @vldunc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldunc_vssl: ; CHECK-LABEL: vldunc_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu.nc %v0, %s1, %s0 ; CHECK-NEXT: vldu.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldunc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldunc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldunc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldunc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldunc_vssvl: ; CHECK-LABEL: vldunc_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldu.nc %v0, %s1, %s2 ; CHECK-NEXT: vldu.nc %v0, %s1, %s2
; CHECK-NEXT: vldu.nc %v0, %s1, %s0 ; CHECK-NEXT: vldu.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldunc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldunc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldunc_vssl_imm(i8* %0) { define void @vldunc_vssl_imm(i8* %0) {
; CHECK-LABEL: vldunc_vssl_imm: ; CHECK-LABEL: vldunc_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldu.nc %v0, 8, %s0 ; CHECK-NEXT: vldu.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldunc_vssvl_imm(i8* %0, i8* %1) { define void @vldunc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldunc_vssvl_imm: ; CHECK-LABEL: vldunc_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu.nc %v0, 8, %s1 ; CHECK-NEXT: vldu.nc %v0, 8, %s1
; CHECK-NEXT: vldu.nc %v0, 8, %s0 ; CHECK-NEXT: vldu.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsx_vssl(i8* %0, i64 %1) { define void @vldlsx_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldlsx_vssl: ; CHECK-LABEL: vldlsx_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.sx %v0, %s1, %s0 ; CHECK-NEXT: vldl.sx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlsx.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldlsx.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsx_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldlsx_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldlsx_vssvl: ; CHECK-LABEL: vldlsx_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl.sx %v0, %s1, %s2 ; CHECK-NEXT: vldl.sx %v0, %s1, %s2
; CHECK-NEXT: vldl.sx %v0, %s1, %s0 ; CHECK-NEXT: vldl.sx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsx_vssl_imm(i8* %0) { define void @vldlsx_vssl_imm(i8* %0) {
; CHECK-LABEL: vldlsx_vssl_imm: ; CHECK-LABEL: vldlsx_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl.sx %v0, 8, %s0 ; CHECK-NEXT: vldl.sx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsx_vssvl_imm(i8* %0, i8* %1) { define void @vldlsx_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldlsx_vssvl_imm: ; CHECK-LABEL: vldlsx_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.sx %v0, 8, %s1 ; CHECK-NEXT: vldl.sx %v0, 8, %s1
; CHECK-NEXT: vldl.sx %v0, 8, %s0 ; CHECK-NEXT: vldl.sx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsxnc_vssl(i8* %0, i64 %1) { define void @vldlsxnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldlsxnc_vssl: ; CHECK-LABEL: vldlsxnc_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsxnc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldlsxnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldlsxnc_vssvl: ; CHECK-LABEL: vldlsxnc_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s2 ; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s2
; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsxnc_vssl_imm(i8* %0) { define void @vldlsxnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vldlsxnc_vssl_imm: ; CHECK-LABEL: vldlsxnc_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl.sx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl.sx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsxnc_vssvl_imm(i8* %0, i8* %1) { define void @vldlsxnc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldlsxnc_vssvl_imm: ; CHECK-LABEL: vldlsxnc_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.sx.nc %v0, 8, %s1 ; CHECK-NEXT: vldl.sx.nc %v0, 8, %s1
; CHECK-NEXT: vldl.sx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl.sx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzx_vssl(i8* %0, i64 %1) { define void @vldlzx_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldlzx_vssl: ; CHECK-LABEL: vldlzx_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.zx %v0, %s1, %s0 ; CHECK-NEXT: vldl.zx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlzx.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldlzx.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzx_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldlzx_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldlzx_vssvl: ; CHECK-LABEL: vldlzx_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl.zx %v0, %s1, %s2 ; CHECK-NEXT: vldl.zx %v0, %s1, %s2
; CHECK-NEXT: vldl.zx %v0, %s1, %s0 ; CHECK-NEXT: vldl.zx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzx_vssl_imm(i8* %0) { define void @vldlzx_vssl_imm(i8* %0) {
; CHECK-LABEL: vldlzx_vssl_imm: ; CHECK-LABEL: vldlzx_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl.zx %v0, 8, %s0 ; CHECK-NEXT: vldl.zx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzx_vssvl_imm(i8* %0, i8* %1) { define void @vldlzx_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldlzx_vssvl_imm: ; CHECK-LABEL: vldlzx_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.zx %v0, 8, %s1 ; CHECK-NEXT: vldl.zx %v0, 8, %s1
; CHECK-NEXT: vldl.zx %v0, 8, %s0 ; CHECK-NEXT: vldl.zx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzxnc_vssl(i8* %0, i64 %1) { define void @vldlzxnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldlzxnc_vssl: ; CHECK-LABEL: vldlzxnc_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzxnc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldlzxnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldlzxnc_vssvl: ; CHECK-LABEL: vldlzxnc_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s2 ; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s2
; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzxnc_vssl_imm(i8* %0) { define void @vldlzxnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vldlzxnc_vssl_imm: ; CHECK-LABEL: vldlzxnc_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl.zx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl.zx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzxnc_vssvl_imm(i8* %0, i8* %1) { define void @vldlzxnc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldlzxnc_vssvl_imm: ; CHECK-LABEL: vldlzxnc_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.zx.nc %v0, 8, %s1 ; CHECK-NEXT: vldl.zx.nc %v0, 8, %s1
; CHECK-NEXT: vldl.zx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl.zx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2d_vssl(i8* %0, i64 %1) { define void @vld2d_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vld2d_vssl: ; CHECK-LABEL: vld2d_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld2d %v0, %s1, %s0 ; CHECK-NEXT: vld2d %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vld2d.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vld2d.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2d_vssvl(i8* %0, i64 %1, i8* %2) { define void @vld2d_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vld2d_vssvl: ; CHECK-LABEL: vld2d_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vld2d %v0, %s1, %s2 ; CHECK-NEXT: vld2d %v0, %s1, %s2
; CHECK-NEXT: vld2d %v0, %s1, %s0 ; CHECK-NEXT: vld2d %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vld2d.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vld2d.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2d_vssl_imm(i8* %0) { define void @vld2d_vssl_imm(i8* %0) {
; CHECK-LABEL: vld2d_vssl_imm: ; CHECK-LABEL: vld2d_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld2d %v0, 8, %s0 ; CHECK-NEXT: vld2d %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2d_vssvl_imm(i8* %0, i8* %1) { define void @vld2d_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vld2d_vssvl_imm: ; CHECK-LABEL: vld2d_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld2d %v0, 8, %s1 ; CHECK-NEXT: vld2d %v0, 8, %s1
; CHECK-NEXT: vld2d %v0, 8, %s0 ; CHECK-NEXT: vld2d %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2dnc_vssl(i8* %0, i64 %1) { define void @vld2dnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vld2dnc_vssl: ; CHECK-LABEL: vld2dnc_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld2d.nc %v0, %s1, %s0 ; CHECK-NEXT: vld2d.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2dnc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vld2dnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vld2dnc_vssvl: ; CHECK-LABEL: vld2dnc_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vld2d.nc %v0, %s1, %s2 ; CHECK-NEXT: vld2d.nc %v0, %s1, %s2
; CHECK-NEXT: vld2d.nc %v0, %s1, %s0 ; CHECK-NEXT: vld2d.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2dnc_vssl_imm(i8* %0) { define void @vld2dnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vld2dnc_vssl_imm: ; CHECK-LABEL: vld2dnc_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld2d.nc %v0, 8, %s0 ; CHECK-NEXT: vld2d.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2dnc_vssvl_imm(i8* %0, i8* %1) { define void @vld2dnc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vld2dnc_vssvl_imm: ; CHECK-LABEL: vld2dnc_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld2d.nc %v0, 8, %s1 ; CHECK-NEXT: vld2d.nc %v0, 8, %s1
; CHECK-NEXT: vld2d.nc %v0, 8, %s0 ; CHECK-NEXT: vld2d.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2d_vssl(i8* %0, i64 %1) { define void @vldu2d_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldu2d_vssl: ; CHECK-LABEL: vldu2d_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu2d %v0, %s1, %s0 ; CHECK-NEXT: vldu2d %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldu2d.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldu2d.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2d_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldu2d_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldu2d_vssvl: ; CHECK-LABEL: vldu2d_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldu2d %v0, %s1, %s2 ; CHECK-NEXT: vldu2d %v0, %s1, %s2
; CHECK-NEXT: vldu2d %v0, %s1, %s0 ; CHECK-NEXT: vldu2d %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2d_vssl_imm(i8* %0) { define void @vldu2d_vssl_imm(i8* %0) {
; CHECK-LABEL: vldu2d_vssl_imm: ; CHECK-LABEL: vldu2d_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldu2d %v0, 8, %s0 ; CHECK-NEXT: vldu2d %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2d_vssvl_imm(i8* %0, i8* %1) { define void @vldu2d_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldu2d_vssvl_imm: ; CHECK-LABEL: vldu2d_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu2d %v0, 8, %s1 ; CHECK-NEXT: vldu2d %v0, 8, %s1
; CHECK-NEXT: vldu2d %v0, 8, %s0 ; CHECK-NEXT: vldu2d %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2dnc_vssl(i8* %0, i64 %1) { define void @vldu2dnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldu2dnc_vssl: ; CHECK-LABEL: vldu2dnc_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu2d.nc %v0, %s1, %s0 ; CHECK-NEXT: vldu2d.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2dnc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldu2dnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldu2dnc_vssvl: ; CHECK-LABEL: vldu2dnc_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldu2d.nc %v0, %s1, %s2 ; CHECK-NEXT: vldu2d.nc %v0, %s1, %s2
; CHECK-NEXT: vldu2d.nc %v0, %s1, %s0 ; CHECK-NEXT: vldu2d.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2dnc_vssl_imm(i8* %0) { define void @vldu2dnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vldu2dnc_vssl_imm: ; CHECK-LABEL: vldu2dnc_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldu2d.nc %v0, 8, %s0 ; CHECK-NEXT: vldu2d.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2dnc_vssvl_imm(i8* %0, i8* %1) { define void @vldu2dnc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldu2dnc_vssvl_imm: ; CHECK-LABEL: vldu2dnc_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu2d.nc %v0, 8, %s1 ; CHECK-NEXT: vldu2d.nc %v0, 8, %s1
; CHECK-NEXT: vldu2d.nc %v0, 8, %s0 ; CHECK-NEXT: vldu2d.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsx_vssl(i8* %0, i64 %1) { define void @vldl2dsx_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldl2dsx_vssl: ; CHECK-LABEL: vldl2dsx_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.sx %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.sx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsx_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldl2dsx_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldl2dsx_vssvl: ; CHECK-LABEL: vldl2dsx_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl2d.sx %v0, %s1, %s2 ; CHECK-NEXT: vldl2d.sx %v0, %s1, %s2
; CHECK-NEXT: vldl2d.sx %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.sx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsx_vssl_imm(i8* %0) { define void @vldl2dsx_vssl_imm(i8* %0) {
; CHECK-LABEL: vldl2dsx_vssl_imm: ; CHECK-LABEL: vldl2dsx_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl2d.sx %v0, 8, %s0 ; CHECK-NEXT: vldl2d.sx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsx_vssvl_imm(i8* %0, i8* %1) { define void @vldl2dsx_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldl2dsx_vssvl_imm: ; CHECK-LABEL: vldl2dsx_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.sx %v0, 8, %s1 ; CHECK-NEXT: vldl2d.sx %v0, 8, %s1
; CHECK-NEXT: vldl2d.sx %v0, 8, %s0 ; CHECK-NEXT: vldl2d.sx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsxnc_vssl(i8* %0, i64 %1) { define void @vldl2dsxnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldl2dsxnc_vssl: ; CHECK-LABEL: vldl2dsxnc_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsxnc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldl2dsxnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldl2dsxnc_vssvl: ; CHECK-LABEL: vldl2dsxnc_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s2 ; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s2
; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsxnc_vssl_imm(i8* %0) { define void @vldl2dsxnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vldl2dsxnc_vssl_imm: ; CHECK-LABEL: vldl2dsxnc_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsxnc_vssvl_imm(i8* %0, i8* %1) { define void @vldl2dsxnc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldl2dsxnc_vssvl_imm: ; CHECK-LABEL: vldl2dsxnc_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s1 ; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s1
; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzx_vssl(i8* %0, i64 %1) { define void @vldl2dzx_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldl2dzx_vssl: ; CHECK-LABEL: vldl2dzx_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.zx %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.zx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzx_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldl2dzx_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldl2dzx_vssvl: ; CHECK-LABEL: vldl2dzx_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl2d.zx %v0, %s1, %s2 ; CHECK-NEXT: vldl2d.zx %v0, %s1, %s2
; CHECK-NEXT: vldl2d.zx %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.zx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzx_vssl_imm(i8* %0) { define void @vldl2dzx_vssl_imm(i8* %0) {
; CHECK-LABEL: vldl2dzx_vssl_imm: ; CHECK-LABEL: vldl2dzx_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl2d.zx %v0, 8, %s0 ; CHECK-NEXT: vldl2d.zx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzx_vssvl_imm(i8* %0, i8* %1) { define void @vldl2dzx_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldl2dzx_vssvl_imm: ; CHECK-LABEL: vldl2dzx_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.zx %v0, 8, %s1 ; CHECK-NEXT: vldl2d.zx %v0, 8, %s1
; CHECK-NEXT: vldl2d.zx %v0, 8, %s0 ; CHECK-NEXT: vldl2d.zx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzxnc_vssl(i8* %0, i64 %1) { define void @vldl2dzxnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldl2dzxnc_vssl: ; CHECK-LABEL: vldl2dzxnc_vssl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzxnc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldl2dzxnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldl2dzxnc_vssvl: ; CHECK-LABEL: vldl2dzxnc_vssvl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s2 ; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s2
; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, i8* %0, i64 %1)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzxnc_vssl_imm(i8* %0) { define void @vldl2dzxnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vldl2dzxnc_vssl_imm: ; CHECK-LABEL: vldl2dzxnc_vssl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzxnc_vssvl_imm(i8* %0, i8* %1) { define void @vldl2dzxnc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldl2dzxnc_vssvl_imm: ; CHECK-LABEL: vldl2dzxnc_vssvl_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s1 ; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s1
; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }