[VE] Support vector register in inline asm

[kaz7]

Summary

Support a vector register constraint in inline asm of clang.
Add a regression test also.

clang/lib/Basic/Targets/VE.h

static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
         {{"s62"}, "sx62"},
         {{"s63"}, "sx63"},
     };
     return llvm::makeArrayRef(GCCRegAliases);
   }
 
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &Info) const override {
+    switch (*Name) {
+    default:
+      return false;
+    case 'v':
+      Info.setAllowsRegister();
+      return true;
+    }
     return false;
   }
 
   bool allowsLargerPreferedTypeAlignment() const override { return false; }
 };
 } // namespace targets
 } // namespace clang
 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_VE_H

clang/test/CodeGen/VE/ve-inline-asm.c

+// REQUIRES: ve-registered-target
+// RUN: %clang_cc1 -triple ve-linux-gnu -emit-llvm -o - %s | FileCheck %s
+
+void r(long v) {
+  long b;
+  asm("lea %0, 256(%1)"
+      : "=r"(b)
+      : "r"(v));
+  // CHECK: %1 = call i64 asm "lea $0, 256($1)", "=r,r"(i64 %0)
+}
+
+void v(char *ptr, char *ptr2) {
+  typedef double __vr __attribute__((__vector_size__(2048)));
+  __vr a;
+  asm("vld %0, 8, %1"
+      : "=v"(a)
+      : "r"(ptr));
+  asm("vst %0, 8, %1"
+      :
+      : "v"(a), "r"(ptr2));
+  // CHECK: %1 = call <256 x double> asm "vld $0, 8, $1", "=v,r"(i8* %0)
+  // CHECK: call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %3)
+}