[SystemZAsmParser] Treat VR128 separately in ParseDirectiveInsn().

[jonpa]

Summary

Since vector registers require an extra bit of encoding they should not be part of the AnyReg register class together with the GPR and FP registers, so they are removed.

This patch makes the parser

• reject higher vector registers (>=16) in operands where they should not be accepted.
• accept higher integers (>=16) in vector register operands.

[uweigand]

See inline comment. Otherwise LGTM.

llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

127 ↗

(On Diff #296412)

Given that we want to allow %v0..%v15 (just not %v16..%v31), I think the old definition actually was correct.

llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

/* Format, Opcode, NumOperands, OperandKinds */
     { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
   { "ss", SystemZ::InsnSS, 4,
     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
   { "sse", SystemZ::InsnSSE, 3,
     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
   { "ssf", SystemZ::InsnSSF, 4,
     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
   { "vri", SystemZ::InsnVRI, 6,
-    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
+    { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
   { "vrr", SystemZ::InsnVRR, 7,
-    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_U4Imm,
+    { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
       MCK_U4Imm } },
   { "vrs", SystemZ::InsnVRS, 5,
-    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_U4Imm } },
+    { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } },
   { "vrv", SystemZ::InsnVRV, 4,
-    { MCK_U48Imm, MCK_AnyReg, MCK_BDVAddr64Disp12, MCK_U4Imm } },
+    { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } },
   { "vrx", SystemZ::InsnVRX, 4,
-    { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12, MCK_U4Imm } },
+    { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } },
   { "vsi", SystemZ::InsnVSI, 4,
-    { MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_U8Imm } }
+    { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } }
 };
 
 static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
   if (!E)
     return;
   if (auto *CE = dyn_cast<MCConstantExpr>(E))
     OS << *CE;
   else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
   Operands.push_back(
       SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
   return MatchOperand_Success;
 }
 
 // Parse any type of register (including integers) and add it to Operands.
 OperandMatchResultTy
 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
+  SMLoc StartLoc = Parser.getTok().getLoc();
+
   // Handle integer values.
   if (Parser.getTok().is(AsmToken::Integer)) {
     const MCExpr *Register;
-    SMLoc StartLoc = Parser.getTok().getLoc();
     if (Parser.parseExpression(Register))
       return MatchOperand_ParseFail;
 
     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
       int64_t Value = CE->getValue();
       if (Value < 0 || Value > 15) {
         Error(StartLoc, "invalid register");
         return MatchOperand_ParseFail;
       }
     }
 
     SMLoc EndLoc =
       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
 
     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
   }
   else {
     Register Reg;
     if (parseRegister(Reg))
       return MatchOperand_ParseFail;
 
+    if (Reg.Num > 15) {
+      Error(StartLoc, "invalid register");
+      return MatchOperand_ParseFail;
+    }
+
     // Map to the correct register kind.
     RegisterKind Kind;
     unsigned RegNo;
     if (Reg.Group == RegGR) {
       Kind = GR64Reg;
       RegNo = SystemZMC::GR64Regs[Reg.Num];
     }
     else if (Reg.Group == RegFP) {
for (int i = 0; i < Entry->NumOperands; i++) {
     if (getLexer().isNot(AsmToken::Comma))
       return Error(StartLoc, "unexpected token in directive");
     Lex();
 
     // Parse operands.
     OperandMatchResultTy ResTy;
     if (Kind == MCK_AnyReg)
       ResTy = parseAnyReg(Operands);
+    else if (Kind == MCK_VR128)
+      ResTy = parseVR128(Operands);
     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
       ResTy = parseBDXAddr64(Operands);
     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
       ResTy = parseBDAddr64(Operands);
     else if (Kind == MCK_BDVAddr64Disp12)
       ResTy = parseBDVAddr64(Operands);
     else if (Kind == MCK_PCRel32)
       ResTy = parsePCRel32(Operands);

llvm/test/MC/SystemZ/directive-insn-vector.s

 #CHECK: e7 37 00 00 00 56     vlr     %v3, %v7
   .insn vrr,0xe70000000056,%v3,%v7,0,0,0,0
 #CHECK: e7 37 60 18 30 eb     wfchdbs %f3, %f7, %f6
   .insn vrr,0xe700000000eb,%v3,%v7,%v6,3,8,1
 
 #CHECK: e6 0c 20 0c 01 35     vlrl    %v16, 12(%r2), 12
   .insn vsi,0xe60000000035,%v16,12(%r2),12
 
+#CHECK: e7 01 00 00 0c 56     vlr     %v16, %v17
+ .insn vrr,0xe70000000056,16,17,0,0,0,0

llvm/test/MC/SystemZ/regs-bad.s

#CHECK: lxr %f0,0(%r1)
   lxr %a0,%f1
   lxr %c0,%f1
   lxr %f0,%r1
   lxr %f0,%a1
   lxr %f0,%c1
   lxr %f0,16
   lxr %f0,0(%r1)
 
+# Test that a high (>=16) vector register is not accepted in a non-vector
+# operand.
+#
+#CHECK: error: invalid register
+#CHECK: .insn rr,0x1800,%v16,%v0
+.insn rr,0x1800,%v16,%v0
+
 # Test access register operands
 #
 #CHECK: error: invalid operand for instruction
 #CHECK: ear %r0,%r0
 #CHECK: error: invalid operand for instruction
 #CHECK: ear %r0,%f0
 #CHECK: error: invalid operand for instruction
 #CHECK: ear %r0,%c0