Add support for the Sparc implementation-defined "ASR" registers.

[jyknight]

Summary

(Note that register "Y" is essentially just ASR0).

Also added some test cases for divide and multiply, which had none before.

[echristo]

Testcase?

-eric

[jyknight]

In D8670#148078, @echristo wrote:

Testcase?

I'd love to, but I couldn't find any tests that test anything like this to copy. (I might be just blind). Can you point me to something I can riff off of?

[echristo]

This looks like something that comes from inline assembly, perhaps write some inline assembly in clang, emit llvm IR, copy it to test/CodeGen/Sparc, and make sure we can assemble it? Otherwise if you just want plain assembly you can look at the tests in test/MC/.

-eric

[jyknight]

Thanks for the hint, added a test now. Somehow I completely missed the "test" directory. I'd seen "unittest", and looked in there (where of course there's not anything related to this), and never went back up to find another dir. :)

[venkatra]

Can you also test 'rd %asr15, %g0' instruction? This instruction aliases the 'stbar' instruction.

[jyknight]

Added test as requested. Also added some Disassembler tests, including ensuring that stbar is still preferred for disassembly instead of the equivalent rd.

[venkatra]

LGTM

[jyknight]

In D8670#150197, @venkatra wrote:

LGTM

Thanks! This is my first submission, so I do not have a commit account yet. I understand the thing to do now is ask if you could please commit it for me?

[jyknight]

Actually don't commit yet...this seems to cause a new segfault when compiling some programs, and I need to track down why that'd be...

[jyknight]

Fixed the code, I hope correctly.

[jyknight]

Ping.

[jyknight]

Ping

[echristo]

What was the bug you fixed when it was causing crashes?

-eric

[jyknight]

In D8670#167209, @echristo wrote:

What was the bug you fixed when it was causing crashes?

I had not correctly updated SparcISelDAGToDAG.cpp, so div simply did not work at all.

It was this patch of my patch:

--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -166,10 +166,10 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
     } else {
       TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
     }
-    TopPart = SDValue(CurDAG->getMachineNode(SP::WRASRrr, dl, MVT::Glue,
-                                 CurDAG->getRegister(SP::Y, MVT::i32),
+    TopPart = SDValue(CurDAG->getMachineNode(SP::WRASRrr, dl, MVT::i32,
                                  TopPart,
                                  CurDAG->getRegister(SP::G0, MVT::i32)), 0);
+    TopPart = CurDAG->getCopyToReg(TopPart, dl, SP::Y, TopPart, SDValue()).getValue(1);

[jyknight]

ping

[echristo]

Since it's just a bug fix on top of the existing code that already was LGTM'd this is fine.

Sorry for the delay.

Thanks!

-eric

lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

static unsigned DoubleRegs[32] = {
     Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
 
   static unsigned QuadFPRegs[32] = {
     Sparc::Q0,  Sparc::Q1,  Sparc::Q2,  Sparc::Q3,
     Sparc::Q4,  Sparc::Q5,  Sparc::Q6,  Sparc::Q7,
     Sparc::Q8,  Sparc::Q9,  Sparc::Q10, Sparc::Q11,
     Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
 
+  static unsigned ASRRegs[32] = {
+    SP::Y,     SP::ASR1,  SP::ASR2,  SP::ASR3,
+    SP::ASR4,  SP::ASR5,  SP::ASR6, SP::ASR7,
+    SP::ASR8,  SP::ASR9,  SP::ASR10, SP::ASR11,
+    SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
+    SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
+    SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
+    SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
+    SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
 
 /// SparcOperand - Instances of this class represent a parsed Sparc machine
 /// instruction.
 class SparcOperand : public MCParsedAsmOperand {
 public:
   enum RegisterKind {
     rk_None,
     rk_IntReg,
     rk_FloatReg,
     rk_DoubleReg,
     rk_QuadReg,
     rk_CCReg,
-    rk_Y
+    rk_ASRReg
   };
 private:
   enum KindTy {
     k_Token,
     k_Register,
     k_Immediate,
     k_MemoryReg,
     k_MemoryImm
case AsmToken::Percent:
     if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
       StringRef name = Parser.getTok().getString();
       Parser.Lex(); // Eat the identifier token.
       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
       switch (RegNo) {
       default:
         Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
         break;
-      case Sparc::Y:
-        Op = SparcOperand::CreateToken("%y", S);
-        break;
 
       case Sparc::ICC:
         if (name == "xcc")
           Op = SparcOperand::CreateToken("%xcc", S);
         else
           Op = SparcOperand::CreateToken("%icc", S);
         break;
       }
if (Tok.is(AsmToken::Identifier)) {
     if (name.equals("sp")) {
       RegNo = Sparc::O6;
       RegKind = SparcOperand::rk_IntReg;
       return true;
     }
 
     if (name.equals("y")) {
       RegNo = Sparc::Y;
-      RegKind = SparcOperand::rk_Y;
+      RegKind = SparcOperand::rk_ASRReg;
+      return true;
+    }
+
+    if (name.substr(0, 3).equals_lower("asr")
+        && !name.substr(3).getAsInteger(10, intVal)
+        && intVal > 0 && intVal < 32) {
+      RegNo = ASRRegs[intVal];
+      RegKind = SparcOperand::rk_ASRReg;
       return true;
     }
 
     if (name.equals("icc")) {
       RegNo = Sparc::ICC;
       RegKind = SparcOperand::rk_CCReg;
       return true;
     }

lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

static const unsigned QFPRegDecoderTable[] = {
   SP::Q4,  SP::Q12,  ~0U,  ~0U,
   SP::Q5,  SP::Q13,  ~0U,  ~0U,
   SP::Q6,  SP::Q14,  ~0U,  ~0U,
   SP::Q7,  SP::Q15,  ~0U,  ~0U } ;
 
 static const unsigned FCCRegDecoderTable[] = {
   SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
 
+static const unsigned ASRRegDecoderTable[] = {
+  SP::Y,     SP::ASR1,  SP::ASR2,  SP::ASR3,
+  SP::ASR4,  SP::ASR5,  SP::ASR6,  SP::ASR7,
+  SP::ASR8,  SP::ASR9,  SP::ASR10, SP::ASR11,
+  SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
+  SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
+  SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
+  SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
+  SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
+
 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
                                                unsigned RegNo,
                                                uint64_t Address,
                                                const void *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
   unsigned Reg = IntRegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::CreateReg(Reg));
static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
                                                const void *Decoder) {
   if (RegNo > 3)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+  Inst.addOperand(MCOperand::CreateReg(ASRRegDecoderTable[RegNo]));
+  return MCDisassembler::Success;
+}
+
 
 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder);
 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
                                  const void *Decoder);
 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
                                   const void *Decoder);
 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,

lib/Target/Sparc/SparcISelDAGToDAG.cpp

case ISD::UDIV: {
     // Set the Y register to the high-part.
     SDValue TopPart;
     if (N->getOpcode() == ISD::SDIV) {
       TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
                                    CurDAG->getTargetConstant(31, MVT::i32)), 0);
     } else {
       TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
     }
-    TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart,
-                                     CurDAG->getRegister(SP::G0, MVT::i32)), 0);
+    TopPart = SDValue(CurDAG->getMachineNode(SP::WRASRrr, dl, MVT::i32,
+                                 TopPart,
+    TopPart = CurDAG->getCopyToReg(TopPart, dl, SP::Y, TopPart, SDValue()).getValue(1);
 
     // FIXME: Handle div by immediate.
     unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
     return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
                                 TopPart);
   }
   case ISD::MULHU:
   case ISD::MULHS: {
     // FIXME: Handle mul by immediate.
     SDValue MulLHS = N->getOperand(0);
     SDValue MulRHS = N->getOperand(1);
     unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
     SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
                                          MulLHS, MulRHS);
     // The high part is in the Y register.
-    return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
+    return CurDAG->SelectNodeTo(N, SP::RDASR, MVT::i32,
+                                CurDAG->getRegister(SP::Y, MVT::i32),
+                                SDValue(Mul, 1));
   }
   }
 
   return SelectCode(N);
 }
 
 
 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for

lib/Target/Sparc/SparcInstrInfo.td

let isCodeGenOnly = 1, rd = 15 in {
     def CALLri : F3_2<2, 0b111000,
                       (outs), (ins MEMri:$ptr, variable_ops),
                       "call $ptr",
                       [(call ADDRri:$ptr)]>;
   }
 }
 
 // Section B.28 - Read State Register Instructions
-let Uses = [Y], rs1 = 0, rs2 = 0 in
-  def RDY : F3_1<2, 0b101000,
-                 (outs IntRegs:$dst), (ins),
-                 "rd %y, $dst", []>;
+let rs2 = 0 in
+  def RDASR : F3_1<2, 0b101000,
+                 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
+                 "rd $rs1, $rd", []>;
 
 // Section B.29 - Write State Register Instructions
-let Defs = [Y], rd = 0 in {
-  def WRYrr : F3_1<2, 0b110000,
-                   (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
-                   "wr $rs1, $rs2, %y", []>;
-  def WRYri : F3_2<2, 0b110000,
-                   (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
-                   "wr $rs1, $simm13, %y", []>;
-}
+def WRASRrr : F3_1<2, 0b110000,
+                 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
+                 "wr $rs1, $rs2, $rd", []>;
+def WRASRri : F3_2<2, 0b110000,
+                 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
+                 "wr $rs1, $simm13, $rd", []>;
+
 // Convert Integer to Floating-point Instructions, p. 141
 def FITOS : F3_3u<2, 0b110100, 0b011000100,
                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
                  "fitos $rs2, $rd",
                  [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
 def FITOD : F3_3u<2, 0b110100, 0b011001000,
                  (outs DFPRegs:$rd), (ins FPRegs:$rs2),
                  "fitod $rs2, $rd",

lib/Target/Sparc/SparcRegisterInfo.td

 
 // Control Registers
 def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
 foreach I = 0-3 in
   def FCC#I : SparcCtrlReg<I, "FCC"#I>;
 
 // Y register
 def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
+// Ancillary state registers (implementation defined)
+def ASR1 : SparcCtrlReg<1, "ASR1">;
+def ASR2 : SparcCtrlReg<2, "ASR2">;
+def ASR3 : SparcCtrlReg<3, "ASR3">;
+def ASR4 : SparcCtrlReg<4, "ASR4">;
+def ASR5 : SparcCtrlReg<5, "ASR5">;
+def ASR6 : SparcCtrlReg<6, "ASR6">;
+def ASR7 : SparcCtrlReg<7, "ASR7">;
+def ASR8 : SparcCtrlReg<8, "ASR8">;
+def ASR9 : SparcCtrlReg<9, "ASR9">;
+def ASR10 : SparcCtrlReg<10, "ASR10">;
+def ASR11 : SparcCtrlReg<11, "ASR11">;
+def ASR12 : SparcCtrlReg<12, "ASR12">;
+def ASR13 : SparcCtrlReg<13, "ASR13">;
+def ASR14 : SparcCtrlReg<14, "ASR14">;
+def ASR15 : SparcCtrlReg<15, "ASR15">;
+def ASR16 : SparcCtrlReg<16, "ASR16">;
+def ASR17 : SparcCtrlReg<17, "ASR17">;
+def ASR18 : SparcCtrlReg<18, "ASR18">;
+def ASR19 : SparcCtrlReg<19, "ASR19">;
+def ASR20 : SparcCtrlReg<20, "ASR20">;
+def ASR21 : SparcCtrlReg<21, "ASR21">;
+def ASR22 : SparcCtrlReg<22, "ASR22">;
+def ASR23 : SparcCtrlReg<23, "ASR23">;
+def ASR24 : SparcCtrlReg<24, "ASR24">;
+def ASR25 : SparcCtrlReg<25, "ASR25">;
+def ASR26 : SparcCtrlReg<26, "ASR26">;
+def ASR27 : SparcCtrlReg<27, "ASR27">;
+def ASR28 : SparcCtrlReg<28, "ASR28">;
+def ASR29 : SparcCtrlReg<29, "ASR29">;
+def ASR30 : SparcCtrlReg<30, "ASR30">;
+def ASR31 : SparcCtrlReg<31, "ASR31">;
 
 // Integer registers
 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;

 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
 
 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>;
 
 def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;
 
 // Floating point control register classes.
 def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;
+
+// Ancillary state registers
+def ASRRegs : RegisterClass<"SP", [i32], 32,
+                            (add Y, (sequence "ASR%u", 1, 31))>;

test/CodeGen/SPARC/basictest.ll

 define i32 @store_zero(i32* %a, i32* %b) {
 entry:
   store i32 0, i32* %a, align 4
   %0 = getelementptr inbounds i32, i32* %b, i32 1
   store i32 0, i32* %0, align 4
   ret i32 0
 }
 
+; CHECK-LABEL: signed_divide:
+; CHECK: sra %o0, 31, %o2
+; CHECK: wr %o2, %g0, %y
+; CHECK: sdiv %o0, %o1, %o0
+define i32 @signed_divide(i32 %a, i32 %b) {
+  %r = sdiv i32 %a, %b
+  ret i32 %r
+}
+
+; CHECK-LABEL: unsigned_divide:
+; CHECK: wr %g0, %g0, %y
+; CHECK: udiv %o0, %o1, %o0
+define i32 @unsigned_divide(i32 %a, i32 %b) {
+  %r = udiv i32 %a, %b
+  ret i32 %r
+}
+
+; CHECK-LABEL: multiply_32x32:
+; CHECK: smul %o0, %o1, %o0
+define i32 @multiply_32x32(i32 %a, i32 %b) {
+  %r = mul i32 %a, %b
+  ret i32 %r
+}
+
+; CHECK-LABEL: signed_multiply_32x32_64:
+; CHECK: smul %o0, %o1, %o1
+; CHECK: rd %y, %o0
+define i64 @signed_multiply_32x32_64(i32 %a, i32 %b) {
+  %xa = sext i32 %a to i64
+  %xb = sext i32 %b to i64
+  %r = mul i64 %xa, %xb
+  ret i64 %r
+}
+
+; CHECK-LABEL: unsigned_multiply_32x32_64:
+; CHECK: umul %o0, %o1, %o2
+; CHECK: rd %y, %o2
+;FIXME: the smul in the output is totally redundant and should not there.
+; CHECK: smul %o0, %o1, %o1
+; CHECK: retl
+; CHECK: mov      %o2, %o0
+define i64 @unsigned_multiply_32x32_64(i32 %a, i32 %b) {
+  %xa = zext i32 %a to i64
+  %xb = zext i32 %b to i64
+  %r = mul i64 %xa, %xb
+  ret i64 %r
+}
+

test/MC/Disassembler/Sparc/sparc.txt

 # CHECK: retl
 0x81 0xc3 0xe0 0x08
 
 # CHECK: ret
 0x81,0xc7,0xe0,0x08
 
 # CHECK:  rett %i7+8
 0x81 0xcf 0xe0 0x08
+
+# CHECK: rd %y, %i0
+0xb1 0x40 0x00 0x00
+
+# CHECK: rd %asr1, %i0
+0xb1 0x40 0x40 0x00
+
+# CHECK: wr %i0, 5, %y
+0x81 0x86 0x20 0x05
+
+# CHECK: wr %i0, %i1, %asr15
+0x9f 0x86 0x00 0x19
+
+# CHECK: stbar
+0x81 0x43 0xc0 0x00

test/MC/Sparc/sparc-special-registers.s

+! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
+
+        ! CHECK: rd %y, %i0            ! encoding: [0xb1,0x40,0x00,0x00]
+        rd %y, %i0
+
+        ! CHECK: rd %asr1, %i0         ! encoding: [0xb1,0x40,0x40,0x00]
+        rd %asr1, %i0
+
+        ! CHECK: wr %i0, 5, %y         ! encoding: [0x81,0x86,0x20,0x05]
+        wr %i0, 5, %y
+
+        ! CHECK: wr %i0, %i1, %asr15   ! encoding: [0x9f,0x86,0x00,0x19]
+        wr %i0, %i1, %asr15
+
+        ! CHECK: rd %asr15, %g0        ! encoding: [0x81,0x43,0xc0,0x00]
+        rd %asr15, %g0