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Add support for the Sparc implementation-defined "ASR" registers.
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Authored by jyknight on Mar 27 2015, 1:35 PM.

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(Note that register "Y" is essentially just ASR0).

Also added some test cases for divide and multiply, which had none before.

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rL LLVM

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jyknight updated this revision to Diff 22812.Mar 27 2015, 1:35 PM
jyknight retitled this revision from to Add support for the Sparc implementation-defined "ASR" registers..
jyknight updated this object.
jyknight edited the test plan for this revision. (Show Details)
jyknight set the repository for this revision to rL LLVM.
jyknight added a subscriber: Unknown Object (MLST).
jyknight updated this revision to Diff 22818.Mar 27 2015, 1:41 PM

Testcase?

-eric

Testcase?

I'd love to, but I couldn't find any tests that test anything like this to copy. (I might be just blind). Can you point me to something I can riff off of?

This looks like something that comes from inline assembly, perhaps write some inline assembly in clang, emit llvm IR, copy it to test/CodeGen/Sparc, and make sure we can assemble it? Otherwise if you just want plain assembly you can look at the tests in test/MC/.

-eric

jyknight updated this revision to Diff 22828.Mar 27 2015, 3:12 PM

Thanks for the hint, added a test now. Somehow I completely missed the "test" directory. I'd seen "unittest", and looked in there (where of course there's not anything related to this), and never went back up to find another dir. :)

Can you also test 'rd %asr15, %g0' instruction? This instruction aliases the 'stbar' instruction.

jyknight updated this revision to Diff 22890.Mar 30 2015, 8:25 AM

Added test as requested. Also added some Disassembler tests, including ensuring that stbar is still preferred for disassembly instead of the equivalent rd.

LGTM

Thanks! This is my first submission, so I do not have a commit account yet. I understand the thing to do now is ask if you could please commit it for me?

Actually don't commit yet...this seems to cause a new segfault when compiling some programs, and I need to track down why that'd be...

jyknight updated this revision to Diff 23395.Apr 7 2015, 9:55 PM
jyknight updated this object.
jyknight removed rL LLVM as the repository for this revision.

Fixed the code, I hope correctly.

What was the bug you fixed when it was causing crashes?

-eric

What was the bug you fixed when it was causing crashes?

I had not correctly updated SparcISelDAGToDAG.cpp, so div simply did not work at all.

It was this patch of my patch:

--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -166,10 +166,10 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
     } else {
       TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
     }
-    TopPart = SDValue(CurDAG->getMachineNode(SP::WRASRrr, dl, MVT::Glue,
-                                 CurDAG->getRegister(SP::Y, MVT::i32),
+    TopPart = SDValue(CurDAG->getMachineNode(SP::WRASRrr, dl, MVT::i32,
                                  TopPart,
                                  CurDAG->getRegister(SP::G0, MVT::i32)), 0);
+    TopPart = CurDAG->getCopyToReg(TopPart, dl, SP::Y, TopPart, SDValue()).getValue(1);
echristo accepted this revision.May 13 2015, 2:57 PM
echristo added a reviewer: echristo.

Since it's just a bug fix on top of the existing code that already was LGTM'd this is fine.

Sorry for the delay.

Thanks!

-eric

This revision is now accepted and ready to land.May 13 2015, 2:57 PM
This revision was automatically updated to reflect the committed changes.