[ADT] Expand llvm::PointerSumType to support scoped enum tags.

[idan]

Summary

Removes constraint that TagT must be implicitly castable to uintptr_t. The intent is to use this in TFRT.

[idan]

clang-tidy fixes

llvm/include/llvm/ADT/PointerSumType.h

 //===- llvm/ADT/PointerSumType.h --------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_ADT_POINTERSUMTYPE_H
 #define LLVM_ADT_POINTERSUMTYPE_H
 
-#include "llvm/ADT/bit.h"
 #include "llvm/ADT/DenseMapInfo.h"
+#include "llvm/ADT/bit.h"
 #include "llvm/Support/PointerLikeTypeTraits.h"
 #include <cassert>
 #include <cstdint>
 #include <type_traits>
 
 namespace llvm {
 
 /// A compile time pair of an integer tag and the pointer-like type which it
 /// indexes within a sum type. Also allows the user to specify a particular
 /// traits class for pointer types with custom behavior such as over-aligned
 /// allocation.
-template <uintptr_t N, typename PointerArgT,
+template <typename TagT, TagT N, typename PointerArgT,
           typename TraitsArgT = PointerLikeTypeTraits<PointerArgT>>
 struct PointerSumTypeMember {
-  enum { Tag = N };
+  static_assert(std::is_integral<TagT>::value || std::is_enum<TagT>::value,
+                "Tag type must be integral");
+
+  static constexpr TagT Tag = N;
   using PointerT = PointerArgT;
   using TraitsT = TraitsArgT;
 };
 
 namespace detail {
 
 template <typename TagT, typename... MemberTs> struct PointerSumTypeHelper;
 
public:
   constexpr PointerSumType() = default;
 
   /// A typed setter to a given tagged member of the sum type.
   template <TagT N>
   void set(typename HelperT::template Lookup<N>::PointerT Pointer) {
     void *V = HelperT::template Lookup<N>::TraitsT::getAsVoidPointer(Pointer);
     assert((reinterpret_cast<uintptr_t>(V) & HelperT::TagMask) == 0 &&
            "Pointer is insufficiently aligned to store the discriminant!");
-    Storage.Value = reinterpret_cast<uintptr_t>(V) | N;
+    Storage.Value = reinterpret_cast<uintptr_t>(V) | static_cast<uintptr_t>(N);
   }
 
   /// A typed constructor for a specific tagged member of the sum type.
   template <TagT N>
   static PointerSumType
   create(typename HelperT::template Lookup<N>::PointerT Pointer) {
     PointerSumType Result;
     Result.set<N>(Pointer);

 template <typename TagT, typename... MemberTs>
 struct PointerSumTypeHelper : MemberTs... {
   // First we use a trick to allow quickly looking up information about
   // a particular member of the sum type. This works because we arranged to
   // have this type derive from all of the member type templates. We can select
   // the matching member for a tag using type deduction during overload
   // resolution.
   template <TagT N, typename PointerT, typename TraitsT>
-  static PointerSumTypeMember<N, PointerT, TraitsT>
-  LookupOverload(PointerSumTypeMember<N, PointerT, TraitsT> *);
-  template <TagT N> static void LookupOverload(...);
+  static PointerSumTypeMember<TagT, N, PointerT, TraitsT>
+  lookupOverload(PointerSumTypeMember<TagT, N, PointerT, TraitsT> *);
+  template <TagT N> static void lookupOverload(...);
   template <TagT N> struct Lookup {
     // Compute a particular member type by resolving the lookup helper overload.
     using MemberT = decltype(
-        LookupOverload<N>(static_cast<PointerSumTypeHelper *>(nullptr)));
+        lookupOverload<N>(static_cast<PointerSumTypeHelper *>(nullptr)));
 
     /// The Nth member's pointer type.
     using PointerT = typename MemberT::PointerT;
 
     /// The Nth member's traits type.
     using TraitsT = typename MemberT::TraitsT;
   };
 
   // Next we need to compute the number of bits available for the discriminant
   // by taking the min of the bits available for each member. Much of this
   // would be amazingly easier with good constexpr support.
   template <uintptr_t V, uintptr_t... Vs>
   struct Min : std::integral_constant<
                    uintptr_t, (V < Min<Vs...>::value ? V : Min<Vs...>::value)> {
   };
   template <uintptr_t V>
   struct Min<V> : std::integral_constant<uintptr_t, V> {};
   enum { NumTagBits = Min<MemberTs::TraitsT::NumLowBitsAvailable...>::value };
 
   // Also compute the smallest discriminant and various masks for convenience.
   constexpr static TagT MinTag =
-      static_cast<TagT>(Min<MemberTs::Tag...>::value);
+      static_cast<TagT>(Min<static_cast<uintptr_t>(MemberTs::Tag)...>::value);
   enum : uint64_t {
     PointerMask = static_cast<uint64_t>(-1) << NumTagBits,
     TagMask = ~PointerMask
   };
 
   // Finally we need a recursive template to do static checks of each
   // member.
   template <typename MemberT, typename... InnerMemberTs>
   struct Checker : Checker<InnerMemberTs...> {
-    static_assert(MemberT::Tag < (1 << NumTagBits),
+    static_assert(static_cast<uint64_t>(MemberT::Tag) < (1 << NumTagBits),
                   "This discriminant value requires too many bits!");
   };
   template <typename MemberT> struct Checker<MemberT> : std::true_type {
-    static_assert(MemberT::Tag < (1 << NumTagBits),
+    static_assert(static_cast<uint64_t>(MemberT::Tag) < (1 << NumTagBits),
                   "This discriminant value requires too many bits!");
   };
   static_assert(Checker<MemberTs...>::value,
                 "Each member must pass the checker.");
 };
 
 } // end namespace detail
 

llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h

enum OtherType {
     /// This marker indicates that the query has no dependency in the specified
     /// function.
     NonFuncLocal,
     /// This marker indicates that the query dependency is unknown.
     Unknown
   };
 
   using ValueTy = PointerSumType<
-      DepType, PointerSumTypeMember<Invalid, Instruction *>,
-      PointerSumTypeMember<Clobber, Instruction *>,
-      PointerSumTypeMember<Def, Instruction *>,
-      PointerSumTypeMember<Other, PointerEmbeddedInt<OtherType, 3>>>;
+      DepType, PointerSumTypeMember<DepType, Invalid, Instruction *>,
+      PointerSumTypeMember<DepType, Clobber, Instruction *>,
+      PointerSumTypeMember<DepType, Def, Instruction *>,
+      PointerSumTypeMember<DepType, Other, PointerEmbeddedInt<OtherType, 3>>>;
   ValueTy Value;
 
   explicit MemDepResult(ValueTy V) : Value(V) {}
 
 public:
   MemDepResult() = default;
 
   /// get methods: These are static ctor methods for creating various
struct NonLocalPointerInfo {
     NonLocalPointerInfo() = default;
   };
 
   /// Cache storing single nonlocal def for the instruction.
   /// It is set when nonlocal def would be found in function returning only
   /// local dependencies.
   DenseMap<AssertingVH<const Value>, NonLocalDepResult> NonLocalDefsCache;
   using ReverseNonLocalDefsCacheTy =
-    DenseMap<Instruction *, SmallPtrSet<const Value*, 4>>;
+      DenseMap<Instruction *, SmallPtrSet<const Value *, 4>>;
   ReverseNonLocalDefsCacheTy ReverseNonLocalDefsCache;
 
   /// This map stores the cached results of doing a pointer lookup at the
   /// bottom of a block.
   ///
   /// The key of this map is the pointer+isload bit, the value is a list of
   /// <bb->result> mappings.
   using CachedNonLocalPointerInfo =
class MemoryDependenceAnalysis
   static AnalysisKey Key;
 
   unsigned DefaultBlockScanLimit;
 
 public:
   using Result = MemoryDependenceResults;
 
   MemoryDependenceAnalysis();
-  MemoryDependenceAnalysis(unsigned DefaultBlockScanLimit) : DefaultBlockScanLimit(DefaultBlockScanLimit) { }
+  MemoryDependenceAnalysis(unsigned DefaultBlockScanLimit)
+      : DefaultBlockScanLimit(DefaultBlockScanLimit) {}
 
   MemoryDependenceResults run(Function &F, FunctionAnalysisManager &AM);
 };
 
 /// A wrapper analysis pass for the legacy pass manager that exposes a \c
 /// MemoryDepnedenceResults instance.
 class MemoryDependenceWrapperPass : public FunctionPass {
   Optional<MemoryDependenceResults> MemDep;

llvm/include/llvm/CodeGen/MachineInstr.h

 public:
   using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;
 
   /// Flags to specify different kinds of comments to output in
   /// assembly code.  These flags carry semantic information not
   /// otherwise easily derivable from the IR text.
   ///
   enum CommentFlag {
-    ReloadReuse = 0x1,    // higher bits are reserved for target dep comments.
+    ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
     NoSchedComment = 0x2,
-    TAsmComments = 0x4    // Target Asm comments should start from this value.
+    TAsmComments = 0x4 // Target Asm comments should start from this value.
   };
 
   enum MIFlag {
-    NoFlags      = 0,
-    FrameSetup   = 1 << 0,              // Instruction is used as a part of
-                                        // function frame setup code.
-    FrameDestroy = 1 << 1,              // Instruction is used as a part of
-                                        // function frame destruction code.
-    BundledPred  = 1 << 2,              // Instruction has bundled predecessors.
-    BundledSucc  = 1 << 3,              // Instruction has bundled successors.
-    FmNoNans     = 1 << 4,              // Instruction does not support Fast
-                                        // math nan values.
-    FmNoInfs     = 1 << 5,              // Instruction does not support Fast
-                                        // math infinity values.
-    FmNsz        = 1 << 6,              // Instruction is not required to retain
-                                        // signed zero values.
-    FmArcp       = 1 << 7,              // Instruction supports Fast math
-                                        // reciprocal approximations.
-    FmContract   = 1 << 8,              // Instruction supports Fast math
-                                        // contraction operations like fma.
-    FmAfn        = 1 << 9,              // Instruction may map to Fast math
-                                        // instrinsic approximation.
-    FmReassoc    = 1 << 10,             // Instruction supports Fast math
-                                        // reassociation of operand order.
-    NoUWrap      = 1 << 11,             // Instruction supports binary operator
-                                        // no unsigned wrap.
-    NoSWrap      = 1 << 12,             // Instruction supports binary operator
-                                        // no signed wrap.
-    IsExact      = 1 << 13,             // Instruction supports division is
-                                        // known to be exact.
-    NoFPExcept   = 1 << 14,             // Instruction does not raise
-                                        // floatint-point exceptions.
-    NoMerge      = 1 << 15,             // Passes that drop source location info
-                                        // (e.g. branch folding) should skip
-                                        // this instruction.
+    NoFlags = 0,
+    FrameSetup = 1 << 0,   // Instruction is used as a part of
+    FrameDestroy = 1 << 1, // Instruction is used as a part of
+    BundledPred = 1 << 2,  // Instruction has bundled predecessors.
+    BundledSucc = 1 << 3,  // Instruction has bundled successors.
+    FmNoNans = 1 << 4,     // Instruction does not support Fast
+    FmNoInfs = 1 << 5,     // Instruction does not support Fast
+    FmNsz = 1 << 6,        // Instruction is not required to retain
+    FmArcp = 1 << 7,       // Instruction supports Fast math
+    FmContract = 1 << 8,   // Instruction supports Fast math
+    FmAfn = 1 << 9,        // Instruction may map to Fast math
+    FmReassoc = 1 << 10,   // Instruction supports Fast math
+    NoUWrap = 1 << 11,     // Instruction supports binary operator
+    NoSWrap = 1 << 12,     // Instruction supports binary operator
+    IsExact = 1 << 13,     // Instruction supports division is
+    NoFPExcept = 1 << 14,  // Instruction does not raise
+    NoMerge = 1 << 15,     // Passes that drop source location info
   };
 
 private:
-  const MCInstrDesc *MCID;              // Instruction descriptor.
-  MachineBasicBlock *Parent = nullptr;  // Pointer to the owning basic block.
+  const MCInstrDesc *MCID;             // Instruction descriptor.
+  MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
 
   // Operands are allocated by an ArrayRecycler.
-  MachineOperand *Operands = nullptr;   // Pointer to the first operand.
-  unsigned NumOperands = 0;             // Number of operands on instruction.
+  MachineOperand *Operands = nullptr; // Pointer to the first operand.
+  unsigned NumOperands = 0;           // Number of operands on instruction.
 
-  uint16_t Flags = 0;                   // Various bits of additional
-                                        // information about machine
-                                        // instruction.
+  uint16_t Flags = 0; // Various bits of additional
 
-  uint8_t AsmPrinterFlags = 0;          // Various bits of information used by
-                                        // the AsmPrinter to emit helpful
-                                        // comments.  This is *not* semantic
-                                        // information.  Do not use this for
-                                        // anything other than to convey comment
-                                        // information to AsmPrinter.
+  uint8_t AsmPrinterFlags = 0; // Various bits of information used by
 
   // OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags
   // to properly pack.
   using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
-  OperandCapacity CapOperands;          // Capacity of the Operands array.
+  OperandCapacity CapOperands; // Capacity of the Operands array.
 
   /// Internal implementation detail class that provides out-of-line storage for
   /// extra info used by the machine instruction when this info cannot be stored
   /// in-line within the instruction itself.
   ///
   /// This has to be defined eagerly due to the implementation constraints of
   /// `PointerSumType` where it is used.
   class ExtraInfo final
enum ExtraInfoInlineKinds {
     EIIK_OutOfLine
   };
 
   // We store extra information about the instruction here. The common case is
   // expected to be nothing or a single pointer (typically a MMO or a symbol).
   // We work to optimize this common case by storing it inline here rather than
   // requiring a separate allocation, but we fall back to an allocation when
   // multiple pointers are needed.
-  PointerSumType<ExtraInfoInlineKinds,
-                 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
-                 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
-                 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
-                 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
+  PointerSumType<
+      ExtraInfoInlineKinds,
+      PointerSumTypeMember<ExtraInfoInlineKinds, EIIK_MMO, MachineMemOperand *>,
+      PointerSumTypeMember<ExtraInfoInlineKinds, EIIK_PreInstrSymbol,
+                           MCSymbol *>,
+      PointerSumTypeMember<ExtraInfoInlineKinds, EIIK_PostInstrSymbol,
+                           MCSymbol *>,
+      PointerSumTypeMember<ExtraInfoInlineKinds, EIIK_OutOfLine, ExtraInfo *>>
       Info;
 
-  DebugLoc debugLoc;                    // Source line information.
+  DebugLoc debugLoc; // Source line information.
 
   // Intrusive list support
   friend struct ilist_traits<MachineInstr>;
   friend struct ilist_callback_traits<MachineBasicBlock>;
   void setParent(MachineBasicBlock *P) { Parent = P; }
 
   /// This constructor creates a copy of the given
   /// MachineInstr in the given MachineFunction.
dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
             SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
 
 public:
   MachineInstr(const MachineInstr &) = delete;
   MachineInstr &operator=(const MachineInstr &) = delete;
   // Use MachineFunction::DeleteMachineInstr() instead.
   ~MachineInstr() = delete;
 
-  const MachineBasicBlock* getParent() const { return Parent; }
-  MachineBasicBlock* getParent() { return Parent; }
+  const MachineBasicBlock *getParent() const { return Parent; }
+  MachineBasicBlock *getParent() { return Parent; }
 
   /// Move the instruction before \p MovePos.
   void moveBefore(MachineInstr *MovePos);
 
   /// Return the function that contains the basic block that this instruction
   /// belongs to.
   ///
   /// Note: this is undefined behaviour if the instruction does not have a
public:
   void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
 
   /// Return whether an AsmPrinter flag is set.
   bool getAsmPrinterFlag(CommentFlag Flag) const {
     return AsmPrinterFlags & Flag;
   }
 
   /// Set a flag for the AsmPrinter.
-  void setAsmPrinterFlag(uint8_t Flag) {
-    AsmPrinterFlags |= Flag;
-  }
+  void setAsmPrinterFlag(uint8_t Flag) { AsmPrinterFlags |= Flag; }
 
   /// Clear specific AsmPrinter flags.
-  void clearAsmPrinterFlag(CommentFlag Flag) {
-    AsmPrinterFlags &= ~Flag;
-  }
+  void clearAsmPrinterFlag(CommentFlag Flag) { AsmPrinterFlags &= ~Flag; }
 
   /// Return the MI flags bitvector.
-  uint16_t getFlags() const {
-    return Flags;
-  }
+  uint16_t getFlags() const { return Flags; }
 
   /// Return whether an MI flag is set.
-  bool getFlag(MIFlag Flag) const {
-    return Flags & Flag;
-  }
+  bool getFlag(MIFlag Flag) const { return Flags & Flag; }
 
   /// Set a MI flag.
-  void setFlag(MIFlag Flag) {
-    Flags |= (uint16_t)Flag;
-  }
+  void setFlag(MIFlag Flag) { Flags |= (uint16_t)Flag; }
 
   void setFlags(unsigned flags) {
     // Filter out the automatically maintained flags.
     unsigned Mask = BundledPred | BundledSucc;
     Flags = (Flags & Mask) | (flags & ~Mask);
   }
 
   /// clearFlag - Clear a MI flag.
-  void clearFlag(MIFlag Flag) {
-    Flags &= ~((uint16_t)Flag);
-  }
+  void clearFlag(MIFlag Flag) { Flags &= ~((uint16_t)Flag); }
 
   /// Return true if MI is in a bundle (but not the first MI in a bundle).
   ///
   /// A bundle looks like this before it's finalized:
   ///   ----------------
   ///   |      MI      |
   ///   ----------------
   ///          |
public:
   ///   |      MI    * |
   ///   ----------------
   ///          |
   ///   ----------------
   ///   |      MI    * |
   ///   ----------------
   /// The first instruction has the special opcode "BUNDLE". It's not "inside"
   /// a bundle, but the next three MIs are.
-  bool isInsideBundle() const {
-    return getFlag(BundledPred);
-  }
+  bool isInsideBundle() const { return getFlag(BundledPred); }
 
   /// Return true if this instruction part of a bundle. This is true
   /// if either itself or its following instruction is marked "InsideBundle".
-  bool isBundled() const {
-    return isBundledWithPred() || isBundledWithSucc();
-  }
+  bool isBundled() const { return isBundledWithPred() || isBundledWithSucc(); }
 
   /// Return true if this instruction is part of a bundle, and it is not the
   /// first instruction in the bundle.
   bool isBundledWithPred() const { return getFlag(BundledPred); }
 
   /// Return true if this instruction is part of a bundle, and it is not the
   /// last instruction in the bundle.
   bool isBundledWithSucc() const { return getFlag(BundledSucc); }
public:
   /// Retuns the total number of operands.
   unsigned getNumOperands() const { return NumOperands; }
 
   /// Returns the total number of operands which are debug locations.
   unsigned getNumDebugOperands() const {
     return std::distance(debug_operands().begin(), debug_operands().end());
   }
 
-  const MachineOperand& getOperand(unsigned i) const {
+  const MachineOperand &getOperand(unsigned i) const {
     assert(i < getNumOperands() && "getOperand() out of range!");
     return Operands[i];
   }
-  MachineOperand& getOperand(unsigned i) {
+  MachineOperand &getOperand(unsigned i) {
     assert(i < getNumOperands() && "getOperand() out of range!");
     return Operands[i];
   }
 
   MachineOperand &getDebugOperand(unsigned Index) {
     assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
     return *(debug_operands().begin() + Index);
   }
public:
 
   /// Returns the total number of definitions.
   unsigned getNumDefs() const {
     return getNumExplicitDefs() + MCID->getNumImplicitDefs();
   }
 
   /// Returns true if the instruction has implicit definition.
   bool hasImplicitDef() const {
-    for (unsigned I = getNumExplicitOperands(), E = getNumOperands();
-      I != E; ++I) {
+    for (unsigned I = getNumExplicitOperands(), E = getNumOperands(); I != E;
+         ++I) {
       const MachineOperand &MO = getOperand(I);
       if (MO.isDef() && MO.isImplicit())
         return true;
     }
     return false;
   }
 
   /// Returns the implicit operands number.
MDNode *getHeapAllocMarker() const {
 
     return nullptr;
   }
 
   /// API for querying MachineInstr properties. They are the same as MCInstrDesc
   /// queries but they are bundle aware.
 
   enum QueryType {
-    IgnoreBundle,    // Ignore bundles
-    AnyInBundle,     // Return true if any instruction in bundle has property
-    AllInBundle      // Return true if all instructions in bundle have property
+    IgnoreBundle, // Ignore bundles
+    AnyInBundle,  // Return true if any instruction in bundle has property
+    AllInBundle   // Return true if all instructions in bundle have property
   };
 
   /// Return true if the instruction (or in the case of a bundle,
   /// the instructions inside the bundle) has the specified property.
   /// The first argument is the property being queried.
   /// The second argument indicates whether the query should look inside
   /// instruction bundles.
   bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
     return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
   }
 
   /// Return true if this instruction has a predicate operand that
   /// controls execution.  It may be set to 'always', or may be set to other
   /// values.   There are various methods in TargetInstrInfo that can be used to
   /// control and modify the predicate in this instruction.
   bool isPredicable(QueryType Type = AllInBundle) const {
-    // If it's a bundle than all bundled instructions must be predicable for this
-    // to return true.
+    // If it's a bundle than all bundled instructions must be predicable for
+    // this to return true.
     return hasProperty(MCID::Predicable, Type);
   }
 
   /// Return true if this instruction is a comparison.
   bool isCompare(QueryType Type = IgnoreBundle) const {
     return hasProperty(MCID::Compare, Type);
   }
 
public:
   /// even / odd pair, ARM::LDM registers have to be in ascending order.
   /// Post-register allocation passes should not attempt to change allocations
   /// for definitions of instructions with this flag.
   bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
     return hasProperty(MCID::ExtraDefRegAllocReq, Type);
   }
 
   enum MICheckType {
-    CheckDefs,      // Check all operands for equality
-    CheckKillDead,  // Check all operands including kill / dead markers
-    IgnoreDefs,     // Ignore all definitions
-    IgnoreVRegDefs  // Ignore virtual register definitions
+    CheckDefs,     // Check all operands for equality
+    CheckKillDead, // Check all operands including kill / dead markers
+    IgnoreDefs,    // Ignore all definitions
+    IgnoreVRegDefs // Ignore virtual register definitions
   };
 
   /// Return true if this instruction is identical to \p Other.
   /// Two instructions are identical if they have the same opcode and all their
   /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
   /// Note that this means liveness related flags (dead, undef, kill) do not
   /// affect the notion of identical.
   bool isIdenticalTo(const MachineInstr &Other,
return isDebugValue() && getDebugOperand(0).isReg() &&
            !getDebugOperand(0).getReg().isValid();
   }
 
   bool isPHI() const {
     return getOpcode() == TargetOpcode::PHI ||
            getOpcode() == TargetOpcode::G_PHI;
   }
   bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
-  bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
+  bool isImplicitDef() const {
+    return getOpcode() == TargetOpcode::IMPLICIT_DEF;
+  }
   bool isInlineAsm() const {
     return getOpcode() == TargetOpcode::INLINEASM ||
            getOpcode() == TargetOpcode::INLINEASM_BR;
   }
 
   /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
   /// specific, be attached to a generic MachineInstr.
   bool isMSInlineAsm() const {
public:
   bool isSubregToReg() const {
     return getOpcode() == TargetOpcode::SUBREG_TO_REG;
   }
 
   bool isRegSequence() const {
     return getOpcode() == TargetOpcode::REG_SEQUENCE;
   }
 
-  bool isBundle() const {
-    return getOpcode() == TargetOpcode::BUNDLE;
-  }
+  bool isBundle() const { return getOpcode() == TargetOpcode::BUNDLE; }
 
-  bool isCopy() const {
-    return getOpcode() == TargetOpcode::COPY;
-  }
+  bool isCopy() const { return getOpcode() == TargetOpcode::COPY; }
 
   bool isFullCopy() const {
     return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
   }
 
   bool isExtractSubreg() const {
     return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
   }
 
   /// Return true if the instruction behaves like a copy.
   /// This does not include native copy instructions.
-  bool isCopyLike() const {
-    return isCopy() || isSubregToReg();
-  }
+  bool isCopyLike() const { return isCopy() || isSubregToReg(); }
 
   /// Return true is the instruction is an identity copy.
   bool isIdentityCopy() const {
     return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
            getOperand(0).getSubReg() == getOperand(1).getSubReg();
   }
 
   /// Return true if this instruction doesn't produce any output in the form of
   /// executable instructions.
   bool isMetaInstruction() const {
     switch (getOpcode()) {
     default:
       return false;
public:
 
   /// Return true if this is a transient instruction that is either very likely
   /// to be eliminated during register allocation (such as copy-like
   /// instructions), or if this instruction doesn't have an execution-time cost.
   bool isTransient() const {
     switch (getOpcode()) {
     default:
       return isMetaInstruction();
-    // Copy-like instructions are usually eliminated during register allocation.
+    // Copy-like instructions are usually eliminated during register
+    // allocation.
     case TargetOpcode::PHI:
     case TargetOpcode::G_PHI:
     case TargetOpcode::COPY:
     case TargetOpcode::INSERT_SUBREG:
     case TargetOpcode::SUBREG_TO_REG:
     case TargetOpcode::REG_SEQUENCE:
       return true;
     }
public:
   /// read-modify-write operation.
   bool readsVirtualRegister(Register Reg) const {
     return readsWritesVirtualRegister(Reg).first;
   }
 
   /// Return a pair of bools (reads, writes) indicating if this instruction
   /// reads or writes Reg. This also considers partial defines.
   /// If Ops is not null, all operand indices for Reg are added.
-  std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
-                                SmallVectorImpl<unsigned> *Ops = nullptr) const;
+  std::pair<bool, bool>
+  readsWritesVirtualRegister(Register Reg,
 
   /// Return true if the MachineInstr kills the specified register.
   /// If TargetRegisterInfo is passed, then it also checks if there is
   /// a kill of a super-register.
   bool killsRegister(Register Reg,
                      const TargetRegisterInfo *TRI = nullptr) const {
     return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
   }

   /// Returns the operand index that is a use of the specific register or -1
   /// if it is not found. It further tightens the search criteria to a use
   /// that kills the register if isKill is true.
   int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
                                 const TargetRegisterInfo *TRI = nullptr) const;
 
   /// Wrapper for findRegisterUseOperandIdx, it returns
   /// a pointer to the MachineOperand rather than an index.
-  MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
-                                      const TargetRegisterInfo *TRI = nullptr) {
+  MachineOperand *
+  findRegisterUseOperand(Register Reg, bool isKill = false,
     int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
     return (Idx == -1) ? nullptr : &getOperand(Idx);
   }
 
-  const MachineOperand *findRegisterUseOperand(
-    Register Reg, bool isKill = false,
+  const MachineOperand *
+  findRegisterUseOperand(Register Reg, bool isKill = false,
                          const TargetRegisterInfo *TRI = nullptr) const {
-    return const_cast<MachineInstr *>(this)->
-      findRegisterUseOperand(Reg, isKill, TRI);
+    return const_cast<MachineInstr *>(this)->findRegisterUseOperand(Reg, isKill,
+                                                                    TRI);
   }
 
   /// Returns the operand index that is a def of the specified register or
   /// -1 if it is not found. If isDead is true, defs that are not dead are
   /// skipped. If Overlap is true, then it also looks for defs that merely
   /// overlap the specified register. If TargetRegisterInfo is non-null,
   /// then it also checks if there is a def of a super-register.
   /// This may also return a register mask operand when Overlap is true.
-  int findRegisterDefOperandIdx(Register Reg,
-                                bool isDead = false, bool Overlap = false,
+  int findRegisterDefOperandIdx(Register Reg, bool isDead = false,
+                                bool Overlap = false,
                                 const TargetRegisterInfo *TRI = nullptr) const;
 
   /// Wrapper for findRegisterDefOperandIdx, it returns
   /// a pointer to the MachineOperand rather than an index.
   MachineOperand *
   findRegisterDefOperand(Register Reg, bool isDead = false,
                          bool Overlap = false,
                          const TargetRegisterInfo *TRI = nullptr) {

   int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
 
   /// Compute the static register class constraint for operand OpIdx.
   /// For normal instructions, this is derived from the MCInstrDesc.
   /// For inline assembly it is derived from the flag words.
   ///
   /// Returns NULL if the static register class constraint cannot be
   /// determined.
-  const TargetRegisterClass*
-  getRegClassConstraint(unsigned OpIdx,
-                        const TargetInstrInfo *TII,
+  const TargetRegisterClass *
+  getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII,
                         const TargetRegisterInfo *TRI) const;
 
   /// Applies the constraints (def/use) implied by this MI on \p Reg to
   /// the given \p CurRC.
   /// If \p ExploreBundle is set and MI is part of a bundle, all the
   /// instructions inside the bundle will be taken into account. In other words,
   /// this method accumulates all the constraints of the operand of this MI and
   /// the related bundle if MI is a bundle or inside a bundle.

 
   /// Return a valid size if the instruction is a folded spill instruction.
   Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const;
 
   /// Return a valid size if the instruction is a restore instruction.
   Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const;
 
   /// Return a valid size if the instruction is a folded restore instruction.
-  Optional<unsigned>
-  getFoldedRestoreSize(const TargetInstrInfo *TII) const;
+  Optional<unsigned> getFoldedRestoreSize(const TargetInstrInfo *TII) const;
 
   /// Copy implicit register operands from specified
   /// instruction to this instruction.
   void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
 
   /// Debugging support
   /// @{
   /// Determine the generic type to be printed (if needed) on uses and defs.

   /// heap alloc site labels. This waits until after instruction selection and
   /// optimizations to create the label, so it should still work if the
   /// instruction is removed or duplicated.
   void setHeapAllocMarker(MachineFunction &MF, MDNode *MD);
 
   /// Return the MIFlags which represent both MachineInstrs. This
   /// should be used when merging two MachineInstrs into one. This routine does
   /// not modify the MIFlags of this MachineInstr.
-  uint16_t mergeFlagsWith(const MachineInstr& Other) const;
+  uint16_t mergeFlagsWith(const MachineInstr &Other) const;
 
   static uint16_t copyFlagsFromInstruction(const Instruction &I);
 
   /// Copy all flags to MachineInst MIFlags
   void copyIRFlags(const Instruction &I);
 
   /// Break any tie involving OpIdx.
   void untieRegOperand(unsigned OpIdx) {
private:
   /// If this instruction is embedded into a MachineFunction, return the
   /// MachineRegisterInfo object for the current function, otherwise
   /// return null.
   MachineRegisterInfo *getRegInfo();
 
   /// Unlink all of the register operands in this instruction from their
   /// respective use lists.  This requires that the operands already be on their
   /// use lists.
-  void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
+  void RemoveRegOperandsFromUseLists(MachineRegisterInfo &);
 
   /// Add all of the register operands in this instruction from their
   /// respective use lists.  This requires that the operands not be on their
   /// use lists yet.
-  void AddRegOperandsToUseLists(MachineRegisterInfo&);
+  void AddRegOperandsToUseLists(MachineRegisterInfo &);
 
   /// Slow path for hasProperty when we're dealing with a bundle.
   bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
 
   /// Implements the logic of getRegClassConstraintEffectForVReg for the
   /// this MI and the given operand index \p OpIdx.
   /// If the related operand does not constrained Reg, this returns CurRC.
   const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
       unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
       const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
 
   /// Stores extra instruction information inline or allocates as ExtraInfo
   /// based on the number of pointers.
   void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
                     MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
                     MDNode *HeapAllocMarker);
 };
 
 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
 /// instruction rather than by pointer value.
 /// The hashing and equality testing functions ignore definitions so this is
 /// useful for CSE, etc.
-struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
-  static inline MachineInstr *getEmptyKey() {
-    return nullptr;
-  }
+struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr *> {
+  static inline MachineInstr *getEmptyKey() { return nullptr; }
 
   static inline MachineInstr *getTombstoneKey() {
-    return reinterpret_cast<MachineInstr*>(-1);
+    return reinterpret_cast<MachineInstr *>(-1);
   }
 
-  static unsigned getHashValue(const MachineInstr* const &MI);
+  static unsigned getHashValue(const MachineInstr *const &MI);
 
-  static bool isEqual(const MachineInstr* const &LHS,
-                      const MachineInstr* const &RHS) {
+  static bool isEqual(const MachineInstr *const &LHS,
+                      const MachineInstr *const &RHS) {
     if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
         LHS == getEmptyKey() || LHS == getTombstoneKey())
       return LHS == RHS;
     return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
   }
 };
 
 //===----------------------------------------------------------------------===//
 // Debugging Support
 
-inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
+inline raw_ostream &operator<<(raw_ostream &OS, const MachineInstr &MI) {
   MI.print(OS);
   return OS;
 }
 
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_MACHINEINSTR_H

llvm/unittests/ADT/PointerSumTypeTest.cpp

 
 namespace {
 
 struct PointerSumTypeTest : public testing::Test {
   enum Kinds { Float, Int1, Int2 };
   float f;
   int i1, i2;
 
-  typedef PointerSumType<Kinds, PointerSumTypeMember<Float, float *>,
-                         PointerSumTypeMember<Int1, int *>,
-                         PointerSumTypeMember<Int2, int *>>
+  typedef PointerSumType<Kinds, PointerSumTypeMember<Kinds, Float, float *>,
+                         PointerSumTypeMember<Kinds, Int1, int *>,
+                         PointerSumTypeMember<Kinds, Int2, int *>>
       SumType;
   SumType a, b, c, n;
 
   PointerSumTypeTest()
       : f(3.14f), i1(42), i2(-1), a(SumType::create<Float>(&f)),
         b(SumType::create<Int1>(&i1)), c(SumType::create<Int2>(&i2)), n() {}
 };
 
TEST_F(PointerSumTypeTest, Assignment) {
 
   n = SumType::create<Float>(nullptr);
   EXPECT_FALSE(n);
   EXPECT_EQ(nullptr, n.get<Float>());
   EXPECT_EQ(nullptr, n.get<Int1>());
   EXPECT_EQ(nullptr, n.get<Int2>());
 }
 
+TEST_F(PointerSumTypeTest, ScopedEnum) {
+  enum class ScopedKind { Float, Int1, Int2 };
+  using ScopedSumType = PointerSumType<
+      ScopedKind, PointerSumTypeMember<ScopedKind, ScopedKind::Float, float *>,
+      PointerSumTypeMember<ScopedKind, ScopedKind::Int1, int *>,
+      PointerSumTypeMember<ScopedKind, ScopedKind::Int2, int *>>;
+  ScopedSumType SumType(ScopedSumType::create<ScopedKind::Float>(&f));
+  EXPECT_TRUE(SumType);
+  EXPECT_EQ(ScopedKind::Float, SumType.getTag());
+}
 
 } // end anonymous namespace