[AArch64] Rename Pairs to Mappings in AArch64NamedImmMapper

[vsukharev]

Summary

Third element is to be added soon to "struct AArch64NamedImmMapper::Mapping".
So its instances should be renamed from ...Pairs to ...Mappings

[jmolloy]

LGTM!

lib/Target/AArch64/Utils/AArch64BaseInfo.h

 /// rather than changing the algorithm.
 struct AArch64NamedImmMapper {
   struct Mapping {
     const char *Name;
     uint32_t Value;
   };
 
   template<int N>
-  AArch64NamedImmMapper(const Mapping (&Pairs)[N], uint32_t TooBigImm)
-    : Pairs(&Pairs[0]), NumPairs(N), TooBigImm(TooBigImm) {}
+  AArch64NamedImmMapper(const Mapping (&Mappings)[N], uint32_t TooBigImm)
+    : Mappings(&Mappings[0]), NumMappings(N), TooBigImm(TooBigImm) {}
 
   StringRef toString(uint32_t Value, bool &Valid) const;
   uint32_t fromString(StringRef Name, bool &Valid) const;
 
   /// Many of the instructions allow an alternative assembly form consisting of
   /// a simple immediate. Currently the only valid forms are ranges [0, N) where
   /// N being 0 indicates no immediate syntax-form is allowed.
   bool validImm(uint32_t Value) const;
 protected:
-  const Mapping *Pairs;
-  size_t NumPairs;
+  const Mapping *Mappings;
+  size_t NumMappings;
   uint32_t TooBigImm;
 };
 
 namespace AArch64AT {
   enum ATValues {
     Invalid = -1,    // Op0 Op1  CRn   CRm   Op2
     S1E1R = 0x43c0,  // 01  000  0111  1000  000
     S1E2R = 0x63c0,  // 01  100  0111  1000  000
     S1E3R = 0x73c0,  // 01  110  0111  1000  000
     S1E1W = 0x43c1,  // 01  000  0111  1000  001
     S1E2W = 0x63c1,  // 01  100  0111  1000  001
     S1E3W = 0x73c1,  // 01  110  0111  1000  001
     S1E0R = 0x43c2,  // 01  000  0111  1000  010
     S1E0W = 0x43c3,  // 01  000  0111  1000  011
     S12E1R = 0x63c4, // 01  100  0111  1000  100
     S12E1W = 0x63c5, // 01  100  0111  1000  101
     S12E0R = 0x63c6, // 01  100  0111  1000  110
     S12E0W = 0x63c7  // 01  100  0111  1000  111
   };
 
   struct ATMapper : AArch64NamedImmMapper {
-    const static Mapping ATPairs[];
+    const static Mapping ATMappings[];
 
     ATMapper();
   };
 
 }
 namespace AArch64DB {
   enum DBValues {
     Invalid = -1,
     OSHLD = 0x1,
     OSHST = 0x2,
     OSH =   0x3,
     NSHLD = 0x5,
     NSHST = 0x6,
     NSH =   0x7,
     ISHLD = 0x9,
     ISHST = 0xa,
     ISH =   0xb,
     LD =    0xd,
     ST =    0xe,
     SY =    0xf
   };
 
   struct DBarrierMapper : AArch64NamedImmMapper {
-    const static Mapping DBarrierPairs[];
+    const static Mapping DBarrierMappings[];
 
     DBarrierMapper();
   };
 }
 
 namespace  AArch64DC {
   enum DCValues {
     Invalid = -1,   // Op1  CRn   CRm   Op2
     ZVA   = 0x5ba1, // 01  011  0111  0100  001
     IVAC  = 0x43b1, // 01  000  0111  0110  001
     ISW   = 0x43b2, // 01  000  0111  0110  010
     CVAC  = 0x5bd1, // 01  011  0111  1010  001
     CSW   = 0x43d2, // 01  000  0111  1010  010
     CVAU  = 0x5bd9, // 01  011  0111  1011  001
     CIVAC = 0x5bf1, // 01  011  0111  1110  001
     CISW  = 0x43f2  // 01  000  0111  1110  010
   };
 
   struct DCMapper : AArch64NamedImmMapper {
-    const static Mapping DCPairs[];
+    const static Mapping DCMappings[];
 
     DCMapper();
   };
 
 }
 
 namespace  AArch64IC {
   enum ICValues {
     Invalid = -1,     // Op1  CRn   CRm   Op2
     IALLUIS = 0x0388, // 000  0111  0001  000
     IALLU = 0x03a8,   // 000  0111  0101  000
     IVAU = 0x1ba9     // 011  0111  0101  001
   };
 
 
   struct ICMapper : AArch64NamedImmMapper {
-    const static Mapping ICPairs[];
+    const static Mapping ICMappings[];
 
     ICMapper();
   };
 
   static inline bool NeedsRegister(ICValues Val) {
     return Val == IVAU;
   }
 }
 
 namespace  AArch64ISB {
   enum ISBValues {
     Invalid = -1,
     SY = 0xf
   };
   struct ISBMapper : AArch64NamedImmMapper {
-    const static Mapping ISBPairs[];
+    const static Mapping ISBMappings[];
 
     ISBMapper();
   };
 }
 
 namespace AArch64PRFM {
   enum PRFMValues {
     Invalid = -1,
enum PRFMValues {
     PSTL1STRM = 0x11,
     PSTL2KEEP = 0x12,
     PSTL2STRM = 0x13,
     PSTL3KEEP = 0x14,
     PSTL3STRM = 0x15
   };
 
   struct PRFMMapper : AArch64NamedImmMapper {
-    const static Mapping PRFMPairs[];
+    const static Mapping PRFMMappings[];
 
     PRFMMapper();
   };
 }
 
 namespace AArch64PState {
   enum PStateValues {
     Invalid = -1,
     SPSel = 0x05,
     DAIFSet = 0x1e,
     DAIFClr = 0x1f
   };
 
   struct PStateMapper : AArch64NamedImmMapper {
-    const static Mapping PStatePairs[];
+    const static Mapping PStateMappings[];
 
     PStateMapper();
   };
 
 }
 
 namespace AArch64SE {
     enum ShiftExtSpecifiers {
enum CycloneSysRegValues {
     CPM_IOACC_CTL_EL3 = 0xff90
   };
 
   // Note that these do not inherit from AArch64NamedImmMapper. This class is
   // sufficiently different in its behaviour that I don't believe it's worth
   // burdening the common AArch64NamedImmMapper with abstractions only needed in
   // this one case.
   struct SysRegMapper {
-    static const AArch64NamedImmMapper::Mapping SysRegPairs[];
-    static const AArch64NamedImmMapper::Mapping CycloneSysRegPairs[];
+    static const AArch64NamedImmMapper::Mapping SysRegMappings[];
+    static const AArch64NamedImmMapper::Mapping CycloneSysRegMappings[];
 
-    const AArch64NamedImmMapper::Mapping *InstPairs;
-    size_t NumInstPairs;
+    const AArch64NamedImmMapper::Mapping *InstMappings;
+    size_t NumInstMappings;
     const FeatureBitset &FeatureBits;
 
     SysRegMapper(const FeatureBitset &FeatureBits) : FeatureBits(FeatureBits) { }
     uint32_t fromString(StringRef Name, bool &Valid) const;
     std::string toString(uint32_t Bits) const;
   };
 
   struct MSRMapper : SysRegMapper {
-    static const AArch64NamedImmMapper::Mapping MSRPairs[];
+    static const AArch64NamedImmMapper::Mapping MSRMappings[];
     MSRMapper(const FeatureBitset &FeatureBits);
   };
 
   struct MRSMapper : SysRegMapper {
-    static const AArch64NamedImmMapper::Mapping MRSPairs[];
+    static const AArch64NamedImmMapper::Mapping MRSMappings[];
     MRSMapper(const FeatureBitset &FeatureBits);
   };
 
   uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
 }
 
 namespace AArch64TLBI {
   enum TLBIValues {
enum TLBIValues {
     VALE1        = 0x443d, // 01  000  1000  0111  101
     VALE2        = 0x643d, // 01  100  1000  0111  101
     VALE3        = 0x743d, // 01  110  1000  0111  101
     VMALLS12E1   = 0x643e, // 01  100  1000  0111  110
     VAALE1       = 0x443f  // 01  000  1000  0111  111
   };
 
   struct TLBIMapper : AArch64NamedImmMapper {
-    const static Mapping TLBIPairs[];
+    const static Mapping TLBIMappings[];
 
     TLBIMapper();
   };
 
   static inline bool NeedsRegister(TLBIValues Val) {
     switch (Val) {
     case VMALLE1IS:
     case ALLE2IS:

lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/Regex.h"
 
 using namespace llvm;
 
 StringRef AArch64NamedImmMapper::toString(uint32_t Value, bool &Valid) const {
-  for (unsigned i = 0; i < NumPairs; ++i) {
-    if (Pairs[i].Value == Value) {
+  for (unsigned i = 0; i < NumMappings; ++i) {
+    if (Mappings[i].Value == Value) {
       Valid = true;
-      return Pairs[i].Name;
+      return Mappings[i].Name;
     }
   }
 
   Valid = false;
   return StringRef();
 }
 
 uint32_t AArch64NamedImmMapper::fromString(StringRef Name, bool &Valid) const {
   std::string LowerCaseName = Name.lower();
-  for (unsigned i = 0; i < NumPairs; ++i) {
-    if (Pairs[i].Name == LowerCaseName) {
+  for (unsigned i = 0; i < NumMappings; ++i) {
+    if (Mappings[i].Name == LowerCaseName) {
       Valid = true;
-      return Pairs[i].Value;
+      return Mappings[i].Value;
     }
   }
 
   Valid = false;
   return -1;
 }
 
 bool AArch64NamedImmMapper::validImm(uint32_t Value) const {
   return Value < TooBigImm;
 }
 
-const AArch64NamedImmMapper::Mapping AArch64AT::ATMapper::ATPairs[] = {
+const AArch64NamedImmMapper::Mapping AArch64AT::ATMapper::ATMappings[] = {
   {"s1e1r", S1E1R},
   {"s1e2r", S1E2R},
   {"s1e3r", S1E3R},
   {"s1e1w", S1E1W},
   {"s1e2w", S1E2W},
   {"s1e3w", S1E3W},
   {"s1e0r", S1E0R},
   {"s1e0w", S1E0W},
   {"s12e1r", S12E1R},
   {"s12e1w", S12E1W},
   {"s12e0r", S12E0R},
   {"s12e0w", S12E0W},
 };
 
 AArch64AT::ATMapper::ATMapper()
-  : AArch64NamedImmMapper(ATPairs, 0) {}
+  : AArch64NamedImmMapper(ATMappings, 0) {}
 
-const AArch64NamedImmMapper::Mapping AArch64DB::DBarrierMapper::DBarrierPairs[] = {
+const AArch64NamedImmMapper::Mapping AArch64DB::DBarrierMapper::DBarrierMappings[] = {
   {"oshld", OSHLD},
   {"oshst", OSHST},
   {"osh", OSH},
   {"nshld", NSHLD},
   {"nshst", NSHST},
   {"nsh", NSH},
   {"ishld", ISHLD},
   {"ishst", ISHST},
   {"ish", ISH},
   {"ld", LD},
   {"st", ST},
   {"sy", SY}
 };
 
 AArch64DB::DBarrierMapper::DBarrierMapper()
-  : AArch64NamedImmMapper(DBarrierPairs, 16u) {}
+  : AArch64NamedImmMapper(DBarrierMappings, 16u) {}
 
-const AArch64NamedImmMapper::Mapping AArch64DC::DCMapper::DCPairs[] = {
+const AArch64NamedImmMapper::Mapping AArch64DC::DCMapper::DCMappings[] = {
   {"zva", ZVA},
   {"ivac", IVAC},
   {"isw", ISW},
   {"cvac", CVAC},
   {"csw", CSW},
   {"cvau", CVAU},
   {"civac", CIVAC},
   {"cisw", CISW}
 };
 
 AArch64DC::DCMapper::DCMapper()
-  : AArch64NamedImmMapper(DCPairs, 0) {}
+  : AArch64NamedImmMapper(DCMappings, 0) {}
 
-const AArch64NamedImmMapper::Mapping AArch64IC::ICMapper::ICPairs[] = {
+const AArch64NamedImmMapper::Mapping AArch64IC::ICMapper::ICMappings[] = {
   {"ialluis",  IALLUIS},
   {"iallu", IALLU},
   {"ivau", IVAU}
 };
 
 AArch64IC::ICMapper::ICMapper()
-  : AArch64NamedImmMapper(ICPairs, 0) {}
+  : AArch64NamedImmMapper(ICMappings, 0) {}
 
-const AArch64NamedImmMapper::Mapping AArch64ISB::ISBMapper::ISBPairs[] = {
+const AArch64NamedImmMapper::Mapping AArch64ISB::ISBMapper::ISBMappings[] = {
   {"sy",  SY},
 };
 
 AArch64ISB::ISBMapper::ISBMapper()
-  : AArch64NamedImmMapper(ISBPairs, 16) {}
+  : AArch64NamedImmMapper(ISBMappings, 16) {}
 
-const AArch64NamedImmMapper::Mapping AArch64PRFM::PRFMMapper::PRFMPairs[] = {
+const AArch64NamedImmMapper::Mapping AArch64PRFM::PRFMMapper::PRFMMappings[] = {
   {"pldl1keep", PLDL1KEEP},
   {"pldl1strm", PLDL1STRM},
   {"pldl2keep", PLDL2KEEP},
   {"pldl2strm", PLDL2STRM},
   {"pldl3keep", PLDL3KEEP},
   {"pldl3strm", PLDL3STRM},
   {"plil1keep", PLIL1KEEP},
   {"plil1strm", PLIL1STRM},
   {"plil2keep", PLIL2KEEP},
   {"plil2strm", PLIL2STRM},
   {"plil3keep", PLIL3KEEP},
   {"plil3strm", PLIL3STRM},
   {"pstl1keep", PSTL1KEEP},
   {"pstl1strm", PSTL1STRM},
   {"pstl2keep", PSTL2KEEP},
   {"pstl2strm", PSTL2STRM},
   {"pstl3keep", PSTL3KEEP},
   {"pstl3strm", PSTL3STRM}
 };
 
 AArch64PRFM::PRFMMapper::PRFMMapper()
-  : AArch64NamedImmMapper(PRFMPairs, 32) {}
+  : AArch64NamedImmMapper(PRFMMappings, 32) {}
 
-const AArch64NamedImmMapper::Mapping AArch64PState::PStateMapper::PStatePairs[] = {
+const AArch64NamedImmMapper::Mapping AArch64PState::PStateMapper::PStateMappings[] = {
   {"spsel", SPSel},
   {"daifset", DAIFSet},
   {"daifclr", DAIFClr}
 };
 
 AArch64PState::PStateMapper::PStateMapper()
-  : AArch64NamedImmMapper(PStatePairs, 0) {}
+  : AArch64NamedImmMapper(PStateMappings, 0) {}
 
-const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSPairs[] = {
+const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
   {"mdccsr_el0", MDCCSR_EL0},
   {"dbgdtrrx_el0", DBGDTRRX_EL0},
   {"mdrar_el1", MDRAR_EL1},
   {"oslsr_el1", OSLSR_EL1},
   {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1},
   {"pmceid0_el0", PMCEID0_EL0},
   {"pmceid1_el0", PMCEID1_EL0},
   {"midr_el1", MIDR_EL1},
const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
   {"icc_rpr_el1", ICC_RPR_EL1},
   {"ich_vtr_el2", ICH_VTR_EL2},
   {"ich_eisr_el2", ICH_EISR_EL2},
   {"ich_elsr_el2", ICH_ELSR_EL2}
 };
 
 AArch64SysReg::MRSMapper::MRSMapper(const FeatureBitset &FeatureBits)
   : SysRegMapper(FeatureBits) {
-    InstPairs = &MRSPairs[0];
-    NumInstPairs = llvm::array_lengthof(MRSPairs);
+    InstMappings = &MRSMappings[0];
+    NumInstMappings = llvm::array_lengthof(MRSMappings);
 }
 
-const AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRPairs[] = {
+const AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRMappings[] = {
   {"dbgdtrtx_el0", DBGDTRTX_EL0},
   {"oslar_el1", OSLAR_EL1},
   {"pmswinc_el0", PMSWINC_EL0},
 
   // Trace registers
   {"trcoslar", TRCOSLAR},
   {"trclar", TRCLAR},
 
   // GICv3 registers
   {"icc_eoir1_el1", ICC_EOIR1_EL1},
   {"icc_eoir0_el1", ICC_EOIR0_EL1},
   {"icc_dir_el1", ICC_DIR_EL1},
   {"icc_sgi1r_el1", ICC_SGI1R_EL1},
   {"icc_asgi1r_el1", ICC_ASGI1R_EL1},
   {"icc_sgi0r_el1", ICC_SGI0R_EL1}
 };
 
 AArch64SysReg::MSRMapper::MSRMapper(const FeatureBitset &FeatureBits)
   : SysRegMapper(FeatureBits) {
-    InstPairs = &MSRPairs[0];
-    NumInstPairs = llvm::array_lengthof(MSRPairs);
+    InstMappings = &MSRMappings[0];
+    NumInstMappings = llvm::array_lengthof(MSRMappings);
 }
 
 
-const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegPairs[] = {
+const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = {
   {"osdtrrx_el1", OSDTRRX_EL1},
   {"osdtrtx_el1",  OSDTRTX_EL1},
   {"teecr32_el1", TEECR32_EL1},
   {"mdccint_el1", MDCCINT_EL1},
   {"mdscr_el1", MDSCR_EL1},
   {"dbgdtr_el0", DBGDTR_EL0},
   {"oseccr_el1", OSECCR_EL1},
   {"dbgvcr32_el2", DBGVCR32_EL2},
const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = {
   {"ich_lr11_el2", ICH_LR11_EL2},
   {"ich_lr12_el2", ICH_LR12_EL2},
   {"ich_lr13_el2", ICH_LR13_EL2},
   {"ich_lr14_el2", ICH_LR14_EL2},
   {"ich_lr15_el2", ICH_LR15_EL2}
 };
 
 const AArch64NamedImmMapper::Mapping
-AArch64SysReg::SysRegMapper::CycloneSysRegPairs[] = {
+AArch64SysReg::SysRegMapper::CycloneSysRegMappings[] = {
   {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3}
 };
 
 uint32_t
 AArch64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const {
   std::string NameLower = Name.lower();
 
   // First search the registers shared by all
-  for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) {
-    if (SysRegPairs[i].Name == NameLower) {
+  for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) {
+    if (SysRegMappings[i].Name == NameLower) {
       Valid = true;
-      return SysRegPairs[i].Value;
+      return SysRegMappings[i].Value;
     }
   }
 
   // Next search for target specific registers
   if (FeatureBits[AArch64::ProcCyclone]) {
-    for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
-      if (CycloneSysRegPairs[i].Name == NameLower) {
+    for (unsigned i = 0; i < array_lengthof(CycloneSysRegMappings); ++i) {
+      if (CycloneSysRegMappings[i].Name == NameLower) {
         Valid = true;
-        return CycloneSysRegPairs[i].Value;
+        return CycloneSysRegMappings[i].Value;
       }
     }
   }
 
   // Now try the instruction-specific registers (either read-only or
   // write-only).
-  for (unsigned i = 0; i < NumInstPairs; ++i) {
-    if (InstPairs[i].Name == NameLower) {
+  for (unsigned i = 0; i < NumInstMappings; ++i) {
+    if (InstMappings[i].Name == NameLower) {
       Valid = true;
-      return InstPairs[i].Value;
+      return InstMappings[i].Value;
     }
   }
 
   // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
   Regex GenericRegPattern("^s([0-3])_([0-7])_c([0-9]|1[0-5])_c([0-9]|1[0-5])_([0-7])$");
 
   SmallVector<StringRef, 5> Ops;
   if (!GenericRegPattern.match(NameLower, &Ops)) {
AArch64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const {
 
   Valid = true;
   return Bits;
 }
 
 std::string
 AArch64SysReg::SysRegMapper::toString(uint32_t Bits) const {
   // First search the registers shared by all
-  for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) {
-    if (SysRegPairs[i].Value == Bits) {
-      return SysRegPairs[i].Name;
+  for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) {
+    if (SysRegMappings[i].Value == Bits) {
+      return SysRegMappings[i].Name;
     }
   }
 
   // Next search for target specific registers
   if (FeatureBits[AArch64::ProcCyclone]) {
-    for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
-      if (CycloneSysRegPairs[i].Value == Bits) {
-        return CycloneSysRegPairs[i].Name;
+    for (unsigned i = 0; i < array_lengthof(CycloneSysRegMappings); ++i) {
+      if (CycloneSysRegMappings[i].Value == Bits) {
+        return CycloneSysRegMappings[i].Name;
       }
     }
   }
 
   // Now try the instruction-specific registers (either read-only or
   // write-only).
-  for (unsigned i = 0; i < NumInstPairs; ++i) {
-    if (InstPairs[i].Value == Bits) {
-      return InstPairs[i].Name;
+  for (unsigned i = 0; i < NumInstMappings; ++i) {
+    if (InstMappings[i].Value == Bits) {
+      return InstMappings[i].Name;
     }
   }
 
   assert(Bits < 0x10000);
   uint32_t Op0 = (Bits >> 14) & 0x3;
   uint32_t Op1 = (Bits >> 11) & 0x7;
   uint32_t CRn = (Bits >> 7) & 0xf;
   uint32_t CRm = (Bits >> 3) & 0xf;
   uint32_t Op2 = Bits & 0x7;
 
   return "s" + utostr(Op0)+ "_" + utostr(Op1) + "_c" + utostr(CRn)
                + "_c" + utostr(CRm) + "_" + utostr(Op2);
 }
 
-const AArch64NamedImmMapper::Mapping AArch64TLBI::TLBIMapper::TLBIPairs[] = {
+const AArch64NamedImmMapper::Mapping AArch64TLBI::TLBIMapper::TLBIMappings[] = {
   {"ipas2e1is", IPAS2E1IS},
   {"ipas2le1is", IPAS2LE1IS},
   {"vmalle1is", VMALLE1IS},
   {"alle2is", ALLE2IS},
   {"alle3is", ALLE3IS},
   {"vae1is", VAE1IS},
   {"vae2is", VAE2IS},
   {"vae3is", VAE3IS},
const AArch64NamedImmMapper::Mapping AArch64TLBI::TLBIMapper::TLBIMappings[] = {
   {"vale1", VALE1},
   {"vale2", VALE2},
   {"vale3", VALE3},
   {"vmalls12e1", VMALLS12E1},
   {"vaale1", VAALE1}
 };
 
 AArch64TLBI::TLBIMapper::TLBIMapper()
-  : AArch64NamedImmMapper(TLBIPairs, 0) {}
+  : AArch64NamedImmMapper(TLBIMappings, 0) {}