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Differential D82088

[AVR] Disassemble instructions with fixed Z operand
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Authored by aykevl on Jun 18 2020, 5:59 AM.

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Reviewers
dylanmckay
Commits
rG9f09c29f0158: [AVR] Disassemble instructions with fixed Z operand
Summary

Some instructions have a fixed Z register and don't have an explicit register operand. This can be worked around by simply printing the operand directly if the particular register class is detected.

The lpm and elpm instructions also needed a custom decoder, which is also included in this patch.

Note: I don't know whether the way I've made the Z register printable is the correct way. Maybe the register should be added to the MCInst instead.

Diff Detail

Event Timeline

aykevl created this revision.Jun 18 2020, 5:59 AM
Herald added subscribers: Jim, hiraditya. · View Herald TranscriptJun 18 2020, 5:59 AM
Harbormaster failed remote builds in B60816: Diff 271685!Jun 18 2020, 6:30 AM
dylanmckay accepted this revision.Jun 18 2020, 10:23 PM

Note: I don't know whether the way I've made the Z register printable is the correct way. Maybe the register should be added to the MCInst instead.

The way you've done it looks correct to me - it both prints the operand with the special Z symbol and adds the register to the MCInst, and is consistent with the existing printOperand logic. Nice work.

This revision is now accepted and ready to land.Jun 18 2020, 10:23 PM
Closed by commit rG9f09c29f0158: [AVR] Disassemble instructions with fixed Z operand (authored by aykevl). · Explain WhyJun 22 2020, 5:45 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AVR/
2 lines
Disassembler/
11 lines
MCTargetDesc/
9 lines
test/
MC/
AVR/
9 lines
6 lines
6 lines
6 lines
12 lines
4 lines
6 lines

Diff 272576

llvm/lib/Target/AVR/AVRInstrFormats.td

Show First 20 Lines • Show All 231 Lines • ▼ Show 20 Linesclass FLPMX<bit e, bit p, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{11-9} = 0b000; let Inst{11-9} = 0b000;
let Inst{8} = reg{4}; let Inst{8} = reg{4};
let Inst{7-4} = reg{3-0}; let Inst{7-4} = reg{3-0};
let Inst{3-2} = 0b01; let Inst{3-2} = 0b01;
let Inst{1} = e; let Inst{1} = e;
let Inst{0} = p; let Inst{0} = p;
let DecoderMethod = "decodeFLPMX";
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MOVWRdRr special encoding: <|0000|0001|dddd|rrrr|> // MOVWRdRr special encoding: <|0000|0001|dddd|rrrr|>
// d = destination = 4 bits // d = destination = 4 bits
// r = source = 4 bits // r = source = 4 bits
// (Only accepts even registers) // (Only accepts even registers)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 343 Lines • Show Last 20 Lines

llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Linesstatic DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn, static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn, static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn, static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
#include "AVRGenDisassemblerTables.inc" #include "AVRGenDisassemblerTables.inc"
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned d = fieldFromInstruction(Insn, 4, 5); unsigned d = fieldFromInstruction(Insn, 4, 5);
if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail) if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
if (decodeFRd(Inst, Insn, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(AVR::R31R30));
return MCDisassembler::Success;
}
static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn, static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned d = fieldFromInstruction(Insn, 4, 3) + 16; unsigned d = fieldFromInstruction(Insn, 4, 3) + 16;
unsigned r = fieldFromInstruction(Insn, 0, 3) + 16; unsigned r = fieldFromInstruction(Insn, 0, 3) + 16;
if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail) if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) == MCDisassembler::Fail) if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines

llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines if (MRI.getNumSubRegIndices() > 0) {
RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum; RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum;
} }
return getRegisterName(RegNum); return getRegisterName(RegNum);
} }
void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) { raw_ostream &O) {
const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).OpInfo[OpNo];
if (MOI.RegClass == AVR::ZREGRegClassID) {
// Special case for the Z register, which sometimes doesn't have an operand
// in the MCInst.
O << "Z";
return;
}
if (OpNo >= MI->size()) { if (OpNo >= MI->size()) {
// Not all operands are correctly disassembled at the moment. This means // Not all operands are correctly disassembled at the moment. This means
// that some machine instructions won't have all the necessary operands // that some machine instructions won't have all the necessary operands
// set. // set.
// To avoid asserting, print <unknown> instead until the necessary support // To avoid asserting, print <unknown> instead until the necessary support
// has been implemented. // has been implemented.
O << "<unknown>"; O << "<unknown>";
return; return;
} }
const MCOperand &Op = MI->getOperand(OpNo); const MCOperand &Op = MI->getOperand(OpNo);
const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).OpInfo[OpNo];
if (Op.isReg()) { if (Op.isReg()) {
bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) ||
(MOI.RegClass == AVR::PTRDISPREGSRegClassID) || (MOI.RegClass == AVR::PTRDISPREGSRegClassID) ||
(MOI.RegClass == AVR::ZREGRegClassID); (MOI.RegClass == AVR::ZREGRegClassID);
if (isPtrReg) { if (isPtrReg) {
O << getRegisterName(Op.getReg(), AVR::ptr); O << getRegisterName(Op.getReg(), AVR::ptr);
▲ Show 20 Lines • Show All 69 Lines • Show Last 20 Lines

llvm/test/MC/AVR/inst-elpm.s

; RUN: llvm-mc -triple avr -mattr=elpm,elpmx -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -mattr=elpm,elpmx -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=elpm,elpmx < %s | llvm-objdump -d --mattr=elpm,elpmx - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
elpm elpm
elpm r3, Z elpm r3, Z
elpm r23, Z elpm r23, Z
elpm r8, Z+ elpm r8, Z+
elpm r0, Z+ elpm r0, Z+
; CHECK: elpm ; encoding: [0xd8,0x95] ; CHECK: elpm ; encoding: [0xd8,0x95]
; CHECK: elpm r3, Z ; encoding: [0x36,0x90] ; CHECK: elpm r3, Z ; encoding: [0x36,0x90]
; CHECK: elpm r23, Z ; encoding: [0x76,0x91] ; CHECK: elpm r23, Z ; encoding: [0x76,0x91]
; CHECK: elpm r8, Z+ ; encoding: [0x87,0x90] ; CHECK: elpm r8, Z+ ; encoding: [0x87,0x90]
; CHECK: elpm r0, Z+ ; encoding: [0x07,0x90] ; CHECK: elpm r0, Z+ ; encoding: [0x07,0x90]
; CHECK-INST: elpm
; CHECK-INST: elpm r3, Z
; CHECK-INST: elpm r23, Z
; CHECK-INST: elpm r8, Z+
; CHECK-INST: elpm r0, Z+

llvm/test/MC/AVR/inst-lac.s

; RUN: llvm-mc -triple avr -mattr=rmw -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -mattr=rmw -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=rmw < %s | llvm-objdump -d --mattr=rmw - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
lac Z, r13 lac Z, r13
lac Z, r0 lac Z, r0
lac Z, r31 lac Z, r31
lac Z, r3 lac Z, r3
; CHECK: lac Z, r13 ; encoding: [0xd6,0x92] ; CHECK: lac Z, r13 ; encoding: [0xd6,0x92]
; CHECK: lac Z, r0 ; encoding: [0x06,0x92] ; CHECK: lac Z, r0 ; encoding: [0x06,0x92]
; CHECK: lac Z, r31 ; encoding: [0xf6,0x93] ; CHECK: lac Z, r31 ; encoding: [0xf6,0x93]
; CHECK: lac Z, r3 ; encoding: [0x36,0x92] ; CHECK: lac Z, r3 ; encoding: [0x36,0x92]
; CHECK-INST: lac Z, r13
; CHECK-INST: lac Z, r0
; CHECK-INST: lac Z, r31
; CHECK-INST: lac Z, r3

llvm/test/MC/AVR/inst-las.s

; RUN: llvm-mc -triple avr -mattr=rmw -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -mattr=rmw -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=rmw < %s | llvm-objdump -d --mattr=rmw - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
las Z, r13 las Z, r13
las Z, r0 las Z, r0
las Z, r31 las Z, r31
las Z, r3 las Z, r3
; CHECK: las Z, r13 ; encoding: [0xd5,0x92] ; CHECK: las Z, r13 ; encoding: [0xd5,0x92]
; CHECK: las Z, r0 ; encoding: [0x05,0x92] ; CHECK: las Z, r0 ; encoding: [0x05,0x92]
; CHECK: las Z, r31 ; encoding: [0xf5,0x93] ; CHECK: las Z, r31 ; encoding: [0xf5,0x93]
; CHECK: las Z, r3 ; encoding: [0x35,0x92] ; CHECK: las Z, r3 ; encoding: [0x35,0x92]
; CHECK-INST: las Z, r13
; CHECK-INST: las Z, r0
; CHECK-INST: las Z, r31
; CHECK-INST: las Z, r3

llvm/test/MC/AVR/inst-lat.s

; RUN: llvm-mc -triple avr -mattr=rmw -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -mattr=rmw -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=rmw < %s | llvm-objdump -d --mattr=rmw - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
lat Z, r13 lat Z, r13
lat Z, r0 lat Z, r0
lat Z, r31 lat Z, r31
lat Z, r3 lat Z, r3
; CHECK: lat Z, r13 ; encoding: [0xd7,0x92] ; CHECK: lat Z, r13 ; encoding: [0xd7,0x92]
; CHECK: lat Z, r0 ; encoding: [0x07,0x92] ; CHECK: lat Z, r0 ; encoding: [0x07,0x92]
; CHECK: lat Z, r31 ; encoding: [0xf7,0x93] ; CHECK: lat Z, r31 ; encoding: [0xf7,0x93]
; CHECK: lat Z, r3 ; encoding: [0x37,0x92] ; CHECK: lat Z, r3 ; encoding: [0x37,0x92]
; CHECK-INST: lat Z, r13
; CHECK-INST: lat Z, r0
; CHECK-INST: lat Z, r31
; CHECK-INST: lat Z, r3

llvm/test/MC/AVR/inst-lpm.s

; RUN: llvm-mc -triple avr -mattr=lpm,lpmx -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -mattr=lpm,lpmx -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=lpm,lpmx < %s | llvm-objdump -d --mattr=lpm,lpmx - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
lpm lpm
lpm r3, Z lpm r3, Z
lpm r23, Z lpm r23, Z
lpm r8, Z+ lpm r8, Z+
lpm r0, Z+ lpm r0, Z+
lpm r31, Z+
; CHECK: lpm ; encoding: [0xc8,0x95] ; CHECK: lpm ; encoding: [0xc8,0x95]
; CHECK: lpm r3, Z ; encoding: [0x34,0x90] ; CHECK: lpm r3, Z ; encoding: [0x34,0x90]
; CHECK: lpm r23, Z ; encoding: [0x74,0x91] ; CHECK: lpm r23, Z ; encoding: [0x74,0x91]
; CHECK: lpm r8, Z+ ; encoding: [0x85,0x90] ; CHECK: lpm r8, Z+ ; encoding: [0x85,0x90]
; CHECK: lpm r0, Z+ ; encoding: [0x05,0x90] ; CHECK: lpm r0, Z+ ; encoding: [0x05,0x90]
; CHECK: lpm r31, Z+ ; encoding: [0xf5,0x91]
; CHECK-INST: lpm
; CHECK-INST: lpm r3, Z
; CHECK-INST: lpm r23, Z
; CHECK-INST: lpm r8, Z+
; CHECK-INST: lpm r0, Z+
; CHECK-INST: lpm r31, Z+

llvm/test/MC/AVR/inst-spm.s

; RUN: llvm-mc -triple avr -mattr=spm,spmx -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -mattr=spm,spmx -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=spm,spmx < %s | llvm-objdump -d --mattr=spm,spmx - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
spm spm
spm Z+ spm Z+
; CHECK: spm ; encoding: [0xe8,0x95] ; CHECK: spm ; encoding: [0xe8,0x95]
; CHECK: spm Z+ ; encoding: [0xf8,0x95] ; CHECK: spm Z+ ; encoding: [0xf8,0x95]
; CHECK-INST: spm
; CHECK-INST: spm Z+

llvm/test/MC/AVR/inst-xch.s

; RUN: llvm-mc -triple avr -mattr=rmw -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -mattr=rmw -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=rmw < %s | llvm-objdump -d --mattr=rmw - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
xch Z, r13 xch Z, r13
xch Z, r0 xch Z, r0
xch Z, r31 xch Z, r31
xch Z, r3 xch Z, r3
; CHECK: xch Z, r13 ; encoding: [0xd4,0x92] ; CHECK: xch Z, r13 ; encoding: [0xd4,0x92]
; CHECK: xch Z, r0 ; encoding: [0x04,0x92] ; CHECK: xch Z, r0 ; encoding: [0x04,0x92]
; CHECK: xch Z, r31 ; encoding: [0xf4,0x93] ; CHECK: xch Z, r31 ; encoding: [0xf4,0x93]
; CHECK: xch Z, r3 ; encoding: [0x34,0x92] ; CHECK: xch Z, r3 ; encoding: [0x34,0x92]
; CHECK-INST: xch Z, r13
; CHECK-INST: xch Z, r0
; CHECK-INST: xch Z, r31
; CHECK-INST: xch Z, r3