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[PPC64] Change doubleword vector shift instructions from intrinsics to opcodes
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Authored by kbarton on Mar 4 2015, 11:33 AM.

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Summary

While reviewing the changes to Clang to add builtin support for the vsld, vsrd, and vsrad instructions, it was pointed out that the builtins are generating the LLVM opcodes (shl, lshr, and ashr) not calls to the intrinsics. This patch changes the implementation of the vsld, vsrd, and vsrad instructions from from intrinsics to VXForm_1 instructions and makes them legal with P8 Altivec. It also removes the definition of the int_ppc_altivec_vsld, int_ppc_altivec_vsrd, and int_ppc_altivec_vsrad intrinsics.

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kbarton updated this revision to Diff 21221.Mar 4 2015, 11:33 AM
kbarton retitled this revision from to [PPC64] Change doubleword vector shift instructions from intrinsics to opcodes.
kbarton updated this object.
kbarton edited the test plan for this revision. (Show Details)
kbarton added reviewers: hfinkel, wschmidt, seurer, nemanjai.
kbarton added a subscriber: Unknown Object (MLST).
wschmidt accepted this revision.Mar 4 2015, 12:40 PM
wschmidt edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Mar 4 2015, 12:40 PM
hfinkel accepted this revision.Mar 4 2015, 3:26 PM
hfinkel edited edge metadata.

LGTM too.

kbarton closed this revision.Mar 5 2015, 8:27 AM

Committed revision 231378.