[MLIR] Add missing colon after CHECKs.

[herhut]

Thanks for fixing these. Please change the description to contain the [MLIR] tag before landing.

mlir/test/IR/memory-ops.mlir

func @dma_ops() {
   dma_start %A[%c0], %Ah[%c0], %num_elements, %tag[%c0] : memref<256 x f32>, memref<256 x f32, 1>, memref<1 x f32>
   dma_wait %tag[%c0], %num_elements : memref<1 x f32>
   // CHECK: dma_start %0[%c0], %1[%c0], %c256, %2[%c0] : memref<256xf32>, memref<256xf32, 1>, memref<1xf32>
   // CHECK-NEXT:  dma_wait %2[%c0], %c256 : memref<1xf32>
 
   // DMA with strides
   dma_start %A[%c0], %Ah[%c0], %num_elements, %tag[%c0], %stride, %elt_per_stride : memref<256 x f32>, memref<256 x f32, 1>, memref<1 x f32>
   dma_wait %tag[%c0], %num_elements : memref<1 x f32>
-  // CHECK-NEXT  dma_start %0[%c0], %1[%c0], %c256, %2[%c0], %c32, %c16 : memref<256xf32>, memref<256xf32, 1>, memref<1xf32>
-  // CHECK-NEXT  dma_wait %2[%c0], %c256 : memref<1xf32>
+  // CHECK-NEXT:  dma_start %0[%c0], %1[%c0], %c256, %2[%c0], %c32, %c16 : memref<256xf32>, memref<256xf32, 1>, memref<1xf32>
+  // CHECK-NEXT:  dma_wait %2[%c0], %c256 : memref<1xf32>
 
   return
 }

mlir/test/Target/llvmir.mlir

llvm.func @callFenceInst() {
   llvm.fence syncscope("agent") release
   // CHECK: fence release
   llvm.fence release
   // CHECK: fence release
   llvm.fence syncscope("") release
   llvm.return
 }
 
-// CHECK-LABEL @passthrough
+// CHECK-LABEL: @passthrough
 // CHECK: #[[ATTR_GROUP:[0-9]*]]
 llvm.func @passthrough() attributes {passthrough = ["noinline", ["alignstack", "4"], "null-pointer-is-valid", ["foo", "bar"]]} {
   llvm.return
 }
 
 // CHECK: attributes #[[ATTR_GROUP]] = {
 // CHECK-DAG: noinline
 // CHECK-DAG: alignstack=4
 // CHECK-DAG: "null-pointer-is-valid"
 // CHECK-DAG: "foo"="bar"

mlir/test/Transforms/canonicalize.mlir

 ^bb2:
   // CHECK-NEXT: return
   dealloc %a: memref<4xf32>
   return
 }
 
 // CHECK-LABEL: func @dead_block_elim
 func @dead_block_elim() {
-  // CHECK-NOT ^bb
+  // CHECK-NOT: ^bb
   func @nested() {
     return
 
   ^bb1:
     return
   }
   return
 

mlir/test/Transforms/memref-bound-check.mlir

affine.for %j = 0 to 256 {
       %x  = affine.load %A[%idx0, %idx1, %idx2] : memref<128 x 64 x 64 x i32>
       // expected-error@-1 {{'affine.load' op memref out of upper bound access along dimension #1}}
       // expected-error@-2 {{'affine.load' op memref out of upper bound access along dimension #2}}
       // expected-error@-3 {{'affine.load' op memref out of upper bound access along dimension #3}}
       %idy0 = affine.apply affine_map<(d0, d1, d2) -> (d0 mod 128)>(%i, %j, %j)
       %idy1 = affine.apply affine_map<(d0, d1, d2) -> (d1 floordiv 4)>(%i, %j, %j)
       %idy2 = affine.apply affine_map<(d0, d1, d2) -> (d2 ceildiv 4 - 1)>(%i, %j, %j)
       affine.store %x, %A[%idy0, %idy1, %idy2] : memref<128 x 64 x 64 x i32> // expected-error {{'affine.store' op memref out of lower bound access along dimension #3}}
-    } // CHECK }
-  } // CHECK }
+    } // CHECK: }
+  } // CHECK: }
   return
 }
 
 // CHECK-LABEL: func @test_no_out_of_bounds()
 func @test_no_out_of_bounds() {
   %zero = constant 0 : index
   %A = alloc() : memref<257 x 256 x i32>
   %C = alloc() : memref<257 x i32>
   %B = alloc() : memref<1 x i32>
 
   affine.for %i = 0 to 256 {
     affine.for %j = 0 to 256 {
       // All of these accesses are in bound; check that no errors are emitted.
       // CHECK: %{{.*}} = affine.apply {{#map.*}}(%{{.*}}, %{{.*}})
       // CHECK-NEXT: %{{.*}} = affine.load %{{.*}}[%{{.*}}, %{{.*}}] : memref<257x256xi32>
       // CHECK-NEXT: %{{.*}} = affine.apply {{#map.*}}(%{{.*}}, %{{.*}})
       // CHECK-NEXT: %{{.*}} = affine.load %{{.*}}[%{{.*}}] : memref<1xi32>
       %idx0 = affine.apply affine_map<(d0, d1) -> ( 64 * (d0 ceildiv 64))>(%i, %j)
       // Without GCDTightenInequalities(), the upper bound on the region
       // accessed along first memref dimension would have come out as d0 <= 318
       // (instead of d0 <= 256), and led to a false positive out of bounds.
       %x  = affine.load %A[%idx0, %zero] : memref<257 x 256 x i32>
       %idy = affine.apply affine_map<(d0, d1) -> (d0 floordiv 256)>(%i, %i)
       %y  = affine.load %B[%idy] : memref<1 x i32>
-    } // CHECK-NEXT }
+    } // CHECK-NEXT: }
   }
   return
 }
 
 // CHECK-LABEL: func @mod_div
 func @mod_div() {
   %zero = constant 0 : index
   %A = alloc() : memref<128 x 64 x 64 x i32>

mlir/test/Transforms/pipeline-data-transfer.mlir

affine.for %i0 = 0 to 8 {
     // CHECK: affine.dma_wait [[TAG_ARG2]]
     // Prologue for DMA overlap on arg0, arg1 nested within i0
     // CHECK: [[BUF_ARG0:%[0-9]+]] = alloc() : memref<2x64x4xvector<8xf32>, 2>
     // CHECK: [[BUF_ARG1:%[0-9]+]] = alloc() : memref<2x64x4xvector<8xf32>, 2>
     // CHECK: [[TAG_ARG0:%[0-9]+]] = alloc() : memref<2x2xi32>
     // CHECK: [[TAG_ARG1:%[0-9]+]] = alloc() : memref<2x2xi32>
     // CHECK: affine.dma_start %{{.*}}[
     // CHECK: affine.dma_start %{{.*}}[
-    // CHECK-NEXT affine.for %{{.*}} = 1 to 8 {
+    // CHECK-NEXT: affine.for %{{.*}} = 1 to 8 {
     affine.for %i1 = 0 to 8 {
       %7 = affine.apply #map1(%i0, %i1)
       %8 = affine.apply #map2(%i1)
       affine.dma_start %arg0[%7, %c0], %0[%c0, %c0], %3[%c0], %num_elts : memref<512x32xvector<8xf32>>, memref<64x4xvector<8xf32>, 2>, memref<2xi32>
       affine.dma_start %arg1[%8, %c0], %1[%c0, %c0], %4[%c0], %num_elts : memref<512x32xvector<8xf32>>, memref<64x4xvector<8xf32>, 2>, memref<2xi32>
       affine.dma_wait %3[%c0], %num_elts : memref<2xi32>
       affine.dma_wait %4[%c0], %num_elts : memref<2xi32>
       // Steady state for DMA overlap on arg0, arg1

mlir/test/mlir-tblgen/pattern.mlir

 
 // CHECK-LABEL: verifyZeroResult
 func @verifyZeroResult(%arg0 : i32) {
   // CHECK: "test.op_i"(%arg0) : (i32) -> ()
   "test.op_h"(%arg0) : (i32) -> ()
   return
 }
 
-// CHECK-LABEL verifyZeroArg
+// CHECK-LABEL: verifyZeroArg
 func @verifyZeroArg() -> i32 {
   // CHECK: "test.op_k"() : () -> i32
   %0 = "test.op_j"() : () -> i32
   return %0 : i32
 }
 
 // CHECK-LABEL: testIgnoreArgMatch
 // CHECK-SAME: (%{{[a-z0-9]*}}: i32, %[[ARG1:[a-z0-9]*]]: i32