[SystemZ] Also accept ISD::USUBO in shouldFormOverflowOp()

[jonpa]

Summary

Forming sub with overflow should be beneficial on SystemZ, just like for additions.

When I tried doing this for i16 the code seems to get worse, so this is only done for i32 and i64.

Added tests also for the additions since I did not find any ones at the present.

(It seems we could have done (some of) this in SystemZElimCompare if we would recognize and handle Load Address in SystemZElimCompare, but IIRC that opcode isn't used that much for additions with an immediate.)

[uweigand]

Otherwise, LGTM. Thanks!

llvm/lib/Target/SystemZ/SystemZISelLowering.h

448

Why do you move it to the .cpp file? It still seems small enough to usefully inline ...

[jonpa]

Sorry, I see that dag-combine-05.ll now fails. This test does not seem to really test your patch anymore (38342a5), since if (on trunk) I remove the check in getAsCarry() the test still passes. I am not sure why that is exactly, but I changed the existing test to at least give the same input to isel (by inserting the i16 intrinsic into the test case since it's now no longer generated by CodeGenPrepare).

Moved function definition to header file.

[uweigand]

I see. I still agree it is preferable to only generate the overflow ops for types where they will be legal.

It also makes sense to still have the test case to something valid by using an explicit overflow op.

So overall, the patch LGTM. Thanks!

llvm/lib/Target/SystemZ/SystemZISelLowering.h

bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
                                       unsigned Align,
                                       MachineMemOperand::Flags Flags,
                                       bool *Fast) const override;
   bool isTruncateFree(Type *, Type *) const override;
   bool isTruncateFree(EVT, EVT) const override;
 
   bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
                             bool MathUsed) const override {
-    // Using overflow ops for overflow checks only should beneficial on
-    // SystemZ.
-    return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
+    // Form add and sub with overflow intrinsics regardless of any extra
+    // users of the math result.
+    return VT == MVT::i32 || VT == MVT::i64;
   }
 
   const char *getTargetNodeName(unsigned Opcode) const override;
   std::pair<unsigned, const TargetRegisterClass *>
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                StringRef Constraint, MVT VT) const override;
   TargetLowering::ConstraintType
   getConstraintType(StringRef Constraint) const override;
   TargetLowering::ConstraintWeight

llvm/test/CodeGen/SystemZ/codegenprepare-form-OF-ops.ll

+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -O3 | FileCheck %s
+;
+; Check that CodeGenPrepare transforms these functions to use
+; uadd.with.overflow / usub.with.overflow intrinsics so that the compare
+; instruction is eliminated.
+
+define i32 @uaddo_32(i32 %arg)  {
+; CHECK-LABEL: uaddo_32:
+; CHECK: alhsik  %r0, %r2, -1
+; CHECK: locrnle %r2, %r0
+; CHECK: br      %r14
+
+bb:
+  %tmp10 = icmp ne i32 %arg, 0
+  %tmp11 = add nsw i32 %arg, -1
+  %tmp12 = select i1 %tmp10, i32 %tmp11, i32 %arg
+  ret i32 %tmp12
+}
+
+define i64 @uaddo_64(i64 %arg)  {
+; CHECK-LABEL: uaddo_64:
+; CHECK: alghsik  %r0, %r2, -1
+; CHECK: locgrnle %r2, %r0
+; CHECK: br       %r14
+bb:
+  %tmp10 = icmp ne i64 %arg, 0
+  %tmp11 = add nsw i64 %arg, -1
+  %tmp12 = select i1 %tmp10, i64 %tmp11, i64 %arg
+  ret i64 %tmp12
+}
+
+define i32 @usubo_32(i32 %arg)  {
+; CHECK-LABEL: usubo_32:
+; CHECK: alhsik %r0, %r2, -1
+; CHECK: locrle %r2, %r0
+; CHECK: br     %r14
+bb:
+  %tmp10 = icmp eq i32 %arg, 0
+  %tmp11 = sub nsw i32 %arg, 1
+  %tmp12 = select i1 %tmp10, i32 %tmp11, i32 %arg
+  ret i32 %tmp12
+}
+
+define i64 @usubo_64(i64 %arg)  {
+; CHECK-LABEL: usubo_64:
+; CHECK: alghsik %r0, %r2, -1
+; CHECK: locgrle %r2, %r0
+; CHECK: br      %r14
+bb:
+  %tmp10 = icmp eq i64 %arg, 0
+  %tmp11 = sub nsw i64 %arg, 1
+  %tmp12 = select i1 %tmp10, i64 %tmp11, i64 %arg
+  ret i64 %tmp12
+}

llvm/test/CodeGen/SystemZ/dag-combine-05.ll

 ; CHECK-NEXT:    lochilh %r0, 1
 ; CHECK-NEXT:    ar %r0, %r1
 ; CHECK-NEXT:    st %r0, 0(%r4)
 ; CHECK-NEXT:    br %r14
 bb:
   %tmp = icmp ult i16 %arg0, 9616
   %tmp1 = zext i1 %tmp to i32
   %tmp2 = load i16, i16* %src
-  %tmp3 = add i16 %tmp2, -1
-  %tmp4 = icmp ne i16 %tmp2, 0
-  %tmp5 = zext i1 %tmp4 to i32
+  %0 = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 %tmp2, i16 -1)
+  %math = extractvalue { i16, i1 } %0, 0
+  %ov = extractvalue { i16, i1 } %0, 1
+  %tmp5 = zext i1 %ov to i32
   %tmp6 = add nuw nsw i32 %tmp5, %tmp1
   store i32 %tmp6, i32* %dst
   ret void
 }
+
+declare { i16, i1 } @llvm.uadd.with.overflow.i16(i16, i16) #1