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Differential D7205

[mips] Add __clear_cache() definition for non-Android systems
ClosedPublic

Authored by petarj on Jan 27 2015, 11:17 AM.

Details

Reviewers
joerg
Commits
rG08fc9e915817: [mips] Add __clear_cache() definition for non-Android systems
rCRT228767: [mips] Add __clear_cache() definition for non-Android systems
rL228767: [mips] Add __clear_cache() definition for non-Android systems
Summary

Make sure clear_cache() builtin has an appropriate definition for Linux.
Call syscall(NR_cacheflush, ...).

Diff Detail

Repository
rL LLVM

Event Timeline

petarj updated this revision to Diff 18831.Jan 27 2015, 11:17 AM
petarj retitled this revision from to [mips] Add __clear_cache() definition for non-Android systems.
petarj updated this object.
petarj edited the test plan for this revision. (Show Details)
petarj added a reviewer: joerg.
petarj added a subscriber: Unknown Object (MLST).
petarj added a comment.Feb 3 2015, 6:14 AM

OK to commit?

Closed by commit rL228767: [mips] Add __clear_cache() definition for non-Android systems (authored by petarj). · Explain WhyFeb 10 2015, 3:38 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
compiler-rt/
trunk/
lib/
builtins/
8 lines

Diff 19715

compiler-rt/trunk/lib/builtins/clear_cache.c

Show All 16 Lines#if defined(__FreeBSD__) && defined(__arm__)
#include <sys/types.h> #include <sys/types.h>
#include <machine/sysarch.h> #include <machine/sysarch.h>
#endif #endif
#if defined(__NetBSD__) && defined(__arm__) #if defined(__NetBSD__) && defined(__arm__)
#include <machine/sysarch.h> #include <machine/sysarch.h>
#endif #endif
#if defined(__ANDROID__) && defined(__mips__) #if defined(__mips__)
#include <sys/cachectl.h> #include <sys/cachectl.h>
#include <sys/syscall.h> #include <sys/syscall.h>
#ifdef __LP64__ #if defined(__ANDROID__) && defined(__LP64__)
/* /*
* clear_mips_cache - Invalidates instruction cache for Mips. * clear_mips_cache - Invalidates instruction cache for Mips.
*/ */
static void clear_mips_cache(const void* Addr, size_t Size) { static void clear_mips_cache(const void* Addr, size_t Size) {
asm volatile ( asm volatile (
".set push\n" ".set push\n"
".set noreorder\n" ".set noreorder\n"
".set noat\n" ".set noat\n"
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines #elif defined(__ANDROID__)
__asm __volatile("svc 0x0" : "=r"(start_reg) __asm __volatile("svc 0x0" : "=r"(start_reg)
: "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags) : "r0"); : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags) : "r0");
if (start_reg != 0) { if (start_reg != 0) {
compilerrt_abort(); compilerrt_abort();
} }
#else #else
compilerrt_abort(); compilerrt_abort();
#endif #endif
#elif defined(__ANDROID__) && defined(__mips__) #elif defined(__mips__)
const uintptr_t start_int = (uintptr_t) start; const uintptr_t start_int = (uintptr_t) start;
const uintptr_t end_int = (uintptr_t) end; const uintptr_t end_int = (uintptr_t) end;
#ifdef __LP64__ #if defined(__ANDROID__) && defined(__LP64__)
// Call synci implementation for short address range. // Call synci implementation for short address range.
const uintptr_t address_range_limit = 256; const uintptr_t address_range_limit = 256;
if ((end_int - start_int) <= address_range_limit) { if ((end_int - start_int) <= address_range_limit) {
clear_mips_cache(start, (end_int - start_int)); clear_mips_cache(start, (end_int - start_int));
} else { } else {
syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE); syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
} }
#else #else
Show All 33 Lines