[BPF] Enable relocation location for load/store/shifts

[yonghong-song]

Summary

Previous btf field relocation is always at assignment like
   r1 = 4
which is converted from an ld_imm64 instruction.

This patch did an optimization such that relocation
instruction might be load/store/shift. Specically, the
following insns may also have relocation, except BPF_MOV:
  LDB, LDH, LDW, LDD, STB, STH, STW, STD,
  LDB32, LDH32, LDW32, STB32, STH32, STW32,
  SLL, SRL, SRA

To accomplish this, a few BPF target specific
codegen only instructions are invented. They
are generated at backend BPF SimplifyPatchable phase,
which is at early llc phase when SSA form is available.
The new codegen only instructions will be converted to
real proper instructions at the codegen and BTF emission stage.

Note that, as revealed by a few tests, this optimization might
be actual generating more relocations:
Scenario 1:
  if (...) {
    ... __builtin_preserve_field_info(arg->b2, 0) ...
  } else {
    ... __builtin_preserve_field_info(arg->b2, 0) ...
  }
  Compiler could do CSE to only have one relocation. But if both
  of the above is translated into codegen internal instructions,
  the compiler will not be able to do that.
Scenario 2:
  offset = ... __builtin_preserve_field_info(arg->b2, 0) ...
  ...
  ...  offset ...
  ...  offset ...
  ...  offset ...
  For whatever reason, the compiler might be temporarily do copy
  propagation of the righthand of "offset" assignment like
  ...  __builtin_preserve_field_info(arg->b2, 0) ...
  ...  __builtin_preserve_field_info(arg->b2, 0) ...
  and CSE will be able to deduplicate later.
  But if these intrinsics are converted to BPF pseudo instructions,
  they will not be able to get deduplicated.

I do not expect we have big instruction count difference.
It may actually reduce instruction count since now relocation
is in deeper insn dependency chain.
For example, for test offset-reloc-fieldinfo-2.ll, this patch
generates 7 instead of 6 relocations for non-alu32 mode, but it
actually reduced instruction count from 29 to 26.

[anakryiko]

I implemented libbpf relocation patching support for new classes of instructions and tested against kernel selftests and runqslower program. All of those pass. Thanks a lot, this is going to improve BPF CO-RE experience immensely!

llvm/lib/Target/BPF/BPFInstrInfo.td

class LOAD<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern>
   let Inst{55-52} = addr{19-16};
   let Inst{47-32} = addr{15-0};
   let BPFClass = BPF_LDX;
 }
 
 class LOADi64<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
     : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
 
+let isCodeGenOnly = 1 in {
+  def CORE_MEM : TYPE_LD_ST<BPF_MEM.Value, BPF_W.Value,
+                            (outs GPR:$dst),
+                            (ins u64imm:$opcode, GPR:$src, u64imm:$offset),
+                            "$dst = core_mem($opcode, $src, $offset)",
+                            []>;
+  def CORE_ALU32_MEM : TYPE_LD_ST<BPF_MEM.Value, BPF_W.Value,
+                                  (outs GPR32:$dst),
+                                  (ins u64imm:$opcode, GPR:$src, u64imm:$offset),
+                                  "$dst = core_alu32_mem($opcode, $src, $offset)",
+                                  []>;
+  let Constraints = "$dst = $src" in {
+    def CORE_SHIFT : ALU_RR<BPF_ALU64, BPF_LSH,
+                             (outs GPR:$dst),
+                             (ins u64imm:$opcode, GPR:$src, u64imm:$offset),
+                             "$dst = core_shift($opcode, $src, $offset)",
+                             []>;
+  }
+}
 
 let Predicates = [BPFNoALU32] in {
   def LDW : LOADi64<BPF_W, "u32", zextloadi32>;
   def LDH : LOADi64<BPF_H, "u16", zextloadi16>;
   def LDB : LOADi64<BPF_B, "u8", zextloadi8>;
 }
 
 def LDD : LOADi64<BPF_DW, "u64", load>;

llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp

BPFMISimplifyPatchable() : MachineFunctionPass(ID) {
     initializeBPFMISimplifyPatchablePass(*PassRegistry::getPassRegistry());
   }
 
 private:
   // Initialize class variables.
   void initialize(MachineFunction &MFParm);
 
   bool removeLD(void);
+  void processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
+                        MachineInstr &MI, Register &SrcReg, Register &DstReg,
+                        const GlobalValue *GVal);
+  void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
+                     Register &SrcReg, const GlobalValue *GVal,
+                     bool doSrcRegProp);
+  void processInst(MachineRegisterInfo *MRI, MachineInstr *Inst,
+                   MachineOperand *RelocOp, const GlobalValue *GVal);
+  void checkADDrr(MachineRegisterInfo *MRI, MachineOperand *RelocOp,
+                  const GlobalValue *GVal);
+  void checkShift(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
+                  MachineOperand *RelocOp, const GlobalValue *GVal,
+                  unsigned Opcode);
 
 public:
   // Main entry point for this pass.
   bool runOnMachineFunction(MachineFunction &MF) override {
     if (!skipFunction(MF.getFunction())) {
       initialize(MF);
     }
     return removeLD();
   }
 };
 
 // Initialize class variables.
 void BPFMISimplifyPatchable::initialize(MachineFunction &MFParm) {
   MF = &MFParm;
   TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo();
   LLVM_DEBUG(dbgs() << "*** BPF simplify patchable insts pass ***\n\n");
 }
 
+void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI,
+    MachineOperand *RelocOp, const GlobalValue *GVal) {
+  const MachineInstr *Inst = RelocOp->getParent();
+  const MachineOperand *Op1 = &Inst->getOperand(1);
+  const MachineOperand *Op2 = &Inst->getOperand(2);
+  const MachineOperand *BaseOp = (RelocOp == Op1) ? Op2 : Op1;
+
+  // Go through all uses of %1 as in %1 = ADD_rr %2, %3
+  const MachineOperand Op0 = Inst->getOperand(0);
+  auto Begin = MRI->use_begin(Op0.getReg()), End = MRI->use_end();
+  decltype(End) NextI;
+  for (auto I = Begin; I != End; I = NextI) {
+    NextI = std::next(I);
+    // The candidate needs to have a unique definition.
+    if (!MRI->getUniqueVRegDef(I->getReg()))
+      continue;
+
+    MachineInstr *DefInst = I->getParent();
+    unsigned Opcode = DefInst->getOpcode();
+    unsigned COREOp;
+    if (Opcode == BPF::LDB || Opcode == BPF::LDH || Opcode == BPF::LDW ||
+        Opcode == BPF::LDD || Opcode == BPF::STB || Opcode == BPF::STH ||
+        Opcode == BPF::STW || Opcode == BPF::STD)
+      COREOp = BPF::CORE_MEM;
+    else if (Opcode == BPF::LDB32 || Opcode == BPF::LDH32 ||
+             Opcode == BPF::LDW32 || Opcode == BPF::STB32 ||
+             Opcode == BPF::STH32 || Opcode == BPF::STW32)
+      COREOp = BPF::CORE_ALU32_MEM;
+    else
+      continue;
+
+    // It must be a form of %1 = *(type *)(%2 + 0) or *(type *)(%2 + 0) = %1.
+    const MachineOperand &ImmOp = DefInst->getOperand(2);
+    if (!ImmOp.isImm() || ImmOp.getImm() != 0)
+      continue;
+
+    BuildMI(*DefInst->getParent(), *DefInst, DefInst->getDebugLoc(), TII->get(COREOp))
+        .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp)
+        .addGlobalAddress(GVal);
+    DefInst->eraseFromParent();
+  }
+}
+
+void BPFMISimplifyPatchable::checkShift(MachineRegisterInfo *MRI,
+    MachineBasicBlock &MBB, MachineOperand *RelocOp, const GlobalValue *GVal,
+    unsigned Opcode) {
+  // Relocation operand should be the operand #2.
+  MachineInstr *Inst = RelocOp->getParent();
+  if (RelocOp != &Inst->getOperand(2))
+    return;
+
+  BuildMI(MBB, *Inst, Inst->getDebugLoc(), TII->get(BPF::CORE_SHIFT))
+      .add(Inst->getOperand(0)).addImm(Opcode)
+      .add(Inst->getOperand(1)).addGlobalAddress(GVal);
+  Inst->eraseFromParent();
+}
+
+void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI,
+    MachineBasicBlock &MBB, MachineInstr &MI, Register &SrcReg,
+    Register &DstReg, const GlobalValue *GVal) {
+  if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) {
+    // We can optimize such a pattern:
+    //  %1:gpr = LD_imm64 @"llvm.s:0:4$0:2"
+    //  %2:gpr32 = LDW32 %1:gpr, 0
+    //  %3:gpr = SUBREG_TO_REG 0, %2:gpr32, %subreg.sub_32
+    //  %4:gpr = ADD_rr %0:gpr, %3:gpr
+    //  or similar patterns below for non-alu32 case.
+    auto Begin = MRI->use_begin(DstReg), End = MRI->use_end();
+    decltype(End) NextI;
+    for (auto I = Begin; I != End; I = NextI) {
+      NextI = std::next(I);
+      if (!MRI->getUniqueVRegDef(I->getReg()))
+        continue;
+
+      unsigned Opcode = I->getParent()->getOpcode();
+      if (Opcode == BPF::SUBREG_TO_REG) {
+        Register TmpReg = I->getParent()->getOperand(0).getReg();
+        processDstReg(MRI, TmpReg, DstReg, GVal, false);
+      }
+    }
+
+    BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg)
+        .addReg(SrcReg, 0, BPF::sub_32);
+    return;
+  }
+
+  // All uses of DstReg replaced by SrcReg
+  processDstReg(MRI, DstReg, SrcReg, GVal, true);
+}
+
+void BPFMISimplifyPatchable::processDstReg(MachineRegisterInfo *MRI,
+    Register &DstReg, Register &SrcReg, const GlobalValue *GVal,
+    bool doSrcRegProp) {
+  auto Begin = MRI->use_begin(DstReg), End = MRI->use_end();
+  decltype(End) NextI;
+  for (auto I = Begin; I != End; I = NextI) {
+    NextI = std::next(I);
+    if (doSrcRegProp)
+      I->setReg(SrcReg);
+
+    // The candidate needs to have a unique definition.
+    if (MRI->getUniqueVRegDef(I->getReg()))
+      processInst(MRI, I->getParent(), &*I, GVal);
+  }
+}
+
+// Check to see whether we could do some optimization
+// to attach relocation to downstream dependent instructions.
+// Two kinds of patterns are recognized below:
+// Pattern 1:
+//   %1 = LD_imm64 @"llvm.b:0:4$0:1"  <== patch_imm = 4
+//   %2 = LDD %1, 0  <== this insn will be removed
+//   %3 = ADD_rr %0, %2
+//   %4 = LDW[32] %3, 0 OR STW[32] %4, %3, 0
+//   The `%4 = ...` will be transformed to
+//      CORE_[ALU32_]MEM(%4, mem_opcode, %0, @"llvm.b:0:4$0:1")
+//   and later on, BTF emit phase will translate to
+//      %4 = LDW[32] %0, 4 STW[32] %4, %0, 4
+//   and attach a relocation to it.
+// Pattern 2:
+//    %15 = LD_imm64 @"llvm.t:5:63$0:2" <== relocation type 5
+//    %16 = LDD %15, 0   <== this insn will be removed
+//    %17 = SRA_rr %14, %16
+//    The `%17 = ...` will be transformed to
+//       %17 = CORE_SHIFT(SRA_ri, %14, @"llvm.t:5:63$0:2")
+//    and later on, BTF emit phase will translate to
+//       %r4 = SRA_ri %r4, 63
+void BPFMISimplifyPatchable::processInst(MachineRegisterInfo *MRI,
+    MachineInstr *Inst, MachineOperand *RelocOp, const GlobalValue *GVal) {
+  unsigned Opcode = Inst->getOpcode();
+  if (Opcode == BPF::ADD_rr)
+    checkADDrr(MRI, RelocOp, GVal);
+  else if (Opcode == BPF::SLL_rr)
+    checkShift(MRI, *Inst->getParent(), RelocOp, GVal, BPF::SLL_ri);
+  else if (Opcode == BPF::SRA_rr)
+    checkShift(MRI, *Inst->getParent(), RelocOp, GVal, BPF::SRA_ri);
+  else if (Opcode == BPF::SRL_rr)
+    checkShift(MRI, *Inst->getParent(), RelocOp, GVal, BPF::SRL_ri);
+}
+
 /// Remove unneeded Load instructions.
 bool BPFMISimplifyPatchable::removeLD() {
   MachineRegisterInfo *MRI = &MF->getRegInfo();
   MachineInstr *ToErase = nullptr;
   bool Changed = false;
 
   for (MachineBasicBlock &MBB : *MF) {
     for (MachineInstr &MI : MBB) {
for (MachineInstr &MI : MBB) {
       Register DstReg = MI.getOperand(0).getReg();
       Register SrcReg = MI.getOperand(1).getReg();
 
       MachineInstr *DefInst = MRI->getUniqueVRegDef(SrcReg);
       if (!DefInst)
         continue;
 
       bool IsCandidate = false;
+      const GlobalValue *GVal = nullptr;
       if (DefInst->getOpcode() == BPF::LD_imm64) {
         const MachineOperand &MO = DefInst->getOperand(1);
         if (MO.isGlobal()) {
-          const GlobalValue *GVal = MO.getGlobal();
+          GVal = MO.getGlobal();
           auto *GVar = dyn_cast<GlobalVariable>(GVal);
           if (GVar) {
             // Global variables representing structure offset or
             // patchable extern globals.
             if (GVar->hasAttribute(BPFCoreSharedInfo::AmaAttr)) {
               assert(MI.getOperand(2).getImm() == 0);
               IsCandidate = true;
             }
           }
         }
       }
 
       if (!IsCandidate)
         continue;
 
-      if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) {
-        BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg)
-            .addReg(SrcReg, 0, BPF::sub_32);
-      } else {
-        auto Begin = MRI->use_begin(DstReg), End = MRI->use_end();
-        decltype(End) NextI;
-        for (auto I = Begin; I != End; I = NextI) {
-          NextI = std::next(I);
-          I->setReg(SrcReg);
-        }
-      }
+      processCandidate(MRI, MBB, MI, SrcReg, DstReg, GVal);
 
       ToErase = &MI;
       Changed = true;
     }
   }
 
   return Changed;
 }

llvm/lib/Target/BPF/BTFDebug.h

 struct BTFLineInfo {
   MCSymbol *Label;      ///< MCSymbol identifying insn for the lineinfo
   uint32_t FileNameOff; ///< file name offset in the .BTF string table
   uint32_t LineOff;     ///< line offset in the .BTF string table
   uint32_t LineNum;     ///< the line number
   uint32_t ColumnNum;   ///< the column number
 };
 
-/// Represent one offset relocation.
+/// Represent one field relocation.
 struct BTFFieldReloc {
   const MCSymbol *Label;  ///< MCSymbol identifying insn for the reloc
   uint32_t TypeID;        ///< Type ID
   uint32_t OffsetNameOff; ///< The string to traverse types
   uint32_t RelocKind;     ///< What to patch the instruction
 };
 
 /// Collect and emit BTF information.
void constructLineInfo(const DISubprogram *SP, MCSymbol *Label, uint32_t Line,
                          uint32_t Column);
 
   /// Generate types and variables for globals.
   void processGlobals(bool ProcessingMapDef);
 
   /// Generate types for function prototypes.
   void processFuncPrototypes();
 
-  /// Generate one offset relocation record.
-  void generateFieldReloc(const MachineInstr *MI, const MCSymbol *ORSym,
-                           DIType *RootTy, StringRef AccessPattern);
+  /// Generate one field relocation record.
+  void generateFieldReloc(const MCSymbol *ORSym, DIType *RootTy,
+                          StringRef AccessPattern);
 
   /// Populating unprocessed struct type.
   unsigned populateStructType(const DIType *Ty);
 
-  /// Process LD_imm64 instructions.
-  void processLDimm64(const MachineInstr *MI);
+  /// Process relocation instructions.
+  void processReloc(const MachineOperand &MO);
 
   /// Emit common header of .BTF and .BTF.ext sections.
   void emitCommonHeader();
 
   /// Emit the .BTF section.
   void emitBTFSection();
 
   /// Emit the .BTF.ext section.

llvm/lib/Target/BPF/BTFDebug.cpp

unsigned BTFDebug::populateStructType(const DIType *Ty) {
   unsigned Id;
   visitTypeEntry(Ty, Id, false, false);
   for (const auto &TypeEntry : TypeEntries)
     TypeEntry->completeType(*this);
   return Id;
 }
 
 /// Generate a struct member field relocation.
-void BTFDebug::generateFieldReloc(const MachineInstr *MI,
-                                   const MCSymbol *ORSym, DIType *RootTy,
-                                   StringRef AccessPattern) {
+void BTFDebug::generateFieldReloc(const MCSymbol *ORSym, DIType *RootTy,
   unsigned RootId = populateStructType(RootTy);
   size_t FirstDollar = AccessPattern.find_first_of('$');
   size_t FirstColon = AccessPattern.find_first_of(':');
   size_t SecondColon = AccessPattern.find_first_of(':', FirstColon + 1);
   StringRef IndexPattern = AccessPattern.substr(FirstDollar + 1);
   StringRef RelocKindStr = AccessPattern.substr(FirstColon + 1,
       SecondColon - FirstColon);
   StringRef PatchImmStr = AccessPattern.substr(SecondColon + 1,
       FirstDollar - SecondColon);
 
   BTFFieldReloc FieldReloc;
   FieldReloc.Label = ORSym;
   FieldReloc.OffsetNameOff = addString(IndexPattern);
   FieldReloc.TypeID = RootId;
   FieldReloc.RelocKind = std::stoull(RelocKindStr);
   PatchImms[AccessPattern.str()] = std::stoul(PatchImmStr);
   FieldRelocTable[SecNameOff].push_back(FieldReloc);
 }
 
-void BTFDebug::processLDimm64(const MachineInstr *MI) {
-  // If the insn is an LD_imm64, the following two cases
-  // will generate an .BTF.ext record.
-  //
-  // If the insn is "r2 = LD_imm64 @__BTF_...",
-  // add this insn into the .BTF.ext FieldReloc subsection.
-  // Relocation looks like:
-  //  . SecName:
-  //    . InstOffset
-  //    . TypeID
-  //    . OffSetNameOff
-  // Later, the insn is replaced with "r2 = <offset>"
-  // where "<offset>" equals to the offset based on current
-  // type definitions.
-  //
-  // If the insn is "r2 = LD_imm64 @VAR" and VAR is
-  // a patchable external global, add this insn into the .BTF.ext
-  // ExternReloc subsection.
-  // Relocation looks like:
-  //  . SecName:
-  //    . InstOffset
-  //    . ExternNameOff
-  // Later, the insn is replaced with "r2 = <value>" or
-  // "LD_imm64 r2, <value>" where "<value>" = 0.
-
+void BTFDebug::processReloc(const MachineOperand &MO) {
   // check whether this is a candidate or not
-  const MachineOperand &MO = MI->getOperand(1);
   if (MO.isGlobal()) {
     const GlobalValue *GVal = MO.getGlobal();
     auto *GVar = dyn_cast<GlobalVariable>(GVal);
     if (GVar && GVar->hasAttribute(BPFCoreSharedInfo::AmaAttr)) {
       MCSymbol *ORSym = OS.getContext().createTempSymbol();
       OS.EmitLabel(ORSym);
 
       MDNode *MDN = GVar->getMetadata(LLVMContext::MD_preserve_access_index);
       DIType *Ty = dyn_cast<DIType>(MDN);
-      generateFieldReloc(MI, ORSym, Ty, GVar->getName());
+      generateFieldReloc(ORSym, Ty, GVar->getName());
     }
   }
 }
 
 void BTFDebug::beginInstruction(const MachineInstr *MI) {
   DebugHandlerBase::beginInstruction(MI);
 
   if (SkipInstruction || MI->isMetaInstruction() ||
       MI->getFlag(MachineInstr::FrameSetup))
     return;
 
   if (MI->isInlineAsm()) {
     // Count the number of register definitions to find the asm string.
     unsigned NumDefs = 0;
     for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
          ++NumDefs)
       ;
 
     // Skip this inline asm instruction if the asmstr is empty.
     const char *AsmStr = MI->getOperand(NumDefs).getSymbolName();
     if (AsmStr[0] == 0)
       return;
   }
 
-  if (MI->getOpcode() == BPF::LD_imm64)
-    processLDimm64(MI);
+  if (MI->getOpcode() == BPF::LD_imm64) {
+    // If the insn is "r2 = LD_imm64 @<an AmaAttr global>",
+    // add this insn into the .BTF.ext FieldReloc subsection.
+    // Relocation looks like:
+    //  . SecName:
+    //    . InstOffset
+    //    . TypeID
+    //    . OffSetNameOff
+    //    . RelocType
+    // Later, the insn is replaced with "r2 = <offset>"
+    // where "<offset>" equals to the offset based on current
+    // type definitions.
+    processReloc(MI->getOperand(1));
+  } else if (MI->getOpcode() == BPF::CORE_MEM ||
+             MI->getOpcode() == BPF::CORE_ALU32_MEM ||
+             MI->getOpcode() == BPF::CORE_SHIFT) {
+    // relocation insn is a load, store or shift insn.
+    processReloc(MI->getOperand(3));
+  }
 
   // Skip this instruction if no DebugLoc or the DebugLoc
   // is the same as the previous instruction.
   const DebugLoc &DL = MI->getDebugLoc();
   if (!DL || PrevInstLoc == DL) {
     // This instruction will be skipped, no LineInfo has
     // been generated, construct one based on function signature.
     if (LineInfoGenerated == false) {
if (MO.isGlobal()) {
         // Emit "mov ri, <imm>" for patched immediate.
         uint32_t Imm = PatchImms[GVar->getName().str()];
         OutMI.setOpcode(BPF::MOV_ri);
         OutMI.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
         OutMI.addOperand(MCOperand::createImm(Imm));
         return true;
       }
     }
+  } else if (MI->getOpcode() == BPF::CORE_MEM ||
+             MI->getOpcode() == BPF::CORE_ALU32_MEM ||
+             MI->getOpcode() == BPF::CORE_SHIFT) {
+    const MachineOperand &MO = MI->getOperand(3);
+    if (MO.isGlobal()) {
+      const GlobalValue *GVal = MO.getGlobal();
+      auto *GVar = dyn_cast<GlobalVariable>(GVal);
+      if (GVar && GVar->hasAttribute(BPFCoreSharedInfo::AmaAttr)) {
+        uint32_t Imm = PatchImms[GVar->getName().str()];
+        OutMI.setOpcode(MI->getOperand(1).getImm());
+        if (MI->getOperand(0).isImm())
+          OutMI.addOperand(MCOperand::createImm(MI->getOperand(0).getImm()));
+        else
+          OutMI.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
+        OutMI.addOperand(MCOperand::createReg(MI->getOperand(2).getReg()));
+        OutMI.addOperand(MCOperand::createImm(Imm));
+        return true;
+      }
+    }
   }
   return false;
 }
 
 void BTFDebug::processFuncPrototypes() {
   const Module *M = MMI->getModule();
   for (const Function &F : M->functions()) {
     const DISubprogram *SP = F.getSubprogram();

llvm/test/CodeGen/BPF/CORE/offset-reloc-end-load.ll

 entry:
   call void @llvm.dbg.value(metadata %struct.s* %arg, metadata !20, metadata !DIExpression()), !dbg !21
   %0 = tail call i32* @llvm.preserve.struct.access.index.p0i32.p0s_struct.ss(%struct.s* %arg, i32 1, i32 1), !dbg !22, !llvm.preserve.access.index !15
   %1 = load i32, i32* %0, align 4, !dbg !23, !tbaa !24
   ret i32 %1, !dbg !28
 }
 
 ; CHECK-LABEL: test
-; CHECK:       r2 = 4
-; CHECK:       r1 += r2
-; CHECK-ALU64: r0 = *(u32 *)(r1 + 0)
-; CHECK-ALU32: w0 = *(u32 *)(r1 + 0)
+; CHECK-ALU64: r0 = *(u32 *)(r1 + 4)
+; CHECK-ALU32: w0 = *(u32 *)(r1 + 4)
 ; CHECK:       exit
 ;
 ; CHECK:       .long   1                       # BTF_KIND_STRUCT(id = 2)
 ;
 ; CHECK:       .byte   115                     # string offset=1
 ; CHECK:       .ascii  ".text"                 # string offset=20
 ; CHECK:       .ascii  "0:1"                   # string offset=26
 ;

llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-1.ll

entry:
   %retval.0.in = select i1 %tobool, i64 %shr3, i64 %shr, !dbg !53
   %retval.0 = trunc i64 %retval.0.in to i32, !dbg !37
   call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0) #5, !dbg !54
   ret i32 %retval.0, !dbg !54
 }
 
 ; CHECK:             r{{[0-9]+}} = 4
 ; CHECK:             r{{[0-9]+}} = 4
-; CHECK:             r{{[0-9]+}} = 51
-; CHECK:             r{{[0-9]+}} = 60
+; CHECK:             r{{[0-9]+}} <<= 51
+; CHECK:             r{{[0-9]+}} s>>= 60
+; CHECK:             r{{[0-9]+}} >>= 60
 ; CHECK:             r{{[0-9]+}} = 1
 
 ; CHECK:             .byte   115                     # string offset=1
 ; CHECK:             .ascii  ".text"                 # string offset=30
 ; CHECK:             .ascii  "0:2"                   # string offset=73
 
 ; CHECK:             .long   16                      # FieldReloc
 ; CHECK-NEXT:        .long   30                      # Field reloc section string offset=30
-; CHECK-NEXT:        .long   5
+; CHECK-NEXT:        .long   6
 ; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
 ; CHECK-NEXT:        .long   2
 ; CHECK-NEXT:        .long   73
 ; CHECK-NEXT:        .long   0
 ; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
 ; CHECK-NEXT:        .long   2
 ; CHECK-NEXT:        .long   73
 ; CHECK-NEXT:        .long   1
 ; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
 ; CHECK-NEXT:        .long   2
 ; CHECK-NEXT:        .long   73
 ; CHECK-NEXT:        .long   4
 ; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
 ; CHECK-NEXT:        .long   2
 ; CHECK-NEXT:        .long   73
 ; CHECK-NEXT:        .long   5
 ; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
 ; CHECK-NEXT:        .long   2
 ; CHECK-NEXT:        .long   73
+; CHECK-NEXT:        .long   5
+; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
+; CHECK-NEXT:        .long   2
+; CHECK-NEXT:        .long   73
 ; CHECK-NEXT:        .long   3
 
 ; Function Attrs: argmemonly nounwind willreturn
 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
 
 ; Function Attrs: nounwind readnone
 declare i16* @llvm.preserve.struct.access.index.p0i16.p0s_struct.ss(%struct.s*, i32, i32) #2
 

llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2.ll

-; RUN: llc -march=bpfel -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK,CHECK-EL %s
-; RUN: llc -march=bpfeb -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK,CHECK-EB %s
-; RUN: llc -march=bpfel -mattr=+alu32 -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK,CHECK-EL %s
-; RUN: llc -march=bpfeb -mattr=+alu32 -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK,CHECK-EB %s
+; RUN: llc -march=bpfel -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK,CHECK-EL,CHECK64 %s
+; RUN: llc -march=bpfeb -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK,CHECK-EB,CHECK64 %s
+; RUN: llc -march=bpfel -mattr=+alu32 -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK,CHECK-EL,CHECK32 %s
+; RUN: llc -march=bpfeb -mattr=+alu32 -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK,CHECK-EB,CHECK32 %s
 ; Source code:
 ;   struct s {
 ;     int a;
 ;     int b1:9;
 ;     int b2:4;
 ;   };
 ;   enum {
 ;     FIELD_BYTE_OFFSET = 0,
sw.epilog:                                        ; preds = %entry, %sw.bb9, %sw.bb5, %sw.bb1, %sw.bb
   %shr15 = lshr i64 %shl, %sh_prom12, !dbg !79
   %retval.0.in = select i1 %tobool, i64 %shr15, i64 %shr, !dbg !79
   %retval.0 = trunc i64 %retval.0.in to i32, !dbg !41
   ret i32 %retval.0, !dbg !80
 }
 
 ; CHECK:             r{{[0-9]+}} = 4
 ; CHECK:             r{{[0-9]+}} = 4
-; CHECK-EL:          r{{[0-9]+}} = 51
-; CHECK-EB:          r{{[0-9]+}} = 41
-; CHECK:             r{{[0-9]+}} = 60
+; CHECK-EL:          r{{[0-9]+}} <<= 51
+; CHECK-EB:          r{{[0-9]+}} <<= 41
+; CHECK:             r{{[0-9]+}} s>>= 60
+; CHECK:             r{{[0-9]+}} >>= 60
 ; CHECK:             r{{[0-9]+}} = 1
 
 ; CHECK:             .long   1                       # BTF_KIND_STRUCT(id = 2)
 ; CHECK:             .byte   115                     # string offset=1
 ; CHECK:             .ascii  ".text"                 # string offset=30
 ; CHECK:             .ascii  "0:2"                   # string offset=36
 
 ; CHECK:             .long   16                      # FieldReloc
 ; CHECK-NEXT:        .long   30                      # Field reloc section string offset=30
-; CHECK-NEXT:        .long   5
+; CHECK32:           .long   6
+; CHECK64:           .long   7
 ; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
 ; CHECK-NEXT:        .long   2
 ; CHECK-NEXT:        .long   36
 ; CHECK-NEXT:        .long   0
 ; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
 ; CHECK-NEXT:        .long   2
 ; CHECK-NEXT:        .long   36
 ; CHECK-NEXT:        .long   1
+; CHECK64:           .long   .Ltmp{{[0-9]+}}
+; CHECK64:           .long   2
+; CHECK64:           .long   36
+; CHECK64:           .long   0
 ; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
 ; CHECK-NEXT:        .long   2
 ; CHECK-NEXT:        .long   36
 ; CHECK-NEXT:        .long   4
 ; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
 ; CHECK-NEXT:        .long   2
 ; CHECK-NEXT:        .long   36
 ; CHECK-NEXT:        .long   5
 ; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
 ; CHECK-NEXT:        .long   2
 ; CHECK-NEXT:        .long   36
+; CHECK-NEXT:        .long   5
+; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
+; CHECK-NEXT:        .long   2
+; CHECK-NEXT:        .long   36
 ; CHECK-NEXT:        .long   3
 
 ; Function Attrs: nounwind readnone
 declare i16* @llvm.preserve.struct.access.index.p0i16.p0s_struct.ss(%struct.s*, i32, i32) #1
 
 ; Function Attrs: nounwind readnone
 declare i32 @llvm.bpf.preserve.field.info.p0i16(i16*, i64) #1