[X86] Fix an 8 bit testb being selected when folding a volatile i32 load pattern.

[aemerson]

Summary

We're not allowed to narrow volatile memory accesses.

[craig.topper]

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

5150

@reames should this be !LoadN->isSimple()?

[reames]

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

5150

Yes.

Though, the approach taken with that hit a snag. I'm probably going to end up reverting a bunch of changes in that whole sequence as I didn't get legalization quite right and have to revisit the design. It's off in TOT.

[aemerson]

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

5150

I think I'm missing some context here. what patches are you referring to?

[craig.topper]

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

5150

These patches and llvm-dev thread.

https://reviews.llvm.org/D69219
https://reviews.llvm.org/D68419
https://reviews.llvm.org/D66309
http://lists.llvm.org/pipermail/llvm-dev/2019-August/134794.html

[aemerson]

Update patch to use !isSimple() instead of isVolatile().

[craig.topper]

LGTM

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

if (N0.getOpcode() == ISD::AND &&
 
       SDValue Imm = CurDAG->getTargetConstant(Mask, dl, VT);
       SDValue Reg = N0.getOperand(0);
 
       // Emit a testl or testw.
       MachineSDNode *NewNode;
       SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
       if (tryFoldLoad(Node, N0.getNode(), Reg, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
+        if (auto *LoadN = dyn_cast<LoadSDNode>(N0.getOperand(0).getNode())) {
+          if (!LoadN->isSimple()) {
+            unsigned NumVolBits = LoadN->getValueType(0).getSizeInBits();
+            if (MOpc == X86::TEST8mi && NumVolBits != 8)
+              break;
+            else if (MOpc == X86::TEST16mi && NumVolBits != 16)
+              break;
+            else if (MOpc == X86::TEST32mi && NumVolBits != 32)
+              break;
+          }
+        }
         SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm,
                           Reg.getOperand(0) };
         NewNode = CurDAG->getMachineNode(MOpc, dl, MVT::i32, MVT::Other, Ops);
         // Update the chain.
         ReplaceUses(Reg.getValue(1), SDValue(NewNode, 1));
         // Record the mem-refs
         CurDAG->setNodeMemRefs(NewNode,
                                {cast<LoadSDNode>(Reg)->getMemOperand()});

llvm/test/CodeGen/X86/select-testb-volatile-load.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s
+
+; This test checks that we don't try to narrow the volatile load by selecting
+; the pattern below into a testb instruction.
+
+define void @testb_volatile(i32 **%ptrptr) {
+; CHECK-LABEL: testb_volatile:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    movq (%rdi), %rax
+; CHECK-NEXT:    testl $1, (%rax)
+; CHECK-NEXT:    jne LBB0_1
+; CHECK-NEXT:  ## %bb.2: ## %exit
+; CHECK-NEXT:    movl $1, (%rax)
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  LBB0_1: ## %bb2
+; CHECK-NEXT:    movl $0, (%rax)
+; CHECK-NEXT:    retq
+entry:
+  %ptr = load i32*, i32** %ptrptr, align 8
+  %vol_load = load volatile i32, i32* %ptr, align 4
+  %and = and i32 %vol_load, 1
+  %cmp = icmp eq i32 %and, 0
+  br i1 %cmp, label %exit, label %bb2
+
+bb2:
+  store i32 0, i32 *%ptr, align 4
+  ret void
+
+exit:
+  store i32 1, i32 *%ptr, align 4
+  ret void
+}