[llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands.

[plotfi]

Summary

This patch makes it so that cases where multiple instructions that differ only in their ConstantInt or ConstantFP MachineOperand values no longer collide. For instance:

%0:_(s1) = G_CONSTANT i1 true
%1:_(s1) = G_CONSTANT i1 false
%2:_(s32) = G_FCONSTANT float 1.0
%3:_(s32) = G_FCONSTANT float 0.0

Prior to this patch the first two instructions would collide together. Also, the last two G_FCONSTANT instructions would also collide. Now they will no longer collide.

llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

 
 std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
   std::string S;
   raw_string_ostream OS(S);
 
   // Gets a hashable artifact from a given MachineOperand (ie an unsigned).
   auto GetHashableMO = [this](const MachineOperand &MO) -> unsigned {
     switch (MO.getType()) {
+    case MachineOperand::MO_CImmediate:
+      return hash_combine(MO.getType(), MO.getTargetFlags(),
+                          MO.getCImm()->getZExtValue());
+    case MachineOperand::MO_FPImmediate:
+      return hash_combine(
+          MO.getType(), MO.getTargetFlags(),
+          MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue());
     case MachineOperand::MO_Immediate:
       return MO.getImm();
     case MachineOperand::MO_TargetIndex:
       return MO.getOffset() | (MO.getTargetFlags() << 16);
     case MachineOperand::MO_Register:
       if (Register::isVirtualRegister(MO.getReg()))
         return MRI.getVRegDef(MO.getReg())->getOpcode();
       return MO.getReg();
 
     // We could explicitly handle all the types of the MachineOperand,
     // here but we can just return a common number until we find a
     // compelling test case where this is bad. The only side effect here
     // is contributing to a hash collision but there's enough information
     // (Opcodes,other registers etc) that this will likely not be a problem.
 
     // TODO: Handle the following Immediate/Index/ID/Predicate cases. They can
     // be hashed on in a stable manner.
-    case MachineOperand::MO_CImmediate:
-    case MachineOperand::MO_FPImmediate:
     case MachineOperand::MO_FrameIndex:
     case MachineOperand::MO_ConstantPoolIndex:
     case MachineOperand::MO_JumpTableIndex:
     case MachineOperand::MO_CFIIndex:
     case MachineOperand::MO_IntrinsicID:
     case MachineOperand::MO_Predicate:
 
     // In the cases below we havn't found a way to produce an artifact that will

llvm/test/CodeGen/MIR/Generic/CFPImmMIRCanonHash.mir

+# RUN: llc -run-pass mir-canonicalizer -o - %s | FileCheck %s
+---
+name: cimm_fpimm_hash_test
+body: |
+  bb.0:
+    ; CHECK: _1:_(s1) = G_CONSTANT i1 true
+    ; CHECK: _1:_(s1) = G_CONSTANT i1 false
+    ; CHECK: _1:_(s32) = G_FCONSTANT float
+    ; CHECK: _1:_(s32) = G_FCONSTANT float
+    %0:_(s1) = G_CONSTANT i1 true
+    %1:_(s1) = G_CONSTANT i1 false
+    %2:_(s32) = G_FCONSTANT float 1.0
+    %3:_(s32) = G_FCONSTANT float 0.0
+...