[llvm-exegesis][NFC] Rename ExegesisTarget::decrementLoopCounterAndLoop()

[courbet]

Summary

To decrementLoopCounterAndJump, and explicitely take the jump target.

llvm/trunk/tools/llvm-exegesis/lib/SnippetRepetitor.cpp

return [this, Instructions, MinInstructions](FunctionFiller &Filler) {
       // The live ins are: the loop counter, the registers that were setup by
       // the entry block, and entry block live ins.
       Loop.MBB->addLiveIn(LoopCounter);
       for (unsigned Reg : Filler.getRegistersSetUp())
         Loop.MBB->addLiveIn(Reg);
       for (const auto &LiveIn : Entry.MBB->liveins())
         Loop.MBB->addLiveIn(LiveIn);
       Loop.addInstructions(Instructions);
-      ET.decrementLoopCounterAndLoop(*Loop.MBB, State.getInstrInfo());
+      ET.decrementLoopCounterAndJump(*Loop.MBB, *Loop.MBB,
+                                     State.getInstrInfo());
 
       // Set up the exit basic block.
       Loop.MBB->addSuccessor(Exit.MBB, llvm::BranchProbability::getZero());
       Exit.addReturn();
     };
   }
 
   BitVector getReservedRegs() const override {

llvm/trunk/tools/llvm-exegesis/lib/Target.h

public:
   }
 
   // Returns a counter usable as a loop counter.
   virtual unsigned getLoopCounterRegister(const llvm::Triple &) const {
     return 0;
   }
 
   // Adds the code to decrement the loop counter and
-  virtual void decrementLoopCounterAndLoop(MachineBasicBlock &MBB,
+  virtual void decrementLoopCounterAndJump(MachineBasicBlock &MBB,
+                                           MachineBasicBlock &TargetMBB,
                                            const llvm::MCInstrInfo &MII) const {
     llvm_unreachable("decrementLoopCounterAndBranch() requires "
                      "getLoopCounterRegister() > 0");
   }
 
   // Returns a list of unavailable registers.
   // Targets can use this to prevent some registers to be automatically selected
   // for use in snippets.

llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp

private:
 
   void randomizeMCOperand(const Instruction &Instr, const Variable &Var,
                           llvm::MCOperand &AssignedValue,
                           const llvm::BitVector &ForbiddenRegs) const override;
 
   void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
                           unsigned Offset) const override;
 
-  void decrementLoopCounterAndLoop(MachineBasicBlock &MBB,
+  void decrementLoopCounterAndJump(MachineBasicBlock &MBB,
+                                   MachineBasicBlock &TargetMBB,
                                    const llvm::MCInstrInfo &MII) const override;
 
   std::vector<llvm::MCInst> setRegTo(const llvm::MCSubtargetInfo &STI,
                                      unsigned Reg,
                                      const llvm::APInt &Value) const override;
 
   ArrayRef<unsigned> getUnavailableRegisters() const override {
     return makeArrayRef(kUnavailableRegisters,
void ExegesisX86Target::fillMemoryOperands(InstructionTemplate &IT,
   };
   SetOp(MemOpIdx + 0, MCOperand::createReg(Reg));    // BaseReg
   SetOp(MemOpIdx + 1, MCOperand::createImm(1));      // ScaleAmt
   SetOp(MemOpIdx + 2, MCOperand::createReg(0));      // IndexReg
   SetOp(MemOpIdx + 3, MCOperand::createImm(Offset)); // Disp
   SetOp(MemOpIdx + 4, MCOperand::createReg(0));      // Segment
 }
 
-void ExegesisX86Target::decrementLoopCounterAndLoop(
-    MachineBasicBlock &MBB, const llvm::MCInstrInfo &MII) const {
+void ExegesisX86Target::decrementLoopCounterAndJump(
+    MachineBasicBlock &MBB, MachineBasicBlock &TargetMBB,
+    const llvm::MCInstrInfo &MII) const {
   BuildMI(&MBB, DebugLoc(), MII.get(X86::ADD64ri8))
       .addDef(kLoopCounterReg)
       .addUse(kLoopCounterReg)
       .addImm(-1);
   BuildMI(&MBB, DebugLoc(), MII.get(X86::JCC_1))
-      .addMBB(&MBB)
+      .addMBB(&TargetMBB)
       .addImm(X86::COND_NE);
 }
 
 std::vector<llvm::MCInst>
 ExegesisX86Target::setRegTo(const llvm::MCSubtargetInfo &STI, unsigned Reg,
                             const llvm::APInt &Value) const {
   if (llvm::X86::GR8RegClass.contains(Reg))
     return {loadImmediate(Reg, 8, Value)};