[ARM][LowOverheadLoops] Use tBcc when reverting

[samparker]

Summary

Check the branch target ranges and use a tBcc instead of t2Bcc when we can.

[dmgreen]

LGTM

llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp

if (!InsertPt) {
     LLVM_DEBUG(dbgs() << "ARM Loops: Start insertion point: " << *InsertPt);
 
   Expand(ML, Start, InsertPt, Dec, End, Revert);
   return true;
 }
 
 // WhileLoopStart holds the exit block, so produce a cmp lr, 0 and then a
 // beq that branches to the exit branch.
-// FIXME: Need to check that we're not trashing the CPSR when generating the
-// cmp. We could also try to generate a cbz if the value in LR is also in
+// TODO: We could also try to generate a cbz if the value in LR is also in
 // another low register.
 void ARMLowOverheadLoops::RevertWhile(MachineInstr *MI) const {
   LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp: " << *MI);
   MachineBasicBlock *MBB = MI->getParent();
   MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
                                     TII->get(ARM::t2CMPri));
   MIB.add(MI->getOperand(0));
   MIB.addImm(0);
   MIB.addImm(ARMCC::AL);
   MIB.addReg(ARM::NoRegister);
   
-  // TODO: Try to use tBcc instead
-  MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2Bcc));
+  MachineBasicBlock *DestBB = MI->getOperand(1).getMBB();
+  unsigned BrOpc = BBUtils->isBBInRange(MI, DestBB, 254) ?
+    ARM::tBcc : ARM::t2Bcc;
+
+  MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
   MIB.add(MI->getOperand(1));   // branch target
   MIB.addImm(ARMCC::EQ);        // condition code
   MIB.addReg(ARM::CPSR);
   MI->eraseFromParent();
 }
 
 // TODO: Check flags so that we can possibly generate a tSubs or tSub.
 void ARMLowOverheadLoops::RevertLoopDec(MachineInstr *MI) const {
   LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to sub: " << *MI);
   MachineBasicBlock *MBB = MI->getParent();
   MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
                                     TII->get(ARM::t2SUBri));
   MIB.addDef(ARM::LR);
   MIB.add(MI->getOperand(1));
   MIB.add(MI->getOperand(2));
   MIB.addImm(ARMCC::AL);
   MIB.addReg(0);
   MIB.addReg(0);
   MI->eraseFromParent();
 }
 
 // Generate a subs, or sub and cmp, and a branch instead of an LE.
-// FIXME: Need to check that we're not trashing the CPSR when generating
-// the cmp.
 void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI) const {
   LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp, br: " << *MI);
 
   // Create cmp
   MachineBasicBlock *MBB = MI->getParent();
   MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
                                     TII->get(ARM::t2CMPri));
   MIB.addReg(ARM::LR);
   MIB.addImm(0);
   MIB.addImm(ARMCC::AL);
   MIB.addReg(ARM::NoRegister);
 
-  // TODO Try to use tBcc instead.
+  MachineBasicBlock *DestBB = MI->getOperand(1).getMBB();
+  unsigned BrOpc = BBUtils->isBBInRange(MI, DestBB, 254) ?
+    ARM::tBcc : ARM::t2Bcc;
+
   // Create bne
-  MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2Bcc));
+  MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
   MIB.add(MI->getOperand(1));   // branch target
   MIB.addImm(ARMCC::NE);        // condition code
   MIB.addReg(ARM::CPSR);
   MI->eraseFromParent();
 }
 
 void ARMLowOverheadLoops::Expand(MachineLoop *ML, MachineInstr *Start,
                                  MachineInstr *InsertPt,

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll

 ; CHECK-MID: bb.3.for.header:
 ; CHECK-MID:   tB %bb.2
 
 ; CHECK-END: .LBB0_1:
 ; CHECK-END:   b .LBB0_3
 ; CHECK-END: .LBB0_2:
 ; CHECK-END:   sub.w lr, lr, #1
 ; CHECK-END:   cmp.w lr, #0
-; CHECK-END:   bne.w .LBB0_3
+; CHECK-END:   bne .LBB0_3
 ; CHECK-END:   b .LBB0_4
 ; CHECK-END: .LBB0_3:
 ; CHECK-END:   b .LBB0_2
 define void @check_loop_dec_brcond_combine(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) {
 entry:
   call void @llvm.set.loop.iterations.i32(i32 %N)
   br label %for.body.preheader
   

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir

 # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
 
 # CHECK-NOT: DoLoopStart
 # CHECK-NOT: DLS
 # CHECK: bb.1.for.body:
 # CHECK:   t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
-# CHECK:   t2Bcc %bb.3, 1, $cpsr
+# CHECK:   tBcc %bb.3, 1, $cpsr
 # CHECK:   tB %bb.2, 14, $noreg
 # CHECK: bb.2.for.cond.cleanup:
 # CHECK: bb.3.for.header:
 
 --- |
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
   

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir

 # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
 # CHECK-NOT: t2DLS
 # CHECK: bb.5.for.inc16:
 # CHECK:   $lr = t2SUBri killed renamable $lr, 1, 14
 # CHECK:   t2CMPri $lr, 0, 14
-# CHECK:   t2Bcc %bb.6, 1
+# CHECK:   tBcc %bb.6, 1
 # CHECK:   tB %bb.2
 # CHECK: bb.6.for.cond4.preheader:
 
 --- |
   ; ModuleID = 'revert-non-header.ll'
   source_filename = "revert-non-header.ll"
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir

 # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s --verify-machineinstrs -o - | FileCheck %s
 
 # CHECK: name: non_loop
 # CHECK: bb.0.entry:
 # CHECK:   tBcc %bb.2, 3
 # CHECK: bb.1.not.preheader:
 # CHECK:   t2CMPri renamable $lr, 0, 14
-# CHECK:   t2Bcc %bb.4, 0
+# CHECK:   tBcc %bb.4, 0
 # CHECK:   tB %bb.2
 # CHECK: bb.3.while.body:
 # CHECK:   t2CMPri $lr, 0, 14
-# CHECK:   t2Bcc %bb.3, 1
+# CHECK:   tBcc %bb.3, 1
 # CHECK:   tB %bb.4
 # CHECK: bb.4.while.end:
 
 --- |
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
   
   define void @non_loop(i16* nocapture %a, i16* nocapture readonly %b, i32 %N) {