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MachineScheduler: Fix missing dependency with multiple subreg defs
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Authored by arsenm on Sep 17 2019, 4:47 PM.

Details

Reviewers
qcolombet
Summary

If an instruction had multiple subregister defs, and one of them was
undef, this would improperly conclude all other lanes are
killed. There could still be other defs of those read-undef lanes in
other operands. This would improperly remove register uses from
CurrentVRegUses, so the visitation of later operands would not find
the necessary register dependency. This would also mean this would
fail or not depending on how different subregister def operands were
ordered.

On an undef subregister def, scan the instruction for other
subregister defs and avoid killing those.

This possibly should be deferring removing anything from
CurrentVRegUses until the entire instruction has been processed
instead.

Diff Detail

Event Timeline

arsenm created this revision.Sep 17 2019, 4:47 PM
qcolombet accepted this revision.Sep 19 2019, 4:22 PM

LGTM

lib/CodeGen/ScheduleDAGInstrs.cpp
406

typo: killd => killed

This revision is now accepted and ready to land.Sep 19 2019, 4:22 PM
arsenm closed this revision.Sep 19 2019, 5:07 PM
arsenm marked an inline comment as done.

r372362