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Differential D66547

[X86][BtVer2] Fix latency/throughput of scalar integer MUL instructions.
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Authored by andreadb on Aug 21 2019, 11:50 AM.

Details

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RKSimon
craig.topper
Commits
rGc9649eb9dab7: [X86][BtVer2] Fix latency/throughput of scalar integer MUL instructions.
rL369661: [X86][BtVer2] Fix latency/throughput of scalar integer MUL instructions.
Summary

Single operand MUL instructions that implicitly set EAX have the following latency/throughput profile (see below):

imul %cl              # latency: 3cy - uOPs: 1 - 1 JMul
imul %cx              # latency: 3cy - uOPs: 3 - 3 JMul
imul %ecx             # latency: 3cy - uOPs: 2 - 2 JMul
imul %rcx             # latency: 6cy - uOPs: 2 - 4 JMul

mul %cl               # latency: 3cy - uOPs: 1 - 1 JMul
mul %cx               # latency: 3cy - uOPs: 3 - 3 JMul
mul %ecx              # latency: 3cy - uOPs: 2 - 2 JMul
mul %rcx              # latency: 6cy - uOPs: 2 - 4 JMul

Excluding the 64bit variant, which has a latency of 6cy, every other instruction has a latency of 3cy. However, the number of decoded macro-opcodes (as well as the resource cyles) depend on the MUL size.

The two operand MULs have a more predictable profile (see below):

imul %dx, %dx         # latency: 3cy - uOPs: 1 - 1 JMul
imul %edx, %edx       # latency: 3cy - uOPs: 1 - 1 JMul
imul %rdx, %rdx       # latency: 6cy - uOPs: 1 - 4 JMul

imul $3, %dx, %dx     # latency: 4cy - uOPs: 2 - 2 JMul
imul $3, %ecx, %ecx   # latency: 3cy - uOPs: 1 - 1 JMul
imul $3, %rdx, %rdx   # latency: 6cy - uOPs: 1 - 4 JMul

This patch updates the values in the scheduling model based on those values.
I had to update quite a few tests because MUL was used in many tests...

Diff Detail

Event Timeline

andreadb created this revision.Aug 21 2019, 11:50 AM
Herald added a subscriber: gbedwell. · View Herald TranscriptAug 21 2019, 11:50 AM
RKSimon accepted this revision.Aug 22 2019, 7:38 AM

LGTM, I agree all the test changes are annoying but nothing to block this in any way.

This revision is now accepted and ready to land.Aug 22 2019, 7:38 AM
andreadb updated this revision to Diff 216623.Aug 22 2019, 7:45 AM

Patch rebased.

Closed by commit rL369661: [X86][BtVer2] Fix latency/throughput of scalar integer MUL instructions. (authored by adibiagio). · Explain WhyAug 22 2019, 8:21 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptAug 22 2019, 8:21 AM

Revision Contents

Diff 216442

lib/Target/X86/X86ScheduleBtVer2.td

Show First 20 Lines • Show All 191 Lines • ▼ Show 20 Lines
defm : JWriteResIntPair<WriteADC, [JALU01], 1, [2]>; defm : JWriteResIntPair<WriteADC, [JALU01], 1, [2]>;
defm : X86WriteRes<WriteBSWAP32, [JALU01], 1, [1], 1>; defm : X86WriteRes<WriteBSWAP32, [JALU01], 1, [1], 1>;
defm : X86WriteRes<WriteBSWAP64, [JALU01], 1, [1], 1>; defm : X86WriteRes<WriteBSWAP64, [JALU01], 1, [1], 1>;
defm : X86WriteRes<WriteCMPXCHG, [JALU01], 3, [3], 5>; defm : X86WriteRes<WriteCMPXCHG, [JALU01], 3, [3], 5>;
defm : X86WriteRes<WriteCMPXCHGRMW, [JALU01, JSAGU, JLAGU], 11, [3, 1, 1], 6>; defm : X86WriteRes<WriteCMPXCHGRMW, [JALU01, JSAGU, JLAGU], 11, [3, 1, 1], 6>;
defm : X86WriteRes<WriteXCHG, [JALU01], 1, [1], 1>; defm : X86WriteRes<WriteXCHG, [JALU01], 1, [1], 1>;
defm : JWriteResIntPair<WriteIMul8, [JALU1, JMul], 3, [1, 1], 2>; defm : JWriteResIntPair<WriteIMul8, [JALU1, JMul], 3, [1, 1], 1>;
defm : JWriteResIntPair<WriteIMul16, [JALU1, JMul], 3, [1, 1], 2>; defm : JWriteResIntPair<WriteIMul16, [JALU1, JMul], 3, [1, 3], 3>;
defm : JWriteResIntPair<WriteIMul16Imm, [JALU1, JMul], 3, [1, 1], 2>; defm : JWriteResIntPair<WriteIMul16Imm, [JALU1, JMul], 4, [1, 2], 2>;
defm : JWriteResIntPair<WriteIMul16Reg, [JALU1, JMul], 3, [1, 1], 2>; defm : JWriteResIntPair<WriteIMul16Reg, [JALU1, JMul], 3, [1, 1], 1>;
defm : JWriteResIntPair<WriteIMul32, [JALU1, JMul], 3, [1, 1], 2>; defm : JWriteResIntPair<WriteIMul32, [JALU1, JMul], 3, [1, 2], 2>;
defm : JWriteResIntPair<WriteIMul32Imm, [JALU1, JMul], 3, [1, 1], 2>; defm : JWriteResIntPair<WriteIMul32Imm, [JALU1, JMul], 3, [1, 1], 1>;
defm : JWriteResIntPair<WriteIMul32Reg, [JALU1, JMul], 3, [1, 1], 2>; defm : JWriteResIntPair<WriteIMul32Reg, [JALU1, JMul], 3, [1, 1], 1>;
defm : JWriteResIntPair<WriteIMul64, [JALU1, JMul], 6, [1, 4], 2>; defm : JWriteResIntPair<WriteIMul64, [JALU1, JMul], 6, [1, 4], 2>;
defm : JWriteResIntPair<WriteIMul64Imm, [JALU1, JMul], 6, [1, 4], 2>; defm : JWriteResIntPair<WriteIMul64Imm, [JALU1, JMul], 6, [1, 4], 1>;
defm : JWriteResIntPair<WriteIMul64Reg, [JALU1, JMul], 6, [1, 4], 2>; defm : JWriteResIntPair<WriteIMul64Reg, [JALU1, JMul], 6, [1, 4], 1>;
defm : X86WriteRes<WriteIMulH, [JALU1], 6, [4], 1>; defm : X86WriteRes<WriteIMulH, [JALU1], 6, [4], 1>;
defm : JWriteResIntPair<WriteDiv8, [JALU1, JDiv], 12, [1, 12], 1>; defm : JWriteResIntPair<WriteDiv8, [JALU1, JDiv], 12, [1, 12], 1>;
defm : JWriteResIntPair<WriteDiv16, [JALU1, JDiv], 17, [1, 17], 2>; defm : JWriteResIntPair<WriteDiv16, [JALU1, JDiv], 17, [1, 17], 2>;
defm : JWriteResIntPair<WriteDiv32, [JALU1, JDiv], 25, [1, 25], 2>; defm : JWriteResIntPair<WriteDiv32, [JALU1, JDiv], 25, [1, 25], 2>;
defm : JWriteResIntPair<WriteDiv64, [JALU1, JDiv], 41, [1, 41], 2>; defm : JWriteResIntPair<WriteDiv64, [JALU1, JDiv], 41, [1, 41], 2>;
defm : JWriteResIntPair<WriteIDiv8, [JALU1, JDiv], 12, [1, 12], 1>; defm : JWriteResIntPair<WriteIDiv8, [JALU1, JDiv], 12, [1, 12], 1>;
defm : JWriteResIntPair<WriteIDiv16, [JALU1, JDiv], 17, [1, 17], 2>; defm : JWriteResIntPair<WriteIDiv16, [JALU1, JDiv], 17, [1, 17], 2>;
▲ Show 20 Lines • Show All 716 Lines • Show Last 20 Lines

test/tools/llvm-mca/X86/BtVer2/clear-super-register-1.s

Show All 9 Lines
## The AND can start immediately after the LZCNT. ## The AND can start immediately after the LZCNT.
## It doesn't need to wait for the IMUL. ## It doesn't need to wait for the IMUL.
and %rcx, %rax and %rcx, %rax
bsf %rax, %rcx bsf %rax, %rcx
# CHECK: Iterations: 100 # CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 400 # CHECK-NEXT: Instructions: 400
# CHECK-NEXT: Total Cycles: 656 # CHECK-NEXT: Total Cycles: 655
# CHECK-NEXT: Total uOps: 1100 # CHECK-NEXT: Total uOps: 1000
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 1.68 # CHECK-NEXT: uOps Per Cycle: 1.53
# CHECK-NEXT: IPC: 0.61 # CHECK-NEXT: IPC: 0.61
# CHECK-NEXT: Block RThroughput: 5.5 # CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 6 4.00 imulq $5, %rcx, %rax # CHECK-NEXT: 1 6 4.00 imulq $5, %rcx, %rax
# CHECK-NEXT: 1 1 0.50 lzcntl %ecx, %eax # CHECK-NEXT: 1 1 0.50 lzcntl %ecx, %eax
# CHECK-NEXT: 1 1 0.50 andq %rcx, %rax # CHECK-NEXT: 1 1 0.50 andq %rcx, %rax
# CHECK-NEXT: 7 4 4.00 bsfq %rax, %rcx # CHECK-NEXT: 7 4 4.00 bsfq %rax, %rcx
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456 # CHECK-NEXT: 012345
# CHECK-NEXT: Index 0123456789 # CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeeeeeER . .. imulq $5, %rcx, %rax # CHECK: [0,0] DeeeeeeER . . imulq $5, %rcx, %rax
# CHECK-NEXT: [0,1] .DeE----R . .. lzcntl %ecx, %eax # CHECK-NEXT: [0,1] DeE-----R . . lzcntl %ecx, %eax
# CHECK-NEXT: [0,2] .D=eE----R. .. andq %rcx, %rax # CHECK-NEXT: [0,2] .DeE-----R. . andq %rcx, %rax
# CHECK-NEXT: [0,3] . D=eeeeER. .. bsfq %rax, %rcx # CHECK-NEXT: [0,3] . DeeeeE-R. . bsfq %rax, %rcx
# CHECK-NEXT: [1,0] . .D=eeeeeeER. imulq $5, %rcx, %rax # CHECK-NEXT: [1,0] . D=eeeeeeER. imulq $5, %rcx, %rax
# CHECK-NEXT: [1,1] . . D=eE----R. lzcntl %ecx, %eax # CHECK-NEXT: [1,1] . .D=eE----R. lzcntl %ecx, %eax
# CHECK-NEXT: [1,2] . . D==eE----R andq %rcx, %rax # CHECK-NEXT: [1,2] . .D==eE----R andq %rcx, %rax
# CHECK-NEXT: [1,3] . . D==eeeeER bsfq %rax, %rcx # CHECK-NEXT: [1,3] . . D==eeeeER bsfq %rax, %rcx
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 2 1.5 0.5 0.0 imulq $5, %rcx, %rax # CHECK-NEXT: 0. 2 1.5 0.5 0.0 imulq $5, %rcx, %rax
# CHECK-NEXT: 1. 2 1.5 1.0 4.0 lzcntl %ecx, %eax # CHECK-NEXT: 1. 2 1.5 1.0 4.5 lzcntl %ecx, %eax
# CHECK-NEXT: 2. 2 2.5 0.0 4.0 andq %rcx, %rax # CHECK-NEXT: 2. 2 2.0 0.0 4.5 andq %rcx, %rax
# CHECK-NEXT: 3. 2 2.5 0.0 0.0 bsfq %rax, %rcx # CHECK-NEXT: 3. 2 2.0 0.0 0.5 bsfq %rax, %rcx

test/tools/llvm-mca/X86/BtVer2/cmpxchg-read-advance.s

Show All 20 Lines
lock cmpxchgq %rcx, (%rdx) lock cmpxchgq %rcx, (%rdx)
# LLVM-MCA-END # LLVM-MCA-END
# CHECK: [0] Code Region # CHECK: [0] Code Region
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2 # CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 17 # CHECK-NEXT: Total Cycles: 17
# CHECK-NEXT: Total uOps: 8 # CHECK-NEXT: Total uOps: 7
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.47 # CHECK-NEXT: uOps Per Cycle: 0.41
# CHECK-NEXT: IPC: 0.12 # CHECK-NEXT: IPC: 0.12
# CHECK-NEXT: Block RThroughput: 4.0 # CHECK-NEXT: Block RThroughput: 4.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 6 4.00 imulq %rax, %rax # CHECK-NEXT: 1 6 4.00 imulq %rax, %rax
# CHECK-NEXT: 6 11 1.50 * * cmpxchgq %rcx, (%rdx) # CHECK-NEXT: 6 11 1.50 * * cmpxchgq %rcx, (%rdx)
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - JALU0 # CHECK-NEXT: [0] - JALU0
# CHECK-NEXT: [1] - JALU1 # CHECK-NEXT: [1] - JALU1
# CHECK-NEXT: [2] - JDiv # CHECK-NEXT: [2] - JDiv
# CHECK-NEXT: [3] - JFPA # CHECK-NEXT: [3] - JFPA
# CHECK-NEXT: [4] - JFPM # CHECK-NEXT: [4] - JFPM
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# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rax # CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rax
# CHECK-NEXT: 1. 1 3.0 0.0 0.0 cmpxchgq %rcx, (%rdx) # CHECK-NEXT: 1. 1 3.0 0.0 0.0 cmpxchgq %rcx, (%rdx)
# CHECK: [1] Code Region # CHECK: [1] Code Region
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2 # CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 17 # CHECK-NEXT: Total Cycles: 17
# CHECK-NEXT: Total uOps: 8 # CHECK-NEXT: Total uOps: 7
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.47 # CHECK-NEXT: uOps Per Cycle: 0.41
# CHECK-NEXT: IPC: 0.12 # CHECK-NEXT: IPC: 0.12
# CHECK-NEXT: Block RThroughput: 4.0 # CHECK-NEXT: Block RThroughput: 4.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 6 4.00 imulq %rcx, %rcx # CHECK-NEXT: 1 6 4.00 imulq %rcx, %rcx
# CHECK-NEXT: 6 11 1.50 * * cmpxchgq %rcx, (%rdx) # CHECK-NEXT: 6 11 1.50 * * cmpxchgq %rcx, (%rdx)
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - JALU0 # CHECK-NEXT: [0] - JALU0
# CHECK-NEXT: [1] - JALU1 # CHECK-NEXT: [1] - JALU1
# CHECK-NEXT: [2] - JDiv # CHECK-NEXT: [2] - JDiv
# CHECK-NEXT: [3] - JFPA # CHECK-NEXT: [3] - JFPA
# CHECK-NEXT: [4] - JFPM # CHECK-NEXT: [4] - JFPM
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# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rcx, %rcx # CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rcx, %rcx
# CHECK-NEXT: 1. 1 3.0 0.0 0.0 cmpxchgq %rcx, (%rdx) # CHECK-NEXT: 1. 1 3.0 0.0 0.0 cmpxchgq %rcx, (%rdx)
# CHECK: [2] Code Region # CHECK: [2] Code Region
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2 # CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 23 # CHECK-NEXT: Total Cycles: 23
# CHECK-NEXT: Total uOps: 8 # CHECK-NEXT: Total uOps: 7
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.35 # CHECK-NEXT: uOps Per Cycle: 0.30
# CHECK-NEXT: IPC: 0.09 # CHECK-NEXT: IPC: 0.09
# CHECK-NEXT: Block RThroughput: 17.0 # CHECK-NEXT: Block RThroughput: 17.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 6 4.00 imulq %rax, %rax # CHECK-NEXT: 1 6 4.00 imulq %rax, %rax
# CHECK-NEXT: 6 17 17.00 * * lock cmpxchgq %rcx, (%rdx) # CHECK-NEXT: 6 17 17.00 * * lock cmpxchgq %rcx, (%rdx)
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - JALU0 # CHECK-NEXT: [0] - JALU0
# CHECK-NEXT: [1] - JALU1 # CHECK-NEXT: [1] - JALU1
# CHECK-NEXT: [2] - JDiv # CHECK-NEXT: [2] - JDiv
# CHECK-NEXT: [3] - JFPA # CHECK-NEXT: [3] - JFPA
# CHECK-NEXT: [4] - JFPM # CHECK-NEXT: [4] - JFPM
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# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rax # CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rax
# CHECK-NEXT: 1. 1 3.0 0.0 0.0 lock cmpxchgq %rcx, (%rdx) # CHECK-NEXT: 1. 1 3.0 0.0 0.0 lock cmpxchgq %rcx, (%rdx)
# CHECK: [3] Code Region # CHECK: [3] Code Region
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2 # CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 23 # CHECK-NEXT: Total Cycles: 23
# CHECK-NEXT: Total uOps: 8 # CHECK-NEXT: Total uOps: 7
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.35 # CHECK-NEXT: uOps Per Cycle: 0.30
# CHECK-NEXT: IPC: 0.09 # CHECK-NEXT: IPC: 0.09
# CHECK-NEXT: Block RThroughput: 17.0 # CHECK-NEXT: Block RThroughput: 17.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 6 4.00 imulq %rcx, %rcx # CHECK-NEXT: 1 6 4.00 imulq %rcx, %rcx
# CHECK-NEXT: 6 17 17.00 * * lock cmpxchgq %rcx, (%rdx) # CHECK-NEXT: 6 17 17.00 * * lock cmpxchgq %rcx, (%rdx)
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - JALU0 # CHECK-NEXT: [0] - JALU0
# CHECK-NEXT: [1] - JALU1 # CHECK-NEXT: [1] - JALU1
# CHECK-NEXT: [2] - JDiv # CHECK-NEXT: [2] - JDiv
# CHECK-NEXT: [3] - JFPA # CHECK-NEXT: [3] - JFPA
# CHECK-NEXT: [4] - JFPM # CHECK-NEXT: [4] - JFPM
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test/tools/llvm-mca/X86/BtVer2/dependency-breaking-sbb-2.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s
# perf stat reports a throughput of 1.51 IPC for this block of code. # perf stat reports a throughput of 1.51 IPC for this block of code.
# The SBB does not depend on the value of register EAX. That means, it doesn't # The SBB does not depend on the value of register EAX. That means, it doesn't
# have to wait for the IMUL to write-back on EAX. However, it still depends on # have to wait for the IMUL to write-back on EAX. However, it still depends on
# the ADD for EFLAGS. # the ADD for EFLAGS.
imul %edx, %eax imul %edx, %eax
add %edx, %edx add %edx, %edx
sbb %eax, %eax sbb %eax, %eax
# CHECK: Iterations: 1500 # CHECK: Iterations: 1500
# CHECK-NEXT: Instructions: 4500 # CHECK-NEXT: Instructions: 4500
# CHECK-NEXT: Total Cycles: 3007 # CHECK-NEXT: Total Cycles: 3006
# CHECK-NEXT: Total uOps: 6000 # CHECK-NEXT: Total uOps: 4500
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 2.00 # CHECK-NEXT: uOps Per Cycle: 1.50
# CHECK-NEXT: IPC: 1.50 # CHECK-NEXT: IPC: 1.50
# CHECK-NEXT: Block RThroughput: 2.0 # CHECK-NEXT: Block RThroughput: 1.5
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 3 1.00 imull %edx, %eax # CHECK-NEXT: 1 3 1.00 imull %edx, %eax
# CHECK-NEXT: 1 1 0.50 addl %edx, %edx # CHECK-NEXT: 1 1 0.50 addl %edx, %edx
# CHECK-NEXT: 1 1 1.00 sbbl %eax, %eax # CHECK-NEXT: 1 1 1.00 sbbl %eax, %eax
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - JALU0 # CHECK-NEXT: [0] - JALU0
# CHECK-NEXT: [1] - JALU1 # CHECK-NEXT: [1] - JALU1
# CHECK-NEXT: [2] - JDiv # CHECK-NEXT: [2] - JDiv
# CHECK-NEXT: [3] - JFPA # CHECK-NEXT: [3] - JFPA
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - addl %edx, %edx # CHECK-NEXT: - 1.00 - - - - - - - - - - - - addl %edx, %edx
# CHECK-NEXT: 2.00 - - - - - - - - - - - - - sbbl %eax, %eax # CHECK-NEXT: 2.00 - - - - - - - - - - - - - sbbl %eax, %eax
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 01 # CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789 # CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeeER .. imull %edx, %eax # CHECK: [0,0] DeeeER .. imull %edx, %eax
# CHECK-NEXT: [0,1] .DeE-R .. addl %edx, %edx # CHECK-NEXT: [0,1] DeE--R .. addl %edx, %edx
# CHECK-NEXT: [0,2] .D=eE-R .. sbbl %eax, %eax # CHECK-NEXT: [0,2] .DeE--R .. sbbl %eax, %eax
# CHECK-NEXT: [1,0] . D==eeeER.. imull %edx, %eax # CHECK-NEXT: [1,0] .D==eeeER .. imull %edx, %eax
# CHECK-NEXT: [1,1] . DeE---R.. addl %edx, %edx # CHECK-NEXT: [1,1] . DeE---R .. addl %edx, %edx
# CHECK-NEXT: [1,2] . D=eE---R. sbbl %eax, %eax # CHECK-NEXT: [1,2] . D=eE---R.. sbbl %eax, %eax
# CHECK-NEXT: [2,0] . D=eeeER. imull %edx, %eax # CHECK-NEXT: [2,0] . D==eeeER. imull %edx, %eax
# CHECK-NEXT: [2,1] . D=eE--R addl %edx, %edx # CHECK-NEXT: [2,1] . D=eE---R. addl %edx, %edx
# CHECK-NEXT: [2,2] . D==eE-R sbbl %eax, %eax # CHECK-NEXT: [2,2] . D=eE---R sbbl %eax, %eax
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 3 2.0 0.7 0.0 imull %edx, %eax # CHECK-NEXT: 0. 3 2.3 1.0 0.0 imull %edx, %eax
# CHECK-NEXT: 1. 3 1.3 1.3 2.0 addl %edx, %edx # CHECK-NEXT: 1. 3 1.3 1.0 2.7 addl %edx, %edx
# CHECK-NEXT: 2. 3 2.3 0.0 1.7 sbbl %eax, %eax # CHECK-NEXT: 2. 3 1.7 0.0 2.7 sbbl %eax, %eax

test/tools/llvm-mca/X86/BtVer2/partial-reg-update-2.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
imul %rax, %rbx imul %rax, %rbx
lzcnt %ax, %bx lzcnt %ax, %bx
add %ecx, %ebx add %ecx, %ebx
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3 # CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 11 # CHECK-NEXT: Total Cycles: 11
# CHECK-NEXT: Total uOps: 4 # CHECK-NEXT: Total uOps: 3
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.36 # CHECK-NEXT: uOps Per Cycle: 0.27
# CHECK-NEXT: IPC: 0.27 # CHECK-NEXT: IPC: 0.27
# CHECK-NEXT: Block RThroughput: 4.0 # CHECK-NEXT: Block RThroughput: 4.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 6 4.00 imulq %rax, %rbx # CHECK-NEXT: 1 6 4.00 imulq %rax, %rbx
# CHECK-NEXT: 1 1 0.50 lzcntw %ax, %bx # CHECK-NEXT: 1 1 0.50 lzcntw %ax, %bx
# CHECK-NEXT: 1 1 0.50 addl %ecx, %ebx # CHECK-NEXT: 1 1 0.50 addl %ecx, %ebx
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0 # CHECK-NEXT: 0
# CHECK-NEXT: Index 0123456789 # CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeeeeeER . imulq %rax, %rbx # CHECK: [0,0] DeeeeeeER . imulq %rax, %rbx
# CHECK-NEXT: [0,1] .D=====eER. lzcntw %ax, %bx # CHECK-NEXT: [0,1] D======eER. lzcntw %ax, %bx
# CHECK-NEXT: [0,2] .D======eER addl %ecx, %ebx # CHECK-NEXT: [0,2] .D======eER addl %ecx, %ebx
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rbx # CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rbx
# CHECK-NEXT: 1. 1 6.0 0.0 0.0 lzcntw %ax, %bx # CHECK-NEXT: 1. 1 7.0 0.0 0.0 lzcntw %ax, %bx
# CHECK-NEXT: 2. 1 7.0 0.0 0.0 addl %ecx, %ebx # CHECK-NEXT: 2. 1 7.0 0.0 0.0 addl %ecx, %ebx

test/tools/llvm-mca/X86/BtVer2/partial-reg-update-4.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
# perf stat reports a throughput of 0.60 IPC for this code snippet. # perf stat reports a throughput of 0.60 IPC for this code snippet.
# The lzcnt cannot execute in parallel with the imul because there is a false # The lzcnt cannot execute in parallel with the imul because there is a false
# dependency on %bx. # dependency on %bx.
imul %ax, %bx imul %ax, %bx
lzcnt %ax, %bx lzcnt %ax, %bx
add %cx, %bx add %cx, %bx
# CHECK: Iterations: 1500 # CHECK: Iterations: 1500
# CHECK-NEXT: Instructions: 4500 # CHECK-NEXT: Instructions: 4500
# CHECK-NEXT: Total Cycles: 7503 # CHECK-NEXT: Total Cycles: 7503
# CHECK-NEXT: Total uOps: 6000 # CHECK-NEXT: Total uOps: 4500
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.80 # CHECK-NEXT: uOps Per Cycle: 0.60
# CHECK-NEXT: IPC: 0.60 # CHECK-NEXT: IPC: 0.60
# CHECK-NEXT: Block RThroughput: 2.0 # CHECK-NEXT: Block RThroughput: 1.5
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 3 1.00 imulw %ax, %bx # CHECK-NEXT: 1 3 1.00 imulw %ax, %bx
# CHECK-NEXT: 1 1 0.50 lzcntw %ax, %bx # CHECK-NEXT: 1 1 0.50 lzcntw %ax, %bx
# CHECK-NEXT: 1 1 0.50 addw %cx, %bx # CHECK-NEXT: 1 1 0.50 addw %cx, %bx
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - JALU0 # CHECK-NEXT: [0] - JALU0
# CHECK-NEXT: [1] - JALU1 # CHECK-NEXT: [1] - JALU1
# CHECK-NEXT: [2] - JDiv # CHECK-NEXT: [2] - JDiv
# CHECK-NEXT: [3] - JFPA # CHECK-NEXT: [3] - JFPA
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# CHECK-NEXT: 1.00 - - - - - - - - - - - - - lzcntw %ax, %bx # CHECK-NEXT: 1.00 - - - - - - - - - - - - - lzcntw %ax, %bx
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - addw %cx, %bx # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - addw %cx, %bx
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 01234567 # CHECK-NEXT: 01234567
# CHECK-NEXT: Index 0123456789 # CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeeER . . . imulw %ax, %bx # CHECK: [0,0] DeeeER . . . imulw %ax, %bx
# CHECK-NEXT: [0,1] .D==eER . . . lzcntw %ax, %bx # CHECK-NEXT: [0,1] D===eER . . . lzcntw %ax, %bx
# CHECK-NEXT: [0,2] .D===eER . . . addw %cx, %bx # CHECK-NEXT: [0,2] .D===eER . . . addw %cx, %bx
# CHECK-NEXT: [1,0] . D===eeeER . . imulw %ax, %bx # CHECK-NEXT: [1,0] .D====eeeER . . imulw %ax, %bx
# CHECK-NEXT: [1,1] . D=====eER . . lzcntw %ax, %bx # CHECK-NEXT: [1,1] . D======eER . . lzcntw %ax, %bx
# CHECK-NEXT: [1,2] . D======eER . . addw %cx, %bx # CHECK-NEXT: [1,2] . D=======eER . . addw %cx, %bx
# CHECK-NEXT: [2,0] . D======eeeER . imulw %ax, %bx # CHECK-NEXT: [2,0] . D=======eeeER . imulw %ax, %bx
# CHECK-NEXT: [2,1] . D========eER. lzcntw %ax, %bx # CHECK-NEXT: [2,1] . D==========eER. lzcntw %ax, %bx
# CHECK-NEXT: [2,2] . D=========eER addw %cx, %bx # CHECK-NEXT: [2,2] . D==========eER addw %cx, %bx
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 3 4.0 0.3 0.0 imulw %ax, %bx # CHECK-NEXT: 0. 3 4.7 0.3 0.0 imulw %ax, %bx
# CHECK-NEXT: 1. 3 6.0 0.0 0.0 lzcntw %ax, %bx # CHECK-NEXT: 1. 3 7.3 0.0 0.0 lzcntw %ax, %bx
# CHECK-NEXT: 2. 3 7.0 0.0 0.0 addw %cx, %bx # CHECK-NEXT: 2. 3 7.7 0.0 0.0 addw %cx, %bx

test/tools/llvm-mca/X86/BtVer2/partial-reg-update-6.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
# perf stat reports a throughput of 0.60 IPC for this code snippet. # perf stat reports a throughput of 0.60 IPC for this code snippet.
# Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the # Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the
# imul. However, the folded load can start immediately. # imul. However, the folded load can start immediately.
# The last lzcnt has a false dependency on %cx. However, even in this case, the # The last lzcnt has a false dependency on %cx. However, even in this case, the
# folded load can start immediately. # folded load can start immediately.
imul %edx, %ecx imul %edx, %ecx
lzcnt (%rsp), %cx lzcnt (%rsp), %cx
lzcnt 2(%rsp), %cx lzcnt 2(%rsp), %cx
# CHECK: Iterations: 1500 # CHECK: Iterations: 1500
# CHECK-NEXT: Instructions: 4500 # CHECK-NEXT: Instructions: 4500
# CHECK-NEXT: Total Cycles: 7504 # CHECK-NEXT: Total Cycles: 7503
# CHECK-NEXT: Total uOps: 6000 # CHECK-NEXT: Total uOps: 4500
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.80 # CHECK-NEXT: uOps Per Cycle: 0.60
# CHECK-NEXT: IPC: 0.60 # CHECK-NEXT: IPC: 0.60
# CHECK-NEXT: Block RThroughput: 2.0 # CHECK-NEXT: Block RThroughput: 2.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 3 1.00 imull %edx, %ecx # CHECK-NEXT: 1 3 1.00 imull %edx, %ecx
# CHECK-NEXT: 1 4 1.00 * lzcntw (%rsp), %cx # CHECK-NEXT: 1 4 1.00 * lzcntw (%rsp), %cx
# CHECK-NEXT: 1 4 1.00 * lzcntw 2(%rsp), %cx # CHECK-NEXT: 1 4 1.00 * lzcntw 2(%rsp), %cx
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - JALU0 # CHECK-NEXT: [0] - JALU0
# CHECK-NEXT: [1] - JALU1 # CHECK-NEXT: [1] - JALU1
# CHECK-NEXT: [2] - JDiv # CHECK-NEXT: [2] - JDiv
# CHECK-NEXT: [3] - JFPA # CHECK-NEXT: [3] - JFPA
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# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imull %edx, %ecx # CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imull %edx, %ecx
# CHECK-NEXT: 1.00 - - - - - - 1.00 - - - - - - lzcntw (%rsp), %cx # CHECK-NEXT: 1.00 - - - - - - 1.00 - - - - - - lzcntw (%rsp), %cx
# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - lzcntw 2(%rsp), %cx # CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - lzcntw 2(%rsp), %cx
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 012345678 # CHECK-NEXT: 01234567
# CHECK-NEXT: Index 0123456789 # CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeeER . . . imull %edx, %ecx # CHECK: [0,0] DeeeER . . . imull %edx, %ecx
# CHECK-NEXT: [0,1] .DeeeeER . . . lzcntw (%rsp), %cx # CHECK-NEXT: [0,1] DeeeeER . . . lzcntw (%rsp), %cx
# CHECK-NEXT: [0,2] .D=eeeeER . . . lzcntw 2(%rsp), %cx # CHECK-NEXT: [0,2] .DeeeeER . . . lzcntw 2(%rsp), %cx
# CHECK-NEXT: [1,0] . D====eeeER . . imull %edx, %ecx # CHECK-NEXT: [1,0] .D====eeeER . . imull %edx, %ecx
# CHECK-NEXT: [1,1] . D===eeeeER . . lzcntw (%rsp), %cx # CHECK-NEXT: [1,1] . D===eeeeER . . lzcntw (%rsp), %cx
# CHECK-NEXT: [1,2] . D====eeeeER . . lzcntw 2(%rsp), %cx # CHECK-NEXT: [1,2] . D====eeeeER . . lzcntw 2(%rsp), %cx
# CHECK-NEXT: [2,0] . D=======eeeER . imull %edx, %ecx # CHECK-NEXT: [2,0] . D=======eeeER . imull %edx, %ecx
# CHECK-NEXT: [2,1] . D======eeeeER. lzcntw (%rsp), %cx # CHECK-NEXT: [2,1] . D=======eeeeER. lzcntw (%rsp), %cx
# CHECK-NEXT: [2,2] . D=======eeeeER lzcntw 2(%rsp), %cx # CHECK-NEXT: [2,2] . D=======eeeeER lzcntw 2(%rsp), %cx
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 3 4.7 0.3 0.0 imull %edx, %ecx # CHECK-NEXT: 0. 3 4.7 0.3 0.0 imull %edx, %ecx
# CHECK-NEXT: 1. 3 4.0 0.3 0.0 lzcntw (%rsp), %cx # CHECK-NEXT: 1. 3 4.3 0.0 0.0 lzcntw (%rsp), %cx
# CHECK-NEXT: 2. 3 5.0 0.0 0.0 lzcntw 2(%rsp), %cx # CHECK-NEXT: 2. 3 4.7 0.0 0.0 lzcntw 2(%rsp), %cx

test/tools/llvm-mca/X86/BtVer2/partial-reg-update-7.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -timeline -timeline-max-iterations=5 < %s | FileCheck %s # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -timeline -timeline-max-iterations=5 < %s | FileCheck %s
sete %r9b sete %r9b
movzbl %al, %eax movzbl %al, %eax
shll $2, %eax shll $2, %eax
imull %ecx, %eax imull %ecx, %eax
cmpl $1025, %eax cmpl $1025, %eax
# CHECK: Iterations: 100 # CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 500 # CHECK-NEXT: Instructions: 500
# CHECK-NEXT: Total Cycles: 504 # CHECK-NEXT: Total Cycles: 504
# CHECK-NEXT: Total uOps: 600 # CHECK-NEXT: Total uOps: 500
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 1.19 # CHECK-NEXT: uOps Per Cycle: 0.99
# CHECK-NEXT: IPC: 0.99 # CHECK-NEXT: IPC: 0.99
# CHECK-NEXT: Block RThroughput: 3.0 # CHECK-NEXT: Block RThroughput: 2.5
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1 0.50 sete %r9b # CHECK-NEXT: 1 1 0.50 sete %r9b
# CHECK-NEXT: 1 1 0.50 movzbl %al, %eax # CHECK-NEXT: 1 1 0.50 movzbl %al, %eax
# CHECK-NEXT: 1 1 0.50 shll $2, %eax # CHECK-NEXT: 1 1 0.50 shll $2, %eax
# CHECK-NEXT: 2 3 1.00 imull %ecx, %eax # CHECK-NEXT: 1 3 1.00 imull %ecx, %eax
# CHECK-NEXT: 1 1 0.50 cmpl $1025, %eax # CHECK-NEXT: 1 1 0.50 cmpl $1025, %eax
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - JALU0 # CHECK-NEXT: [0] - JALU0
# CHECK-NEXT: [1] - JALU1 # CHECK-NEXT: [1] - JALU1
# CHECK-NEXT: [2] - JDiv # CHECK-NEXT: [2] - JDiv
# CHECK-NEXT: [3] - JFPA # CHECK-NEXT: [3] - JFPA
# CHECK-NEXT: [4] - JFPM # CHECK-NEXT: [4] - JFPM
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# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456789 # CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 012345678 # CHECK-NEXT: Index 0123456789 012345678
# CHECK: [0,0] DeER . . . . . . sete %r9b # CHECK: [0,0] DeER . . . . . . sete %r9b
# CHECK-NEXT: [0,1] DeER . . . . . . movzbl %al, %eax # CHECK-NEXT: [0,1] DeER . . . . . . movzbl %al, %eax
# CHECK-NEXT: [0,2] .DeER. . . . . . shll $2, %eax # CHECK-NEXT: [0,2] .DeER. . . . . . shll $2, %eax
# CHECK-NEXT: [0,3] . DeeeER . . . . . imull %ecx, %eax # CHECK-NEXT: [0,3] .D=eeeER . . . . . imull %ecx, %eax
# CHECK-NEXT: [0,4] . D==eER . . . . . cmpl $1025, %eax # CHECK-NEXT: [0,4] . D===eER . . . . . cmpl $1025, %eax
# CHECK-NEXT: [1,0] . D===eER. . . . . sete %r9b # CHECK-NEXT: [1,0] . D====eER. . . . . sete %r9b
# CHECK-NEXT: [1,1] . D=eE-R. . . . . movzbl %al, %eax # CHECK-NEXT: [1,1] . D==eE-R. . . . . movzbl %al, %eax
# CHECK-NEXT: [1,2] . D==eE-R . . . . shll $2, %eax # CHECK-NEXT: [1,2] . D===eE-R . . . . shll $2, %eax
# CHECK-NEXT: [1,3] . D==eeeER . . . . imull %ecx, %eax # CHECK-NEXT: [1,3] . D===eeeER . . . . imull %ecx, %eax
# CHECK-NEXT: [1,4] . .D====eER . . . . cmpl $1025, %eax # CHECK-NEXT: [1,4] . D======eER . . . . cmpl $1025, %eax
# CHECK-NEXT: [2,0] . .D=====eER. . . . sete %r9b # CHECK-NEXT: [2,0] . D======eER. . . . sete %r9b
# CHECK-NEXT: [2,1] . . D===eE-R. . . . movzbl %al, %eax # CHECK-NEXT: [2,1] . D=====eE-R. . . . movzbl %al, %eax
# CHECK-NEXT: [2,2] . . D====eE-R . . . shll $2, %eax # CHECK-NEXT: [2,2] . .D=====eE-R . . . shll $2, %eax
# CHECK-NEXT: [2,3] . . D====eeeER . . . imull %ecx, %eax # CHECK-NEXT: [2,3] . .D======eeeER . . . imull %ecx, %eax
# CHECK-NEXT: [2,4] . . D======eER . . . cmpl $1025, %eax # CHECK-NEXT: [2,4] . . D========eER . . . cmpl $1025, %eax
# CHECK-NEXT: [3,0] . . D=======eER. . . sete %r9b # CHECK-NEXT: [3,0] . . D=========eER. . . sete %r9b
# CHECK-NEXT: [3,1] . . D=====eE-R. . . movzbl %al, %eax # CHECK-NEXT: [3,1] . . D=======eE-R. . . movzbl %al, %eax
# CHECK-NEXT: [3,2] . . D======eE-R . . shll $2, %eax # CHECK-NEXT: [3,2] . . D========eE-R . . shll $2, %eax
# CHECK-NEXT: [3,3] . . .D======eeeER . . imull %ecx, %eax # CHECK-NEXT: [3,3] . . D========eeeER . . imull %ecx, %eax
# CHECK-NEXT: [3,4] . . . D========eER . . cmpl $1025, %eax # CHECK-NEXT: [3,4] . . D===========eER . . cmpl $1025, %eax
# CHECK-NEXT: [4,0] . . . D=========eER. . sete %r9b # CHECK-NEXT: [4,0] . . D===========eER. . sete %r9b
# CHECK-NEXT: [4,1] . . . D=======eE-R. . movzbl %al, %eax # CHECK-NEXT: [4,1] . . D==========eE-R. . movzbl %al, %eax
# CHECK-NEXT: [4,2] . . . D========eE-R . shll $2, %eax # CHECK-NEXT: [4,2] . . .D==========eE-R . shll $2, %eax
# CHECK-NEXT: [4,3] . . . D========eeeER. imull %ecx, %eax # CHECK-NEXT: [4,3] . . .D===========eeeER. imull %ecx, %eax
# CHECK-NEXT: [4,4] . . . D==========eER cmpl $1025, %eax # CHECK-NEXT: [4,4] . . . D=============eER cmpl $1025, %eax
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 5 5.8 0.2 0.0 sete %r9b # CHECK-NEXT: 0. 5 7.0 0.2 0.0 sete %r9b
# CHECK-NEXT: 1. 5 4.2 0.2 0.8 movzbl %al, %eax # CHECK-NEXT: 1. 5 5.8 0.2 0.8 movzbl %al, %eax
# CHECK-NEXT: 2. 5 5.0 0.0 0.8 shll $2, %eax # CHECK-NEXT: 2. 5 6.2 0.0 0.8 shll $2, %eax
# CHECK-NEXT: 3. 5 5.0 0.0 0.0 imull %ecx, %eax # CHECK-NEXT: 3. 5 6.8 0.0 0.0 imull %ecx, %eax
# CHECK-NEXT: 4. 5 7.0 0.0 0.0 cmpl $1025, %eax # CHECK-NEXT: 4. 5 9.2 0.0 0.0 cmpl $1025, %eax

test/tools/llvm-mca/X86/BtVer2/partial-reg-update.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
imul %ax, %cx imul %ax, %cx
add %al, %cl add %al, %cl
add %ecx, %ebx add %ecx, %ebx
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3 # CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 8 # CHECK-NEXT: Total Cycles: 8
# CHECK-NEXT: Total uOps: 4 # CHECK-NEXT: Total uOps: 3
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.50 # CHECK-NEXT: uOps Per Cycle: 0.38
# CHECK-NEXT: IPC: 0.38 # CHECK-NEXT: IPC: 0.38
# CHECK-NEXT: Block RThroughput: 2.0 # CHECK-NEXT: Block RThroughput: 1.5
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 3 1.00 imulw %ax, %cx # CHECK-NEXT: 1 3 1.00 imulw %ax, %cx
# CHECK-NEXT: 1 1 0.50 addb %al, %cl # CHECK-NEXT: 1 1 0.50 addb %al, %cl
# CHECK-NEXT: 1 1 0.50 addl %ecx, %ebx # CHECK-NEXT: 1 1 0.50 addl %ecx, %ebx
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: Index 01234567 # CHECK-NEXT: Index 01234567
# CHECK: [0,0] DeeeER . imulw %ax, %cx # CHECK: [0,0] DeeeER . imulw %ax, %cx
# CHECK-NEXT: [0,1] .D==eER. addb %al, %cl # CHECK-NEXT: [0,1] D===eER. addb %al, %cl
# CHECK-NEXT: [0,2] .D===eER addl %ecx, %ebx # CHECK-NEXT: [0,2] .D===eER addl %ecx, %ebx
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulw %ax, %cx # CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulw %ax, %cx
# CHECK-NEXT: 1. 1 3.0 0.0 0.0 addb %al, %cl # CHECK-NEXT: 1. 1 4.0 0.0 0.0 addb %al, %cl
# CHECK-NEXT: 2. 1 4.0 0.0 0.0 addl %ecx, %ebx # CHECK-NEXT: 2. 1 4.0 0.0 0.0 addl %ecx, %ebx

test/tools/llvm-mca/X86/BtVer2/read-advance-2.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -resource-pressure=0 -timeline < %s | FileCheck %s # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -resource-pressure=0 -timeline < %s | FileCheck %s
imull %esi imull %esi
imull (%rdi) imull (%rdi)
# The second integer multiply can start at cycle 2 because the implicit reads # The second integer multiply can start at cycle 2 because the implicit reads
# can start after the load operand is evaluated. # can start after the load operand is evaluated.
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2 # CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 10 # CHECK-NEXT: Total Cycles: 11
# CHECK-NEXT: Total uOps: 4 # CHECK-NEXT: Total uOps: 4
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.40 # CHECK-NEXT: uOps Per Cycle: 0.36
# CHECK-NEXT: IPC: 0.20 # CHECK-NEXT: IPC: 0.18
# CHECK-NEXT: Block RThroughput: 2.0 # CHECK-NEXT: Block RThroughput: 4.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 3 1.00 imull %esi # CHECK-NEXT: 2 3 2.00 imull %esi
# CHECK-NEXT: 2 6 1.00 * imull (%rdi) # CHECK-NEXT: 2 6 2.00 * imull (%rdi)
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0
# CHECK-NEXT: Index 0123456789 # CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeeER . imull %esi # CHECK: [0,0] DeeeER . imull %esi
# CHECK-NEXT: [0,1] .DeeeeeeER imull (%rdi) # CHECK-NEXT: [0,1] .D=eeeeeeER imull (%rdi)
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imull %esi # CHECK-NEXT: 0. 1 1.0 1.0 0.0 imull %esi
# CHECK-NEXT: 1. 1 1.0 1.0 0.0 imull (%rdi) # CHECK-NEXT: 1. 1 2.0 2.0 0.0 imull (%rdi)

test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s

Show First 20 Lines • Show All 1,328 Lines • ▼ Show 20 Lines
# CHECK-NEXT: 1 12 12.00 U idivb %dil # CHECK-NEXT: 1 12 12.00 U idivb %dil
# CHECK-NEXT: 1 15 12.00 * U idivb (%rax) # CHECK-NEXT: 1 15 12.00 * U idivb (%rax)
# CHECK-NEXT: 2 17 17.00 U idivw %si # CHECK-NEXT: 2 17 17.00 U idivw %si
# CHECK-NEXT: 2 20 17.00 * U idivw (%rax) # CHECK-NEXT: 2 20 17.00 * U idivw (%rax)
# CHECK-NEXT: 2 25 25.00 U idivl %edx # CHECK-NEXT: 2 25 25.00 U idivl %edx
# CHECK-NEXT: 2 28 25.00 * U idivl (%rax) # CHECK-NEXT: 2 28 25.00 * U idivl (%rax)
# CHECK-NEXT: 2 41 41.00 U idivq %rcx # CHECK-NEXT: 2 41 41.00 U idivq %rcx
# CHECK-NEXT: 2 44 41.00 * U idivq (%rax) # CHECK-NEXT: 2 44 41.00 * U idivq (%rax)
# CHECK-NEXT: 2 3 1.00 imulb %dil # CHECK-NEXT: 1 3 1.00 imulb %dil
# CHECK-NEXT: 2 6 1.00 * imulb (%rax) # CHECK-NEXT: 1 6 1.00 * imulb (%rax)
# CHECK-NEXT: 2 3 1.00 imulw %di # CHECK-NEXT: 3 3 3.00 imulw %di
# CHECK-NEXT: 2 6 1.00 * imulw (%rax) # CHECK-NEXT: 3 6 3.00 * imulw (%rax)
# CHECK-NEXT: 2 3 1.00 imulw %si, %di # CHECK-NEXT: 1 3 1.00 imulw %si, %di
# CHECK-NEXT: 2 6 1.00 * imulw (%rax), %di # CHECK-NEXT: 1 6 1.00 * imulw (%rax), %di
# CHECK-NEXT: 2 3 1.00 imulw $511, %si, %di # CHECK-NEXT: 2 4 2.00 imulw $511, %si, %di
# CHECK-NEXT: 2 6 1.00 * imulw $511, (%rax), %di # CHECK-NEXT: 2 7 2.00 * imulw $511, (%rax), %di
# CHECK-NEXT: 2 3 1.00 imulw $7, %si, %di # CHECK-NEXT: 2 4 2.00 imulw $7, %si, %di
# CHECK-NEXT: 2 6 1.00 * imulw $7, (%rax), %di # CHECK-NEXT: 2 7 2.00 * imulw $7, (%rax), %di
# CHECK-NEXT: 2 3 1.00 imull %edi # CHECK-NEXT: 2 3 2.00 imull %edi
# CHECK-NEXT: 2 6 1.00 * imull (%rax) # CHECK-NEXT: 2 6 2.00 * imull (%rax)
# CHECK-NEXT: 2 3 1.00 imull %esi, %edi # CHECK-NEXT: 1 3 1.00 imull %esi, %edi
# CHECK-NEXT: 2 6 1.00 * imull (%rax), %edi # CHECK-NEXT: 1 6 1.00 * imull (%rax), %edi
# CHECK-NEXT: 2 3 1.00 imull $665536, %esi, %edi # CHECK-NEXT: 1 3 1.00 imull $665536, %esi, %edi
# CHECK-NEXT: 2 6 1.00 * imull $665536, (%rax), %edi # CHECK-NEXT: 1 6 1.00 * imull $665536, (%rax), %edi
# CHECK-NEXT: 2 3 1.00 imull $7, %esi, %edi # CHECK-NEXT: 1 3 1.00 imull $7, %esi, %edi
# CHECK-NEXT: 2 6 1.00 * imull $7, (%rax), %edi # CHECK-NEXT: 1 6 1.00 * imull $7, (%rax), %edi
# CHECK-NEXT: 2 6 4.00 imulq %rdi # CHECK-NEXT: 2 6 4.00 imulq %rdi
# CHECK-NEXT: 2 9 4.00 * imulq (%rax) # CHECK-NEXT: 2 9 4.00 * imulq (%rax)
# CHECK-NEXT: 2 6 4.00 imulq %rsi, %rdi # CHECK-NEXT: 1 6 4.00 imulq %rsi, %rdi
# CHECK-NEXT: 2 9 4.00 * imulq (%rax), %rdi # CHECK-NEXT: 1 9 4.00 * imulq (%rax), %rdi
# CHECK-NEXT: 2 6 4.00 imulq $665536, %rsi, %rdi # CHECK-NEXT: 1 6 4.00 imulq $665536, %rsi, %rdi
# CHECK-NEXT: 2 9 4.00 * imulq $665536, (%rax), %rdi # CHECK-NEXT: 1 9 4.00 * imulq $665536, (%rax), %rdi
# CHECK-NEXT: 2 6 4.00 imulq $7, %rsi, %rdi # CHECK-NEXT: 1 6 4.00 imulq $7, %rsi, %rdi
# CHECK-NEXT: 2 9 4.00 * imulq $7, (%rax), %rdi # CHECK-NEXT: 1 9 4.00 * imulq $7, (%rax), %rdi
# CHECK-NEXT: 1 100 0.50 U inb $7, %al # CHECK-NEXT: 1 100 0.50 U inb $7, %al
# CHECK-NEXT: 1 100 0.50 U inb %dx, %al # CHECK-NEXT: 1 100 0.50 U inb %dx, %al
# CHECK-NEXT: 1 100 0.50 U inw $7, %ax # CHECK-NEXT: 1 100 0.50 U inw $7, %ax
# CHECK-NEXT: 1 100 0.50 U inw %dx, %ax # CHECK-NEXT: 1 100 0.50 U inw %dx, %ax
# CHECK-NEXT: 1 100 0.50 U inl $7, %eax # CHECK-NEXT: 1 100 0.50 U inl $7, %eax
# CHECK-NEXT: 1 100 0.50 U inl %dx, %eax # CHECK-NEXT: 1 100 0.50 U inl %dx, %eax
# CHECK-NEXT: 1 1 0.50 incb %dil # CHECK-NEXT: 1 1 0.50 incb %dil
# CHECK-NEXT: 1 5 1.00 * * incb (%rax) # CHECK-NEXT: 1 5 1.00 * * incb (%rax)
Show All 40 Lines
# CHECK-NEXT: 1 4 1.00 * movswl (%rax), %edi # CHECK-NEXT: 1 4 1.00 * movswl (%rax), %edi
# CHECK-NEXT: 1 4 1.00 * movzwl (%rax), %edi # CHECK-NEXT: 1 4 1.00 * movzwl (%rax), %edi
# CHECK-NEXT: 1 1 0.50 movswq %ax, %rdi # CHECK-NEXT: 1 1 0.50 movswq %ax, %rdi
# CHECK-NEXT: 1 1 0.50 movzwq %ax, %rdi # CHECK-NEXT: 1 1 0.50 movzwq %ax, %rdi
# CHECK-NEXT: 1 4 1.00 * movswq (%rax), %rdi # CHECK-NEXT: 1 4 1.00 * movswq (%rax), %rdi
# CHECK-NEXT: 1 4 1.00 * movzwq (%rax), %rdi # CHECK-NEXT: 1 4 1.00 * movzwq (%rax), %rdi
# CHECK-NEXT: 1 1 0.50 movslq %eax, %rdi # CHECK-NEXT: 1 1 0.50 movslq %eax, %rdi
# CHECK-NEXT: 1 4 1.00 * movslq (%rax), %rdi # CHECK-NEXT: 1 4 1.00 * movslq (%rax), %rdi
# CHECK-NEXT: 2 3 1.00 mulb %dil # CHECK-NEXT: 1 3 1.00 mulb %dil
# CHECK-NEXT: 2 6 1.00 * mulb (%rax) # CHECK-NEXT: 1 6 1.00 * mulb (%rax)
# CHECK-NEXT: 2 3 1.00 mulw %si # CHECK-NEXT: 3 3 3.00 mulw %si
# CHECK-NEXT: 2 6 1.00 * mulw (%rax) # CHECK-NEXT: 3 6 3.00 * mulw (%rax)
# CHECK-NEXT: 2 3 1.00 mull %edx # CHECK-NEXT: 2 3 2.00 mull %edx
# CHECK-NEXT: 2 6 1.00 * mull (%rax) # CHECK-NEXT: 2 6 2.00 * mull (%rax)
# CHECK-NEXT: 2 6 4.00 mulq %rcx # CHECK-NEXT: 2 6 4.00 mulq %rcx
# CHECK-NEXT: 2 9 4.00 * mulq (%rax) # CHECK-NEXT: 2 9 4.00 * mulq (%rax)
# CHECK-NEXT: 1 1 0.50 negb %dil # CHECK-NEXT: 1 1 0.50 negb %dil
# CHECK-NEXT: 1 5 1.00 * * negb (%r8) # CHECK-NEXT: 1 5 1.00 * * negb (%r8)
# CHECK-NEXT: 1 19 19.00 * * lock negb (%r8) # CHECK-NEXT: 1 19 19.00 * * lock negb (%r8)
# CHECK-NEXT: 1 1 0.50 negw %si # CHECK-NEXT: 1 1 0.50 negw %si
# CHECK-NEXT: 1 5 1.00 * * negw (%r9) # CHECK-NEXT: 1 5 1.00 * * negw (%r9)
# CHECK-NEXT: 1 19 19.00 * * lock negw (%r9) # CHECK-NEXT: 1 19 19.00 * * lock negw (%r9)
▲ Show 20 Lines • Show All 521 Lines • ▼ Show 20 Lines
# CHECK-NEXT: [9] - JSAGU # CHECK-NEXT: [9] - JSAGU
# CHECK-NEXT: [10] - JSTC # CHECK-NEXT: [10] - JSTC
# CHECK-NEXT: [11] - JVALU0 # CHECK-NEXT: [11] - JVALU0
# CHECK-NEXT: [12] - JVALU1 # CHECK-NEXT: [12] - JVALU1
# CHECK-NEXT: [13] - JVIMUL # CHECK-NEXT: [13] - JVIMUL
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
# CHECK-NEXT: 702.50 752.50 380.00 - - - - 812.00 64.00 713.00 - - - - # CHECK-NEXT: 702.50 752.50 380.00 - - - - 812.00 80.00 713.00 - - - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - - adcb $0, %al # CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - - adcb $0, %al
# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - - adcb $0, %dil # CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - - adcb $0, %dil
# CHECK-NEXT: 1.00 1.00 - - - - - 1.00 - 1.00 - - - - adcb $0, (%rax) # CHECK-NEXT: 1.00 1.00 - - - - - 1.00 - 1.00 - - - - adcb $0, (%rax)
# CHECK-NEXT: 1.00 1.00 - - - - - 1.00 - 1.00 - - - - lock adcb $0, (%rax) # CHECK-NEXT: 1.00 1.00 - - - - - 1.00 - 1.00 - - - - lock adcb $0, (%rax)
# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - - adcb $7, %al # CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - - adcb $7, %al
▲ Show 20 Lines • Show All 293 Lines • ▼ Show 20 Lines
# CHECK-NEXT: - 1.00 17.00 - - - - - - - - - - - idivw %si # CHECK-NEXT: - 1.00 17.00 - - - - - - - - - - - idivw %si
# CHECK-NEXT: - 1.00 17.00 - - - - 1.00 - - - - - - idivw (%rax) # CHECK-NEXT: - 1.00 17.00 - - - - 1.00 - - - - - - idivw (%rax)
# CHECK-NEXT: - 1.00 25.00 - - - - - - - - - - - idivl %edx # CHECK-NEXT: - 1.00 25.00 - - - - - - - - - - - idivl %edx
# CHECK-NEXT: - 1.00 25.00 - - - - 1.00 - - - - - - idivl (%rax) # CHECK-NEXT: - 1.00 25.00 - - - - 1.00 - - - - - - idivl (%rax)
# CHECK-NEXT: - 1.00 41.00 - - - - - - - - - - - idivq %rcx # CHECK-NEXT: - 1.00 41.00 - - - - - - - - - - - idivq %rcx
# CHECK-NEXT: - 1.00 41.00 - - - - 1.00 - - - - - - idivq (%rax) # CHECK-NEXT: - 1.00 41.00 - - - - 1.00 - - - - - - idivq (%rax)
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imulb %dil # CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imulb %dil
# CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - imulb (%rax) # CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - imulb (%rax)
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imulw %di # CHECK-NEXT: - 1.00 - - - - - - 3.00 - - - - - imulw %di
# CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - imulw (%rax) # CHECK-NEXT: - 1.00 - - - - - 1.00 3.00 - - - - - imulw (%rax)
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imulw %si, %di # CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imulw %si, %di
# CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - imulw (%rax), %di # CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - imulw (%rax), %di
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imulw $511, %si, %di # CHECK-NEXT: - 1.00 - - - - - - 2.00 - - - - - imulw $511, %si, %di
# CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - imulw $511, (%rax), %di # CHECK-NEXT: - 1.00 - - - - - 1.00 2.00 - - - - - imulw $511, (%rax), %di
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imulw $7, %si, %di # CHECK-NEXT: - 1.00 - - - - - - 2.00 - - - - - imulw $7, %si, %di
# CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - imulw $7, (%rax), %di # CHECK-NEXT: - 1.00 - - - - - 1.00 2.00 - - - - - imulw $7, (%rax), %di
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imull %edi # CHECK-NEXT: - 1.00 - - - - - - 2.00 - - - - - imull %edi
# CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - imull (%rax) # CHECK-NEXT: - 1.00 - - - - - 1.00 2.00 - - - - - imull (%rax)
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imull %esi, %edi # CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imull %esi, %edi
# CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - imull (%rax), %edi # CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - imull (%rax), %edi
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imull $665536, %esi, %edi # CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imull $665536, %esi, %edi
# CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - imull $665536, (%rax), %edi # CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - imull $665536, (%rax), %edi
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imull $7, %esi, %edi # CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imull $7, %esi, %edi
# CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - imull $7, (%rax), %edi # CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - imull $7, (%rax), %edi
# CHECK-NEXT: - 1.00 - - - - - - 4.00 - - - - - imulq %rdi # CHECK-NEXT: - 1.00 - - - - - - 4.00 - - - - - imulq %rdi
# CHECK-NEXT: - 1.00 - - - - - 1.00 4.00 - - - - - imulq (%rax) # CHECK-NEXT: - 1.00 - - - - - 1.00 4.00 - - - - - imulq (%rax)
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movswq %ax, %rdi # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movswq %ax, %rdi
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movzwq %ax, %rdi # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movzwq %ax, %rdi
# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - movswq (%rax), %rdi # CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - movswq (%rax), %rdi
# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - movzwq (%rax), %rdi # CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - movzwq (%rax), %rdi
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movslq %eax, %rdi # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movslq %eax, %rdi
# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - movslq (%rax), %rdi # CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - movslq (%rax), %rdi
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - mulb %dil # CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - mulb %dil
# CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - mulb (%rax) # CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - mulb (%rax)
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - mulw %si # CHECK-NEXT: - 1.00 - - - - - - 3.00 - - - - - mulw %si
# CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - mulw (%rax) # CHECK-NEXT: - 1.00 - - - - - 1.00 3.00 - - - - - mulw (%rax)
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - mull %edx # CHECK-NEXT: - 1.00 - - - - - - 2.00 - - - - - mull %edx
# CHECK-NEXT: - 1.00 - - - - - 1.00 1.00 - - - - - mull (%rax) # CHECK-NEXT: - 1.00 - - - - - 1.00 2.00 - - - - - mull (%rax)
# CHECK-NEXT: - 1.00 - - - - - - 4.00 - - - - - mulq %rcx # CHECK-NEXT: - 1.00 - - - - - - 4.00 - - - - - mulq %rcx
# CHECK-NEXT: - 1.00 - - - - - 1.00 4.00 - - - - - mulq (%rax) # CHECK-NEXT: - 1.00 - - - - - 1.00 4.00 - - - - - mulq (%rax)
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - negb %dil # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - negb %dil
# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - 1.00 - - - - negb (%r8) # CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - 1.00 - - - - negb (%r8)
# CHECK-NEXT: 0.50 0.50 - - - - - 19.00 - 19.00 - - - - lock negb (%r8) # CHECK-NEXT: 0.50 0.50 - - - - - 19.00 - 19.00 - - - - lock negb (%r8)
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - negw %si # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - negw %si
# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - 1.00 - - - - negw (%r9) # CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - 1.00 - - - - negw (%r9)
# CHECK-NEXT: 0.50 0.50 - - - - - 19.00 - 19.00 - - - - lock negw (%r9) # CHECK-NEXT: 0.50 0.50 - - - - - 19.00 - 19.00 - - - - lock negw (%r9)
▲ Show 20 Lines • Show All 510 Lines • Show Last 20 Lines

test/tools/llvm-mca/X86/intel-syntax.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,INTEL # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,INTEL
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -output-asm-variant=0 < %s | FileCheck %s -check-prefixes=ALL,ATT # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -output-asm-variant=0 < %s | FileCheck %s -check-prefixes=ALL,ATT
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -output-asm-variant=1 < %s | FileCheck %s -check-prefixes=ALL,INTEL # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -output-asm-variant=1 < %s | FileCheck %s -check-prefixes=ALL,INTEL
.intel_syntax noprefix .intel_syntax noprefix
mov eax, 1 mov eax, 1
mov ebx, 0xff mov ebx, 0xff
imul esi, edi imul esi, edi
lea eax, [rsi + rdi] lea eax, [rsi + rdi]
# ALL: Iterations: 100 # ALL: Iterations: 100
# ALL-NEXT: Instructions: 400 # ALL-NEXT: Instructions: 400
# ALL-NEXT: Total Cycles: 305 # ALL-NEXT: Total Cycles: 306
# ALL-NEXT: Total uOps: 500 # ALL-NEXT: Total uOps: 400
# ALL: Dispatch Width: 2 # ALL: Dispatch Width: 2
# ALL-NEXT: uOps Per Cycle: 1.64 # ALL-NEXT: uOps Per Cycle: 1.31
# ALL-NEXT: IPC: 1.31 # ALL-NEXT: IPC: 1.31
# ALL-NEXT: Block RThroughput: 2.5 # ALL-NEXT: Block RThroughput: 2.0
# ALL: Instruction Info: # ALL: Instruction Info:
# ALL-NEXT: [1]: #uOps # ALL-NEXT: [1]: #uOps
# ALL-NEXT: [2]: Latency # ALL-NEXT: [2]: Latency
# ALL-NEXT: [3]: RThroughput # ALL-NEXT: [3]: RThroughput
# ALL-NEXT: [4]: MayLoad # ALL-NEXT: [4]: MayLoad
# ALL-NEXT: [5]: MayStore # ALL-NEXT: [5]: MayStore
# ALL-NEXT: [6]: HasSideEffects (U) # ALL-NEXT: [6]: HasSideEffects (U)
# ALL: [1] [2] [3] [4] [5] [6] Instructions: # ALL: [1] [2] [3] [4] [5] [6] Instructions:
# ATT-NEXT: 1 1 0.50 movl $1, %eax # ATT-NEXT: 1 1 0.50 movl $1, %eax
# ATT-NEXT: 1 1 0.50 movl $255, %ebx # ATT-NEXT: 1 1 0.50 movl $255, %ebx
# ATT-NEXT: 2 3 1.00 imull %edi, %esi # ATT-NEXT: 1 3 1.00 imull %edi, %esi
# ATT-NEXT: 1 1 0.50 leal (%rsi,%rdi), %eax # ATT-NEXT: 1 1 0.50 leal (%rsi,%rdi), %eax
# INTEL-NEXT: 1 1 0.50 mov eax, 1 # INTEL-NEXT: 1 1 0.50 mov eax, 1
# INTEL-NEXT: 1 1 0.50 mov ebx, 255 # INTEL-NEXT: 1 1 0.50 mov ebx, 255
# INTEL-NEXT: 2 3 1.00 imul esi, edi # INTEL-NEXT: 1 3 1.00 imul esi, edi
# INTEL-NEXT: 1 1 0.50 lea eax, [rsi + rdi] # INTEL-NEXT: 1 1 0.50 lea eax, [rsi + rdi]

test/tools/llvm-mca/X86/llvm-mca-markers-10.s

Show All 9 Lines# LLVM-MCA-END upper
leal 42(%rdi), %eax leal 42(%rdi), %eax
# LLVM-MCA-END lower # LLVM-MCA-END lower
imull %esi, %eax imull %esi, %eax
# CHECK: [0] Code Region - upper # CHECK: [0] Code Region - upper
# CHECK: Iterations: 100 # CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200 # CHECK-NEXT: Instructions: 200
# CHECK-NEXT: Total Cycles: 205 # CHECK-NEXT: Total Cycles: 106
# CHECK-NEXT: Total uOps: 300 # CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 1.46 # CHECK-NEXT: uOps Per Cycle: 1.89
# CHECK-NEXT: IPC: 0.98 # CHECK-NEXT: IPC: 1.89
# CHECK-NEXT: Block RThroughput: 1.5 # CHECK-NEXT: Block RThroughput: 1.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1 0.50 leal 42(%rdi), %eax # CHECK-NEXT: 1 1 0.50 leal 42(%rdi), %eax
# CHECK-NEXT: 2 3 1.00 imull %esi, %eax # CHECK-NEXT: 1 3 1.00 imull %esi, %eax
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - JALU0 # CHECK-NEXT: [0] - JALU0
# CHECK-NEXT: [1] - JALU1 # CHECK-NEXT: [1] - JALU1
# CHECK-NEXT: [2] - JDiv # CHECK-NEXT: [2] - JDiv
# CHECK-NEXT: [3] - JFPA # CHECK-NEXT: [3] - JFPA
# CHECK-NEXT: [4] - JFPM # CHECK-NEXT: [4] - JFPM
# CHECK-NEXT: [5] - JFPU0 # CHECK-NEXT: [5] - JFPU0
Show All 14 Lines
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
# CHECK-NEXT: 0.99 0.01 - - - - - - - - - - - - leal 42(%rdi), %eax # CHECK-NEXT: 0.99 0.01 - - - - - - - - - - - - leal 42(%rdi), %eax
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imull %esi, %eax # CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imull %esi, %eax
# CHECK: [1] Code Region - lower # CHECK: [1] Code Region - lower
# CHECK: Iterations: 100 # CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200 # CHECK-NEXT: Instructions: 200
# CHECK-NEXT: Total Cycles: 204 # CHECK-NEXT: Total Cycles: 105
# CHECK-NEXT: Total uOps: 300 # CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 1.47 # CHECK-NEXT: uOps Per Cycle: 1.90
# CHECK-NEXT: IPC: 0.98 # CHECK-NEXT: IPC: 1.90
# CHECK-NEXT: Block RThroughput: 1.5 # CHECK-NEXT: Block RThroughput: 1.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 3 1.00 imull %esi, %eax # CHECK-NEXT: 1 3 1.00 imull %esi, %eax
# CHECK-NEXT: 1 1 0.50 leal 42(%rdi), %eax # CHECK-NEXT: 1 1 0.50 leal 42(%rdi), %eax
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - JALU0 # CHECK-NEXT: [0] - JALU0
# CHECK-NEXT: [1] - JALU1 # CHECK-NEXT: [1] - JALU1
# CHECK-NEXT: [2] - JDiv # CHECK-NEXT: [2] - JDiv
# CHECK-NEXT: [3] - JFPA # CHECK-NEXT: [3] - JFPA
# CHECK-NEXT: [4] - JFPM # CHECK-NEXT: [4] - JFPM
Show All 18 Lines

test/tools/llvm-mca/X86/llvm-mca-markers-9.s

Show All 9 Lines# LLVM-MCA-END inner
leal 42(%rdi), %eax leal 42(%rdi), %eax
# LLVM-MCA-END outer # LLVM-MCA-END outer
imull %esi, %eax imull %esi, %eax
# CHECK: [0] Code Region - outer # CHECK: [0] Code Region - outer
# CHECK: Iterations: 100 # CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 300 # CHECK-NEXT: Instructions: 300
# CHECK-NEXT: Total Cycles: 205 # CHECK-NEXT: Total Cycles: 156
# CHECK-NEXT: Total uOps: 400 # CHECK-NEXT: Total uOps: 300
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 1.95 # CHECK-NEXT: uOps Per Cycle: 1.92
# CHECK-NEXT: IPC: 1.46 # CHECK-NEXT: IPC: 1.92
# CHECK-NEXT: Block RThroughput: 2.0 # CHECK-NEXT: Block RThroughput: 1.5
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1 0.50 leal 42(%rdi), %eax # CHECK-NEXT: 1 1 0.50 leal 42(%rdi), %eax
# CHECK-NEXT: 2 3 1.00 imull %esi, %eax # CHECK-NEXT: 1 3 1.00 imull %esi, %eax
# CHECK-NEXT: 1 1 0.50 leal 42(%rdi), %eax # CHECK-NEXT: 1 1 0.50 leal 42(%rdi), %eax
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - JALU0 # CHECK-NEXT: [0] - JALU0
# CHECK-NEXT: [1] - JALU1 # CHECK-NEXT: [1] - JALU1
# CHECK-NEXT: [2] - JDiv # CHECK-NEXT: [2] - JDiv
# CHECK-NEXT: [3] - JFPA # CHECK-NEXT: [3] - JFPA
# CHECK-NEXT: [4] - JFPM # CHECK-NEXT: [4] - JFPM
# CHECK-NEXT: [5] - JFPU0 # CHECK-NEXT: [5] - JFPU0
# CHECK-NEXT: [6] - JFPU1 # CHECK-NEXT: [6] - JFPU1
# CHECK-NEXT: [7] - JLAGU # CHECK-NEXT: [7] - JLAGU
# CHECK-NEXT: [8] - JMul # CHECK-NEXT: [8] - JMul
# CHECK-NEXT: [9] - JSAGU # CHECK-NEXT: [9] - JSAGU
# CHECK-NEXT: [10] - JSTC # CHECK-NEXT: [10] - JSTC
# CHECK-NEXT: [11] - JVALU0 # CHECK-NEXT: [11] - JVALU0
# CHECK-NEXT: [12] - JVALU1 # CHECK-NEXT: [12] - JVALU1
# CHECK-NEXT: [13] - JVIMUL # CHECK-NEXT: [13] - JVIMUL
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
# CHECK-NEXT: 1.00 2.00 - - - - - - 1.00 - - - - - # CHECK-NEXT: 1.49 1.51 - - - - - - 1.00 - - - - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
# CHECK-NEXT: - 1.00 - - - - - - - - - - - - leal 42(%rdi), %eax # CHECK-NEXT: 0.99 0.01 - - - - - - - - - - - - leal 42(%rdi), %eax
# CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imull %esi, %eax # CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imull %esi, %eax
# CHECK-NEXT: 1.00 - - - - - - - - - - - - - leal 42(%rdi), %eax # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - leal 42(%rdi), %eax
# CHECK: [1] Code Region - inner # CHECK: [1] Code Region - inner
# CHECK: Iterations: 100 # CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 100 # CHECK-NEXT: Instructions: 100
# CHECK-NEXT: Total Cycles: 303 # CHECK-NEXT: Total Cycles: 303
# CHECK-NEXT: Total uOps: 200 # CHECK-NEXT: Total uOps: 100
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.66 # CHECK-NEXT: uOps Per Cycle: 0.33
# CHECK-NEXT: IPC: 0.33 # CHECK-NEXT: IPC: 0.33
# CHECK-NEXT: Block RThroughput: 1.0 # CHECK-NEXT: Block RThroughput: 1.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 3 1.00 imull %esi, %eax # CHECK-NEXT: 1 3 1.00 imull %esi, %eax
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - JALU0 # CHECK-NEXT: [0] - JALU0
# CHECK-NEXT: [1] - JALU1 # CHECK-NEXT: [1] - JALU1
# CHECK-NEXT: [2] - JDiv # CHECK-NEXT: [2] - JDiv
# CHECK-NEXT: [3] - JFPA # CHECK-NEXT: [3] - JFPA
# CHECK-NEXT: [4] - JFPM # CHECK-NEXT: [4] - JFPM
# CHECK-NEXT: [5] - JFPU0 # CHECK-NEXT: [5] - JFPU0
Show All 16 Lines