[X86][SSE] Improve matching of SSE blend instructions with splatted vector inputs

[RKSimon]

Summary

If the input to a shuffle is safely splatted (i.e. no undef) then the SSE blend instructions can use any lane from that input to match against.

[chandlerc]

I generally think this entire thing should be handled in the target-independent dag combiner. We should always canonicalize a splat-like shuffle into a buildvector that is obviously a splat. And we should always canonicalize a shuffle of such a buildvector into a blend IMO.

At the very least, I'd prefer to see these at x86 DAG combines rather than doing it in the lowering unless (as mentioned below) you have test cases where the pattern only emerges while lowering.

lib/Target/X86/X86ISelLowering.cpp

7366–7369

Why are only constants safe here? Shouldn't it be any buildvector of a single scalar SDValue without undefs?

I also could have sworn there was already a predicate for this...

7372–7376

If we fail to turn this kind of shuffle vector into a buildvector splat, we should fix that in the target independent dag combining, no?

The only time I've been unable to do this is when the pattern didn't emerge until *during* lowering. Do you have test cases showing that?

[RKSimon]

No problem - I'll look into moving this into the target-independent dag combiner.

lib/Target/X86/X86ISelLowering.cpp

7366–7369

I just added the most likely contenders to the safesplat detector. I can find several existing predicates that do some splat testing, mainly within various different targets' specific code, and none that appear to do all the obvious tests. I'll look into putting a more general predicate in the ISD namespace and convert some existing use cases (I've been meaning to do something similar for the zeroable shuffle tests as well).

7372–7376

I'll look at adding a dag combiner test to improve partial splats with undefs to a full splat.

No real world test cases that I can recall. The only cases I can think of are ones where we are blending with zero, lowering often raises 'zeroable' lanes to definite zeros, but AFAIK we don't track that in x86 shuffle lowering. But even this could technicaly be raised to the target independent dag combiner.

[RKSimon]

Abandoning patch - I will attempt to do this in DAG combine instead.

lib/Target/X86/X86ISelLowering.cpp

 /// This doesn't do any checks for the availability of instructions for blending
 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
 /// be matched in the backend with the type given. What it does check for is
 /// that the shuffle mask is in fact a blend.
 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
                                          SDValue V2, ArrayRef<int> Mask,
                                          const X86Subtarget *Subtarget,
                                          SelectionDAG &DAG) {
+  // Determine if inputs are safe splats (no undefs).
+  auto isSafeSplat = [](SDValue V) {
+    BitVector UndefElements;
+    if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V.getNode())) {
+      if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
+        return true;
+      if (BVOp->getConstantFPSplatNode(&UndefElements) && UndefElements.none())
+        return true;
+    }
+    if (auto *SVNOp = dyn_cast<ShuffleVectorSDNode>(V.getNode())) {
+      ArrayRef<int> SVNMask = SVNOp->getMask();
+      for (int i = 0, Size = SVNMask.size(); i < Size; ++i)
+        if (SVNMask[i] < 0 || SVNMask[i] != SVNMask[0])
+          return false;
+      return true;
+    }
+    return false;
+  };
+  bool IsV1Splat = isSafeSplat(V1);
+  bool IsV2Splat = isSafeSplat(V2);
 
   unsigned BlendMask = 0;
   for (int i = 0, Size = Mask.size(); i < Size; ++i) {
     if (Mask[i] >= Size) {
-      if (Mask[i] != i + Size)
+      if (Mask[i] != i + Size && !IsV2Splat)
         return SDValue(); // Shuffled V2 input!
       BlendMask |= 1u << i;
       continue;
     }
-    if (Mask[i] >= 0 && Mask[i] != i)
+    if (Mask[i] >= 0 && Mask[i] != i && !IsV1Splat)
       return SDValue(); // Shuffled V1 input!
   }
   switch (VT.SimpleTy) {
   case MVT::v2f64:
   case MVT::v4f32:
   case MVT::v4f64:
   case MVT::v8f32:
     return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,

test/CodeGen/X86/combine-or.ll

 
 
 ; Verify that the dag-combiner does not fold a OR of two shuffles into a single
 ; shuffle instruction when the shuffle indexes are not compatible.
 
 define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test17:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    xorps %xmm2, %xmm2
-; CHECK-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,0]
-; CHECK-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[0,2]
-; CHECK-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
+; CHECK-NEXT:    pxor %xmm2, %xmm2
+; CHECK-NEXT:    pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
+; CHECK-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[0,2]
+; CHECK-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
 ; CHECK-NEXT:    orps %xmm1, %xmm2
 ; CHECK-NEXT:    movaps %xmm2, %xmm0
 ; CHECK-NEXT:    retq
   %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 2>
   %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
   %or = or <4 x i32> %shuf1, %shuf2
   ret <4 x i32> %or
 }

test/CodeGen/X86/vector-blend.ll

 ; AVX2-LABEL: blend_shufflevector_4xi64:
 ; AVX2:       # BB#0: # %entry
 ; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5,6,7]
 ; AVX2-NEXT:    retq
 entry:
   %select = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
   ret <4 x i64> %select
 }
+
+; Blend with Splat
+
+define <4 x float> @blend_splat_float(<4 x float> %v1, <4 x float> %v2) {
+; SSE2-LABEL: blend_splat_float:
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,3],xmm0[1,3]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
+; SSE2-NEXT:    movaps  %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: blend_splat_float:
+; SSSE3:       # BB#0: # %entry
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,3],xmm0[1,3]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
+; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: blend_splat_float:
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
+; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: blend_splat_float:
+; AVX1:       # BB#0: # %entry
+; AVX1-NEXT:    vpermilps {{.*#+}} xmm1 = xmm1[3,3,3,3]
+; AVX1-NEXT:    vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: blend_splat_float:
+; AVX2:       # BB#0: # %entry
+; AVX2-NEXT:    vpermilps {{.*#+}} xmm1 = xmm1[3,3,3,3]
+; AVX2-NEXT:    vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
+; AVX2-NEXT:    retq
+entry:
+  %splat = shufflevector <4 x float> %v2, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  %select = shufflevector <4 x float> %v1, <4 x float> %splat, <4 x i32> <i32 4, i32 1, i32 7, i32 3>
+  ret <4 x float> %select
+}
+