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Differential D65069

[ARM][ParallelDSP] Improve smlad search
AbandonedPublic

Authored by samparker on Jul 22 2019, 2:48 AM.

Details

Reviewers
SjoerdMeijer
Summary

There was a bug with the smlad search where we'd only look at the LHS of an Add to see whether it was a valid operation. We don't really need to perform this check and can just try to use the add as an accumulator value if either LHS and RHS are invalid. This change allows more smlads to be generated.

Diff Detail

Event Timeline

samparker created this revision.Jul 22 2019, 2:48 AM
Herald added subscribers: kristof.beyls, javed.absar. · View Herald TranscriptJul 22 2019, 2:48 AM
samparker abandoned this revision.Jul 25 2019, 5:57 AM

Not sure why this is still lingering in my phab, this has been closed already.

Revision Contents

PathSize
lib/
Target/
ARM/
6 lines
test/
CodeGen/
ARM/
ParallelDSP/
18 lines
142 lines
150 lines

Diff 211036

lib/Target/ARM/ARMParallelDSP.cpp

Show First 20 Lines • Show All 492 Lines • ▼ Show 20 Lines
break; break;
case Instruction::PHI: case Instruction::PHI:
// Could be the accumulator value. // Could be the accumulator value.
return R.InsertAcc(V); return R.InsertAcc(V);
case Instruction::Add: { case Instruction::Add: {
// Adds should be adding together two muls, or another add and a mul to // Adds should be adding together two muls, or another add and a mul to
// be within the mac chain. One of the operands may also be the // be within the mac chain. One of the operands may also be the
// accumulator value at which point we should stop searching. // accumulator value at which point we should stop searching.
bool ValidLHS = Search(I->getOperand(0), R); if (Search(I->getOperand(0), R) && Search(I->getOperand(1), R)) {
bool ValidRHS = Search(I->getOperand(1), R);
if (!ValidLHS && !ValidLHS)
return false;
else if (ValidLHS && ValidRHS) {
R.InsertAdd(I); R.InsertAdd(I);
return true; return true;
} else { } else {
R.InsertAdd(I); R.InsertAdd(I);
return R.InsertAcc(I); return R.InsertAcc(I);
} }
} }
case Instruction::Mul: { case Instruction::Mul: {
▲ Show 20 Lines • Show All 323 Lines • Show Last 20 Lines

test/CodeGen/ARM/ParallelDSP/aliasing.ll

Show First 20 Lines • Show All 445 Lines • ▼ Show 20 Linesfor.body:
%conv8 = sext i16 %1 to i32 %conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8 %mul9 = mul nsw i32 %conv7, %conv8
%add10 = add i32 %mul, %mac1.026 %add10 = add i32 %mul, %mac1.026
%add11 = add i32 %mul9, %add10 %add11 = add i32 %mul9, %add10
%exitcond = icmp ne i32 %add, %arg %exitcond = icmp ne i32 %add, %arg
br i1 %exitcond, label %for.body, label %for.cond.cleanup br i1 %exitcond, label %for.body, label %for.cond.cleanup
} }
; TODO: I think we should be able to generate one smlad here. The search fails
; when it finds the alias.
; CHECK-LABEL: one_pair_alias ; CHECK-LABEL: one_pair_alias
; CHECK-NOT: call i32 @llvm.arm.smlad ; CHECK: phi i32
; CHECK: [[ACC:%[^ ]+]] = phi i32 [ 0, %entry ], [ [[SMLAD:%[^ ]+]], %for.body ]
; CHECK: [[LD0:%[^ ]+]] = load i16, i16* %arrayidx, align 2
; CHECK: [[ADDR_B:%[^ ]+]] = bitcast i16* %arrayidx4 to i32*
; CHECK: [[B:%[^ ]+]] = load i32, i32* [[ADDR_B]], align 2
; CHECK: [[ALIAS:%[^ ]+]] = load i16, i16* %arrayidx1, align 2
; CHECK: store i16 43, i16* %arrayidx7
; CHECK: [[ADDR_C:%[^ ]+]] = bitcast i16* %arrayidx7 to i32*
; CHECK: [[C:%[^ ]+]] = load i32, i32* [[ADDR_C]], align 2
; CHECK: [[SEXT0:%[^ ]+]] = sext i16 [[LD0]] to i32
; CHECK: [[SEXT1:%[^ ]+]] = sext i16 [[ALIAS]] to i32
; CHECK: [[MUL:%[^ ]+]] = mul nsw i32 [[SEXT1]], [[SEXT0]]
; CHECK: [[ADD:%[^ ]+]] = add nsw i32 [[MUL]], [[ACC]]
; CHECK: [[SMLAD]] = call i32 @llvm.arm.smlad(i32 [[C]], i32 [[B]], i32 [[ADD]])
define i32 @one_pair_alias(i16* noalias nocapture readonly %b, i16* noalias nocapture readonly %c) { define i32 @one_pair_alias(i16* noalias nocapture readonly %b, i16* noalias nocapture readonly %c) {
entry: entry:
br label %for.body br label %for.body
for.cond.cleanup: ; preds = %for.body for.cond.cleanup: ; preds = %for.body
ret i32 %add26 ret i32 %add26
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

test/CodeGen/ARM/ParallelDSP/search.ll

  • This file was added.
; RUN: opt -mtriple=arm -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
; CHECK-LABEL: invalid_second_add
; CHECK: phi i32
; CHECK: [[ACC:%[^ ]+]] = phi i32 [ 0, %entry ], [ [[SMLAD:%[^ ]+]], %for.body ]
; CHECK: [[ADDR_B:%[^ ]+]] = bitcast i16* %arrayidx4 to i32*
; CHECK: [[B:%[^ ]+]] = load i32, i32* [[ADDR_B]], align 2
; CHECK: [[ADDR_C:%[^ ]+]] = bitcast i16* %arrayidx7 to i32*
; CHECK: [[C:%[^ ]+]] = load i32, i32* [[ADDR_C]], align 2
; CHECK: [[SDIV:%[^ ]+]] = sdiv i32
; CHECK: [[ADD:%[^ ]+]] = add nsw i32 [[SDIV]], [[ACC]]
; CHECK: [[SMLAD]] = call i32 @llvm.arm.smlad(i32 [[C]], i32 [[B]], i32 [[ADD]])
define i32 @invalid_second_add(i16* noalias nocapture readonly %b, i16* noalias nocapture readonly %c) {
entry:
br label %for.body
for.cond.cleanup:
ret i32 %add26
for.body:
%i.050 = phi i32 [ 0, %entry ], [ %add27, %for.body ]
%a.049 = phi i32 [ 0, %entry ], [ %add26, %for.body ]
%add3 = or i32 %i.050, 1
%add11 = or i32 %i.050, 2
%add19 = or i32 %i.050, 3
%arrayidx = getelementptr inbounds i16, i16* %b, i32 %i.050
%arrayidx4 = getelementptr inbounds i16, i16* %b, i32 %add3
%arrayidx12 = getelementptr inbounds i16, i16* %b, i32 %add11
%arrayidx20 = getelementptr inbounds i16, i16* %b, i32 %add19
%arrayidx1 = getelementptr inbounds i16, i16* %c, i32 %i.050
%arrayidx7 = getelementptr inbounds i16, i16* %c, i32 %add3
%arrayidx15 = getelementptr inbounds i16, i16* %c, i32 %add11
%arrayidx23 = getelementptr inbounds i16, i16* %c, i32 %add19
%tmp = load i16, i16* %arrayidx, align 2
%tmp2 = load i16, i16* %arrayidx4, align 2
%tmp4 = load i16, i16* %arrayidx12, align 2
%tmp6 = load i16, i16* %arrayidx20, align 2
%tmp1 = load i16, i16* %arrayidx1, align 2
%tmp3 = load i16, i16* %arrayidx7, align 2
%tmp5 = load i16, i16* %arrayidx15, align 2
%tmp7 = load i16, i16* %arrayidx23, align 2
%conv = sext i16 %tmp to i32
%conv2 = sext i16 %tmp1 to i32
%sdiv = sdiv i32 %conv2, %conv
%add = add nsw i32 %sdiv, %a.049
%conv5 = sext i16 %tmp2 to i32
%conv8 = sext i16 %tmp3 to i32
%mul9 = mul nsw i32 %conv8, %conv5
%add10 = add nsw i32 %add, %mul9
%conv13 = sext i16 %tmp4 to i32
%conv16 = sext i16 %tmp5 to i32
%mul17 = mul nsw i32 %conv16, %conv13
%add18 = add nsw i32 %add10, %mul17
%conv21 = sext i16 %tmp6 to i32
%conv24 = sext i16 %tmp7 to i32
%mul25 = mul nsw i32 %conv24, %conv21
%add26 = add nsw i32 %add18, %mul25
%add27 = add nuw nsw i32 %i.050, 4
%cmp = icmp ult i32 %add27, 100
br i1 %cmp, label %for.body, label %for.cond.cleanup
}
define i32 @one_zext(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
; CHECK-LABEL: @one_zext
; CHECK-NOT: call i32 @llvm.arm.smlad
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
%.pre = load i16, i16* %arg3, align 2
%.pre27 = load i16, i16* %arg2, align 2
br label %for.body
for.cond.cleanup:
%mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
ret i32 %mac1.0.lcssa
for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
%0 = load i16, i16* %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
%arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
%1 = load i16, i16* %arrayidx1, align 2
%arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
%2 = load i16, i16* %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = zext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
%arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
%3 = load i16, i16* %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = zext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
%add10 = add i32 %mul, %mac1.026
%add11 = add i32 %mul9, %add10
%exitcond = icmp ne i32 %add, %arg
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}
define i32 @two_zext(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
; CHECK-LABEL: @two_zext
; CHECK-NOT: call i32 @llvm.arm.smlad
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
%.pre = load i16, i16* %arg3, align 2
%.pre27 = load i16, i16* %arg2, align 2
br label %for.body
for.cond.cleanup:
%mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
ret i32 %mac1.0.lcssa
for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
%0 = load i16, i16* %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
%arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
%1 = load i16, i16* %arrayidx1, align 2
%arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
%2 = load i16, i16* %arrayidx3, align 2
%conv = zext i16 %2 to i32
%conv4 = zext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
%arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
%3 = load i16, i16* %arrayidx6, align 2
%conv7 = zext i16 %3 to i32
%conv8 = zext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
%add10 = add i32 %mul, %mac1.026
%add11 = add i32 %mul9, %add10
%exitcond = icmp ne i32 %add, %arg
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}

test/CodeGen/ARM/ParallelDSP/smlad0.ll

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; Here the Mul is the LHS, and the Add the RHS. ; Here the Mul is the LHS, and the Add the RHS.
%add11 = add i32 %mul9, %add10 %add11 = add i32 %mul9, %add10
%exitcond = icmp ne i32 %add, %arg %exitcond = icmp ne i32 %add, %arg
br i1 %exitcond, label %for.body, label %for.cond.cleanup br i1 %exitcond, label %for.body, label %for.cond.cleanup
} }
define dso_local arm_aapcs_vfpcc i32 @TwoReductions(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
;
; CHECK-LABEL: @TwoReductions
;
; CHECK: %mac1{{\.}}058 = phi i32 [ [[V10:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ]
; CHECK: %mac2{{\.}}057 = phi i32 [ [[V17:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ]
; CHECK: [[V10]] = call i32 @llvm.arm.smlad(i32 %{{.*}}, i32 %{{.*}}, i32 %mac1{{\.}}058)
; CHECK: [[V17]] = call i32 @llvm.arm.smlad(i32 %{{.*}}, i32 %{{.*}}, i32 %mac2{{\.}}057)
; CHECK-NOT: call i32 @llvm.arm.smlad
;
entry:
%cmp55 = icmp sgt i32 %arg, 0
br i1 %cmp55, label %for.body.preheader, label %for.cond.cleanup
for.cond.cleanup:
%mac2.0.lcssa = phi i32 [ 0, %entry ], [ %add28, %for.body ]
%mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add16, %for.body ]
%add30 = add nsw i32 %mac1.0.lcssa, %mac2.0.lcssa
ret i32 %add30
for.body.preheader:
br label %for.body
for.body:
; And two reduction statements here:
%mac1.058 = phi i32 [ %add16, %for.body ], [ 0, %for.body.preheader ]
%mac2.057 = phi i32 [ %add28, %for.body ], [ 0, %for.body.preheader ]
%i.056 = phi i32 [ %add29, %for.body ], [ 0, %for.body.preheader ]
%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.056
%0 = load i16, i16* %arrayidx, align 2
%add1 = or i32 %i.056, 1
%arrayidx2 = getelementptr inbounds i16, i16* %arg3, i32 %add1
%1 = load i16, i16* %arrayidx2, align 2
%add3 = or i32 %i.056, 2
%arrayidx4 = getelementptr inbounds i16, i16* %arg3, i32 %add3
%2 = load i16, i16* %arrayidx4, align 2
%add5 = or i32 %i.056, 3
%arrayidx6 = getelementptr inbounds i16, i16* %arg3, i32 %add5
%3 = load i16, i16* %arrayidx6, align 2
%arrayidx8 = getelementptr inbounds i16, i16* %arg2, i32 %i.056
%4 = load i16, i16* %arrayidx8, align 2
%conv = sext i16 %4 to i32
%conv9 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv9
%arrayidx11 = getelementptr inbounds i16, i16* %arg2, i32 %add1
%5 = load i16, i16* %arrayidx11, align 2
%conv12 = sext i16 %5 to i32
%conv13 = sext i16 %1 to i32
%mul14 = mul nsw i32 %conv12, %conv13
%add15 = add i32 %mul, %mac1.058
%add16 = add i32 %add15, %mul14
%arrayidx18 = getelementptr inbounds i16, i16* %arg2, i32 %add3
%6 = load i16, i16* %arrayidx18, align 2
%conv19 = sext i16 %6 to i32
%conv20 = sext i16 %2 to i32
%mul21 = mul nsw i32 %conv19, %conv20
%arrayidx23 = getelementptr inbounds i16, i16* %arg2, i32 %add5
%7 = load i16, i16* %arrayidx23, align 2
%conv24 = sext i16 %7 to i32
%conv25 = sext i16 %3 to i32
%mul26 = mul nsw i32 %conv24, %conv25
%add27 = add i32 %mul21, %mac2.057
%add28 = add i32 %add27, %mul26
%add29 = add nuw nsw i32 %i.056, 4
%cmp = icmp slt i32 %add29, %arg
br i1 %cmp, label %for.body, label %for.cond.cleanup
}
define i32 @one_zext(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
; CHECK-LABEL: @one_zext
; CHECK-NOT: call i32 @llvm.arm.smlad
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
%.pre = load i16, i16* %arg3, align 2
%.pre27 = load i16, i16* %arg2, align 2
br label %for.body
for.cond.cleanup:
%mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
ret i32 %mac1.0.lcssa
for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
%0 = load i16, i16* %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
%arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
%1 = load i16, i16* %arrayidx1, align 2
%arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
%2 = load i16, i16* %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = zext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
%arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
%3 = load i16, i16* %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = zext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
%add10 = add i32 %mul, %mac1.026
%add11 = add i32 %mul9, %add10
%exitcond = icmp ne i32 %add, %arg
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}
define i32 @two_zext(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
; CHECK-LABEL: @two_zext
; CHECK-NOT: call i32 @llvm.arm.smlad
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
%.pre = load i16, i16* %arg3, align 2
%.pre27 = load i16, i16* %arg2, align 2
br label %for.body
for.cond.cleanup:
%mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
ret i32 %mac1.0.lcssa
for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
%0 = load i16, i16* %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
%arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
%1 = load i16, i16* %arrayidx1, align 2
%arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
%2 = load i16, i16* %arrayidx3, align 2
%conv = zext i16 %2 to i32
%conv4 = zext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
%arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
%3 = load i16, i16* %arrayidx6, align 2
%conv7 = zext i16 %3 to i32
%conv8 = zext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
%add10 = add i32 %mul, %mac1.026
%add11 = add i32 %mul9, %add10
%exitcond = icmp ne i32 %add, %arg
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}