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Differential D64561

Add address-space mangling for stack related intrinsics
ClosedPublic

Authored by cdevadas on Jul 11 2019, 5:56 AM.

Details

Reviewers
arsenm
Commits
rG006cf8c03d77: Added address-space mangling for stack related intrinsics
rL366679: Added address-space mangling for stack related intrinsics
Summary

This patch includes the changes for intrinsics
int_addressofreturnaddress,
int_frameaddress & int_sponentry.
A few more intrinsics will be coming with
similar changes in future patches.

Diff Detail

Event Timeline

cdevadas created this revision.Jul 11 2019, 5:56 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 11 2019, 5:56 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
arsenm added a comment.Jul 11 2019, 6:14 AM

There also need to be some codegen changes. SelectionDAG uses the wrong pointer type as well when lowering

lib/CodeGen/SjLjEHPrepare.cpp
481

This needs to use the alloca address space

lib/Target/X86/X86WinEHState.cpp
343

Ditto

lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
768–770

Ditto

904

Ditto

lib/Transforms/Instrumentation/SanitizerCoverage.cpp
846

Ditto

cdevadas updated this revision to Diff 209465.Jul 12 2019, 5:42 AM

Added allocaAddressSpace.

arsenm added inline comments.Jul 15 2019, 6:11 AM
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
5557–5558

You can use TLI.getFrameIndexTy

cdevadas updated this revision to Diff 210082.Jul 16 2019, 6:19 AM

Used TLI.getFrameIndexTy. Thanks.

arsenm accepted this revision.Jul 19 2019, 10:45 AM

LGTM

This revision is now accepted and ready to land.Jul 19 2019, 10:45 AM
Closed by commit rL366679: Added address-space mangling for stack related intrinsics (authored by cdevadas). · Explain WhyJul 22 2019, 5:46 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
include/
llvm/
IR/
6 lines
lib/
CodeGen/
SelectionDAG/
4 lines
5 lines
Target/
X86/
5 lines
Transforms/
Instrumentation/
11 lines
6 lines
test/
Bitcode/
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
Instrumentation/
HWAddressSanitizer/
2 lines
2 lines
SanitizerCoverage/
4 lines
Verifier/
2 lines

Diff 210082

include/llvm/IR/Intrinsics.td

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def int_objc_arc_annotation_bottomup_bbend : Intrinsic<[], def int_objc_arc_annotation_bottomup_bbend : Intrinsic<[],
[llvm_ptrptr_ty, [llvm_ptrptr_ty,
llvm_ptrptr_ty]>; llvm_ptrptr_ty]>;
//===--------------------- Code Generator Intrinsics ----------------------===// //===--------------------- Code Generator Intrinsics ----------------------===//
// //
def int_returnaddress : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty], [IntrNoMem, ImmArg<0>]>; def int_returnaddress : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty], [IntrNoMem, ImmArg<0>]>;
def int_addressofreturnaddress : Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>; def int_addressofreturnaddress : Intrinsic<[llvm_anyptr_ty], [], [IntrNoMem]>;
def int_frameaddress : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty], [IntrNoMem, ImmArg<0>]>; def int_frameaddress : Intrinsic<[llvm_anyptr_ty], [llvm_i32_ty], [IntrNoMem, ImmArg<0>]>;
def int_sponentry : Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>; def int_sponentry : Intrinsic<[llvm_anyptr_ty], [], [IntrNoMem]>;
def int_read_register : Intrinsic<[llvm_anyint_ty], [llvm_metadata_ty], def int_read_register : Intrinsic<[llvm_anyint_ty], [llvm_metadata_ty],
[IntrReadMem], "llvm.read_register">; [IntrReadMem], "llvm.read_register">;
def int_write_register : Intrinsic<[], [llvm_metadata_ty, llvm_anyint_ty], def int_write_register : Intrinsic<[], [llvm_metadata_ty, llvm_anyint_ty],
[], "llvm.write_register">; [], "llvm.write_register">;
// Gets the address of the local variable area. This is typically a copy of the // Gets the address of the local variable area. This is typically a copy of the
// stack, frame, or base pointer depending on the type of prologue. // stack, frame, or base pointer depending on the type of prologue.
def int_localaddress : Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>; def int_localaddress : Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
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lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,548 Lines • ▼ Show 20 Lines setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
getValue(I.getArgOperand(0)))); getValue(I.getArgOperand(0))));
return; return;
case Intrinsic::addressofreturnaddress: case Intrinsic::addressofreturnaddress:
setValue(&I, DAG.getNode(ISD::ADDROFRETURNADDR, sdl, setValue(&I, DAG.getNode(ISD::ADDROFRETURNADDR, sdl,
TLI.getPointerTy(DAG.getDataLayout()))); TLI.getPointerTy(DAG.getDataLayout())));
return; return;
case Intrinsic::sponentry: case Intrinsic::sponentry:
setValue(&I, DAG.getNode(ISD::SPONENTRY, sdl, setValue(&I, DAG.getNode(ISD::SPONENTRY, sdl,
TLI.getPointerTy(DAG.getDataLayout()))); TLI.getFrameIndexTy(DAG.getDataLayout())));
return; return;
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You can use TLI.getFrameIndexTy

arsenm: You can use TLI.getFrameIndexTy
case Intrinsic::frameaddress: case Intrinsic::frameaddress:
setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
TLI.getPointerTy(DAG.getDataLayout()), TLI.getFrameIndexTy(DAG.getDataLayout()),
getValue(I.getArgOperand(0)))); getValue(I.getArgOperand(0))));
return; return;
case Intrinsic::read_register: { case Intrinsic::read_register: {
Value *Reg = I.getArgOperand(0); Value *Reg = I.getArgOperand(0);
SDValue Chain = getRoot(); SDValue Chain = getRoot();
SDValue RegName = SDValue RegName =
DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata())); DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
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lib/CodeGen/SjLjEHPrepare.cpp

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bool SjLjEHPrepare::runOnFunction(Function &F) { bool SjLjEHPrepare::runOnFunction(Function &F) {
Module &M = *F.getParent(); Module &M = *F.getParent();
RegisterFn = M.getOrInsertFunction( RegisterFn = M.getOrInsertFunction(
"_Unwind_SjLj_Register", Type::getVoidTy(M.getContext()), "_Unwind_SjLj_Register", Type::getVoidTy(M.getContext()),
PointerType::getUnqual(FunctionContextTy)); PointerType::getUnqual(FunctionContextTy));
UnregisterFn = M.getOrInsertFunction( UnregisterFn = M.getOrInsertFunction(
"_Unwind_SjLj_Unregister", Type::getVoidTy(M.getContext()), "_Unwind_SjLj_Unregister", Type::getVoidTy(M.getContext()),
PointerType::getUnqual(FunctionContextTy)); PointerType::getUnqual(FunctionContextTy));
FrameAddrFn = Intrinsic::getDeclaration(&M, Intrinsic::frameaddress); FrameAddrFn = Intrinsic::getDeclaration(
&M, Intrinsic::frameaddress,
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This needs to use the alloca address space

arsenm: This needs to use the alloca address space
{Type::getInt8PtrTy(M.getContext(),
M.getDataLayout().getAllocaAddrSpace())});
StackAddrFn = Intrinsic::getDeclaration(&M, Intrinsic::stacksave); StackAddrFn = Intrinsic::getDeclaration(&M, Intrinsic::stacksave);
StackRestoreFn = Intrinsic::getDeclaration(&M, Intrinsic::stackrestore); StackRestoreFn = Intrinsic::getDeclaration(&M, Intrinsic::stackrestore);
BuiltinSetupDispatchFn = BuiltinSetupDispatchFn =
Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_setup_dispatch); Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_setup_dispatch);
LSDAAddrFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_lsda); LSDAAddrFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_lsda);
CallSiteFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_callsite); CallSiteFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_callsite);
FuncCtxFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_functioncontext); FuncCtxFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_functioncontext);
bool Res = setupEntryBlockAndCallSites(F); bool Res = setupEntryBlockAndCallSites(F);
return Res; return Res;
} }

lib/Target/X86/X86WinEHState.cpp

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LSDA = Builder.CreateXor(LSDA, Val); LSDA = Builder.CreateXor(LSDA, Val);
} }
Builder.CreateStore(LSDA, Builder.CreateStructGEP(RegNodeTy, RegNode, 3)); Builder.CreateStore(LSDA, Builder.CreateStructGEP(RegNodeTy, RegNode, 3));
// If using _except_handler4, the EHGuard contains: FramePtr xor Cookie. // If using _except_handler4, the EHGuard contains: FramePtr xor Cookie.
if (UseStackGuard) { if (UseStackGuard) {
Value *Val = Builder.CreateLoad(Int32Ty, Cookie); Value *Val = Builder.CreateLoad(Int32Ty, Cookie);
Value *FrameAddr = Builder.CreateCall( Value *FrameAddr = Builder.CreateCall(
Intrinsic::getDeclaration(TheModule, Intrinsic::frameaddress), Intrinsic::getDeclaration(
TheModule, Intrinsic::frameaddress,
arsenmUnsubmitted
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Ditto

arsenm: Ditto
Builder.getInt8PtrTy(
TheModule->getDataLayout().getAllocaAddrSpace())),
Builder.getInt32(0), "frameaddr"); Builder.getInt32(0), "frameaddr");
Value *FrameAddrI32 = Builder.CreatePtrToInt(FrameAddr, Int32Ty); Value *FrameAddrI32 = Builder.CreatePtrToInt(FrameAddr, Int32Ty);
FrameAddrI32 = Builder.CreateXor(FrameAddrI32, Val); FrameAddrI32 = Builder.CreateXor(FrameAddrI32, Val);
Builder.CreateStore(FrameAddrI32, EHGuardNode); Builder.CreateStore(FrameAddrI32, EHGuardNode);
} }
// Register the exception handler. // Register the exception handler.
Link = Builder.CreateStructGEP(RegNodeTy, RegNode, 2); Link = Builder.CreateStructGEP(RegNodeTy, RegNode, 2);
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lib/Transforms/Instrumentation/HWAddressSanitizer.cpp

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Value *HWAddressSanitizer::getStackBaseTag(IRBuilder<> &IRB) { Value *HWAddressSanitizer::getStackBaseTag(IRBuilder<> &IRB) {
if (ClGenerateTagsWithCalls) if (ClGenerateTagsWithCalls)
return getNextTagWithCall(IRB); return getNextTagWithCall(IRB);
if (StackBaseTag) if (StackBaseTag)
return StackBaseTag; return StackBaseTag;
// FIXME: use addressofreturnaddress (but implement it in aarch64 backend // FIXME: use addressofreturnaddress (but implement it in aarch64 backend
// first). // first).
Module *M = IRB.GetInsertBlock()->getParent()->getParent(); Module *M = IRB.GetInsertBlock()->getParent()->getParent();
auto GetStackPointerFn = auto GetStackPointerFn = Intrinsic::getDeclaration(
Intrinsic::getDeclaration(M, Intrinsic::frameaddress); M, Intrinsic::frameaddress,
IRB.getInt8PtrTy(M->getDataLayout().getAllocaAddrSpace()));
arsenmUnsubmitted
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Ditto

arsenm: Ditto
Value *StackPointer = IRB.CreateCall( Value *StackPointer = IRB.CreateCall(
GetStackPointerFn, {Constant::getNullValue(IRB.getInt32Ty())}); GetStackPointerFn, {Constant::getNullValue(IRB.getInt32Ty())});
// Extract some entropy from the stack pointer for the tags. // Extract some entropy from the stack pointer for the tags.
// Take bits 20..28 (ASLR entropy) and xor with bits 0..8 (these differ // Take bits 20..28 (ASLR entropy) and xor with bits 0..8 (these differ
// between functions). // between functions).
Value *StackPointerLong = IRB.CreatePointerCast(StackPointer, IntptrTy); Value *StackPointerLong = IRB.CreatePointerCast(StackPointer, IntptrTy);
Value *StackTag = Value *StackTag =
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StackBaseTag = IRB.CreateAShr(ThreadLong, 3); StackBaseTag = IRB.CreateAShr(ThreadLong, 3);
// Prepare ring buffer data. // Prepare ring buffer data.
Value *PC; Value *PC;
if (TargetTriple.getArch() == Triple::aarch64) if (TargetTriple.getArch() == Triple::aarch64)
PC = readRegister(IRB, "pc"); PC = readRegister(IRB, "pc");
else else
PC = IRB.CreatePtrToInt(F, IntptrTy); PC = IRB.CreatePtrToInt(F, IntptrTy);
auto GetStackPointerFn = Module *M = F->getParent();
Intrinsic::getDeclaration(F->getParent(), Intrinsic::frameaddress); auto GetStackPointerFn = Intrinsic::getDeclaration(
arsenmUnsubmitted
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Ditto

arsenm: Ditto
M, Intrinsic::frameaddress,
IRB.getInt8PtrTy(M->getDataLayout().getAllocaAddrSpace()));
Value *SP = IRB.CreatePtrToInt( Value *SP = IRB.CreatePtrToInt(
IRB.CreateCall(GetStackPointerFn, IRB.CreateCall(GetStackPointerFn,
{Constant::getNullValue(IRB.getInt32Ty())}), {Constant::getNullValue(IRB.getInt32Ty())}),
IntptrTy); IntptrTy);
// Mix SP and PC. // Mix SP and PC.
// Assumptions: // Assumptions:
// PC is 0x0000PPPPPPPPPPPP (48 bits are meaningful, others are zero) // PC is 0x0000PPPPPPPPPPPP (48 bits are meaningful, others are zero)
// SP is 0xsssssssssssSSSS0 (4 lower bits are zero) // SP is 0xsssssssssssSSSS0 (4 lower bits are zero)
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lib/Transforms/Instrumentation/SanitizerCoverage.cpp

Show First 20 Lines • Show All 836 Lines • ▼ Show 20 Lines if (Options.Inline8bitCounters) {
auto Load = IRB.CreateLoad(Int8Ty, CounterPtr); auto Load = IRB.CreateLoad(Int8Ty, CounterPtr);
auto Inc = IRB.CreateAdd(Load, ConstantInt::get(Int8Ty, 1)); auto Inc = IRB.CreateAdd(Load, ConstantInt::get(Int8Ty, 1));
auto Store = IRB.CreateStore(Inc, CounterPtr); auto Store = IRB.CreateStore(Inc, CounterPtr);
SetNoSanitizeMetadata(Load); SetNoSanitizeMetadata(Load);
SetNoSanitizeMetadata(Store); SetNoSanitizeMetadata(Store);
} }
if (Options.StackDepth && IsEntryBB && !IsLeafFunc) { if (Options.StackDepth && IsEntryBB && !IsLeafFunc) {
// Check stack depth. If it's the deepest so far, record it. // Check stack depth. If it's the deepest so far, record it.
Function *GetFrameAddr = Module *M = F.getParent();
Intrinsic::getDeclaration(F.getParent(), Intrinsic::frameaddress); Function *GetFrameAddr = Intrinsic::getDeclaration(
arsenmUnsubmitted
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Ditto

arsenm: Ditto
M, Intrinsic::frameaddress,
IRB.getInt8PtrTy(M->getDataLayout().getAllocaAddrSpace()));
auto FrameAddrPtr = auto FrameAddrPtr =
IRB.CreateCall(GetFrameAddr, {Constant::getNullValue(Int32Ty)}); IRB.CreateCall(GetFrameAddr, {Constant::getNullValue(Int32Ty)});
auto FrameAddrInt = IRB.CreatePtrToInt(FrameAddrPtr, IntptrTy); auto FrameAddrInt = IRB.CreatePtrToInt(FrameAddrPtr, IntptrTy);
auto LowestStack = IRB.CreateLoad(IntptrTy, SanCovLowestStack); auto LowestStack = IRB.CreateLoad(IntptrTy, SanCovLowestStack);
auto IsStackLower = IRB.CreateICmpULT(FrameAddrInt, LowestStack); auto IsStackLower = IRB.CreateICmpULT(FrameAddrInt, LowestStack);
auto ThenTerm = SplitBlockAndInsertIfThen(IsStackLower, &*IP, false); auto ThenTerm = SplitBlockAndInsertIfThen(IsStackLower, &*IP, false);
IRBuilder<> ThenIRB(ThenTerm); IRBuilder<> ThenIRB(ThenTerm);
auto Store = ThenIRB.CreateStore(FrameAddrInt, SanCovLowestStack); auto Store = ThenIRB.CreateStore(FrameAddrInt, SanCovLowestStack);
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test/Bitcode/compatibility-3.6.ll

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declare void @llvm.clear_cache(i8*, i8*) declare void @llvm.clear_cache(i8*, i8*)
declare void @llvm.instrprof_increment(i8*, i64, i32, i32) declare void @llvm.instrprof_increment(i8*, i64, i32, i32)
!10 = !{!"rax"} !10 = !{!"rax"}
define void @intrinsics.codegen() { define void @intrinsics.codegen() {
call i8* @llvm.returnaddress(i32 1) call i8* @llvm.returnaddress(i32 1)
; CHECK: call i8* @llvm.returnaddress(i32 1) ; CHECK: call i8* @llvm.returnaddress(i32 1)
call i8* @llvm.frameaddress(i32 1) call i8* @llvm.frameaddress(i32 1)
; CHECK: call i8* @llvm.frameaddress(i32 1) ; CHECK: call i8* @llvm.frameaddress.p0i8(i32 1)
call i32 @llvm.read_register.i32(metadata !10) call i32 @llvm.read_register.i32(metadata !10)
; CHECK: call i32 @llvm.read_register.i32(metadata !10) ; CHECK: call i32 @llvm.read_register.i32(metadata !10)
call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
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test/Bitcode/compatibility-3.7.ll

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declare void @llvm.clear_cache(i8*, i8*) declare void @llvm.clear_cache(i8*, i8*)
declare void @llvm.instrprof_increment(i8*, i64, i32, i32) declare void @llvm.instrprof_increment(i8*, i64, i32, i32)
!10 = !{!"rax"} !10 = !{!"rax"}
define void @intrinsics.codegen() { define void @intrinsics.codegen() {
call i8* @llvm.returnaddress(i32 1) call i8* @llvm.returnaddress(i32 1)
; CHECK: call i8* @llvm.returnaddress(i32 1) ; CHECK: call i8* @llvm.returnaddress(i32 1)
call i8* @llvm.frameaddress(i32 1) call i8* @llvm.frameaddress(i32 1)
; CHECK: call i8* @llvm.frameaddress(i32 1) ; CHECK: call i8* @llvm.frameaddress.p0i8(i32 1)
call i32 @llvm.read_register.i32(metadata !10) call i32 @llvm.read_register.i32(metadata !10)
; CHECK: call i32 @llvm.read_register.i32(metadata !10) ; CHECK: call i32 @llvm.read_register.i32(metadata !10)
call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
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test/Bitcode/compatibility-3.8.ll

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declare void @llvm.clear_cache(i8*, i8*) declare void @llvm.clear_cache(i8*, i8*)
declare void @llvm.instrprof_increment(i8*, i64, i32, i32) declare void @llvm.instrprof_increment(i8*, i64, i32, i32)
!10 = !{!"rax"} !10 = !{!"rax"}
define void @intrinsics.codegen() { define void @intrinsics.codegen() {
call i8* @llvm.returnaddress(i32 1) call i8* @llvm.returnaddress(i32 1)
; CHECK: call i8* @llvm.returnaddress(i32 1) ; CHECK: call i8* @llvm.returnaddress(i32 1)
call i8* @llvm.frameaddress(i32 1) call i8* @llvm.frameaddress(i32 1)
; CHECK: call i8* @llvm.frameaddress(i32 1) ; CHECK: call i8* @llvm.frameaddress.p0i8(i32 1)
call i32 @llvm.read_register.i32(metadata !10) call i32 @llvm.read_register.i32(metadata !10)
; CHECK: call i32 @llvm.read_register.i32(metadata !10) ; CHECK: call i32 @llvm.read_register.i32(metadata !10)
call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
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test/Bitcode/compatibility-3.9.ll

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declare void @llvm.clear_cache(i8*, i8*) declare void @llvm.clear_cache(i8*, i8*)
declare void @llvm.instrprof_increment(i8*, i64, i32, i32) declare void @llvm.instrprof_increment(i8*, i64, i32, i32)
!10 = !{!"rax"} !10 = !{!"rax"}
define void @intrinsics.codegen() { define void @intrinsics.codegen() {
call i8* @llvm.returnaddress(i32 1) call i8* @llvm.returnaddress(i32 1)
; CHECK: call i8* @llvm.returnaddress(i32 1) ; CHECK: call i8* @llvm.returnaddress(i32 1)
call i8* @llvm.frameaddress(i32 1) call i8* @llvm.frameaddress(i32 1)
; CHECK: call i8* @llvm.frameaddress(i32 1) ; CHECK: call i8* @llvm.frameaddress.p0i8(i32 1)
call i32 @llvm.read_register.i32(metadata !10) call i32 @llvm.read_register.i32(metadata !10)
; CHECK: call i32 @llvm.read_register.i32(metadata !10) ; CHECK: call i32 @llvm.read_register.i32(metadata !10)
call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
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test/Bitcode/compatibility-4.0.ll

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declare void @llvm.clear_cache(i8*, i8*) declare void @llvm.clear_cache(i8*, i8*)
declare void @llvm.instrprof_increment(i8*, i64, i32, i32) declare void @llvm.instrprof_increment(i8*, i64, i32, i32)
!10 = !{!"rax"} !10 = !{!"rax"}
define void @intrinsics.codegen() { define void @intrinsics.codegen() {
call i8* @llvm.returnaddress(i32 1) call i8* @llvm.returnaddress(i32 1)
; CHECK: call i8* @llvm.returnaddress(i32 1) ; CHECK: call i8* @llvm.returnaddress(i32 1)
call i8* @llvm.frameaddress(i32 1) call i8* @llvm.frameaddress(i32 1)
; CHECK: call i8* @llvm.frameaddress(i32 1) ; CHECK: call i8* @llvm.frameaddress.p0i8(i32 1)
call i32 @llvm.read_register.i32(metadata !10) call i32 @llvm.read_register.i32(metadata !10)
; CHECK: call i32 @llvm.read_register.i32(metadata !10) ; CHECK: call i32 @llvm.read_register.i32(metadata !10)
call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
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test/Bitcode/compatibility-5.0.ll

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declare void @llvm.clear_cache(i8*, i8*) declare void @llvm.clear_cache(i8*, i8*)
declare void @llvm.instrprof_increment(i8*, i64, i32, i32) declare void @llvm.instrprof_increment(i8*, i64, i32, i32)
!10 = !{!"rax"} !10 = !{!"rax"}
define void @intrinsics.codegen() { define void @intrinsics.codegen() {
call i8* @llvm.returnaddress(i32 1) call i8* @llvm.returnaddress(i32 1)
; CHECK: call i8* @llvm.returnaddress(i32 1) ; CHECK: call i8* @llvm.returnaddress(i32 1)
call i8* @llvm.frameaddress(i32 1) call i8* @llvm.frameaddress(i32 1)
; CHECK: call i8* @llvm.frameaddress(i32 1) ; CHECK: call i8* @llvm.frameaddress.p0i8(i32 1)
call i32 @llvm.read_register.i32(metadata !10) call i32 @llvm.read_register.i32(metadata !10)
; CHECK: call i32 @llvm.read_register.i32(metadata !10) ; CHECK: call i32 @llvm.read_register.i32(metadata !10)
call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
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test/Bitcode/compatibility-6.0.ll

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declare void @llvm.clear_cache(i8*, i8*) declare void @llvm.clear_cache(i8*, i8*)
declare void @llvm.instrprof_increment(i8*, i64, i32, i32) declare void @llvm.instrprof_increment(i8*, i64, i32, i32)
!10 = !{!"rax"} !10 = !{!"rax"}
define void @intrinsics.codegen() { define void @intrinsics.codegen() {
call i8* @llvm.returnaddress(i32 1) call i8* @llvm.returnaddress(i32 1)
; CHECK: call i8* @llvm.returnaddress(i32 1) ; CHECK: call i8* @llvm.returnaddress(i32 1)
call i8* @llvm.frameaddress(i32 1) call i8* @llvm.frameaddress(i32 1)
; CHECK: call i8* @llvm.frameaddress(i32 1) ; CHECK: call i8* @llvm.frameaddress.p0i8(i32 1)
call i32 @llvm.read_register.i32(metadata !10) call i32 @llvm.read_register.i32(metadata !10)
; CHECK: call i32 @llvm.read_register.i32(metadata !10) ; CHECK: call i32 @llvm.read_register.i32(metadata !10)
call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
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test/Bitcode/compatibility.ll

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declare void @llvm.clear_cache(i8*, i8*) declare void @llvm.clear_cache(i8*, i8*)
declare void @llvm.instrprof_increment(i8*, i64, i32, i32) declare void @llvm.instrprof_increment(i8*, i64, i32, i32)
!10 = !{!"rax"} !10 = !{!"rax"}
define void @intrinsics.codegen() { define void @intrinsics.codegen() {
call i8* @llvm.returnaddress(i32 1) call i8* @llvm.returnaddress(i32 1)
; CHECK: call i8* @llvm.returnaddress(i32 1) ; CHECK: call i8* @llvm.returnaddress(i32 1)
call i8* @llvm.frameaddress(i32 1) call i8* @llvm.frameaddress(i32 1)
; CHECK: call i8* @llvm.frameaddress(i32 1) ; CHECK: call i8* @llvm.frameaddress.p0i8(i32 1)
call i32 @llvm.read_register.i32(metadata !10) call i32 @llvm.read_register.i32(metadata !10)
; CHECK: call i32 @llvm.read_register.i32(metadata !10) ; CHECK: call i32 @llvm.read_register.i32(metadata !10)
call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
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test/Instrumentation/HWAddressSanitizer/alloca.ll

; Test alloca instrumentation. ; Test alloca instrumentation.
; ;
; RUN: opt < %s -hwasan -hwasan-with-ifunc=1 -S | FileCheck %s --check-prefixes=CHECK,DYNAMIC-SHADOW,NO-UAR-TAGS ; RUN: opt < %s -hwasan -hwasan-with-ifunc=1 -S | FileCheck %s --check-prefixes=CHECK,DYNAMIC-SHADOW,NO-UAR-TAGS
; RUN: opt < %s -hwasan -hwasan-mapping-offset=0 -S | FileCheck %s --check-prefixes=CHECK,ZERO-BASED-SHADOW,NO-UAR-TAGS ; RUN: opt < %s -hwasan -hwasan-mapping-offset=0 -S | FileCheck %s --check-prefixes=CHECK,ZERO-BASED-SHADOW,NO-UAR-TAGS
; RUN: opt < %s -hwasan -hwasan-with-ifunc=1 -hwasan-uar-retag-to-zero=0 -S | FileCheck %s --check-prefixes=CHECK,DYNAMIC-SHADOW,UAR-TAGS ; RUN: opt < %s -hwasan -hwasan-with-ifunc=1 -hwasan-uar-retag-to-zero=0 -S | FileCheck %s --check-prefixes=CHECK,DYNAMIC-SHADOW,UAR-TAGS
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--linux-android" target triple = "aarch64--linux-android"
declare void @use32(i32*) declare void @use32(i32*)
define void @test_alloca() sanitize_hwaddress { define void @test_alloca() sanitize_hwaddress {
; CHECK-LABEL: @test_alloca( ; CHECK-LABEL: @test_alloca(
; CHECK: %[[FP:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) ; CHECK: %[[FP:[^ ]*]] = call i8* @llvm.frameaddress.p0i8(i32 0)
; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %[[FP]] to i64 ; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %[[FP]] to i64
; CHECK: %[[B:[^ ]*]] = lshr i64 %[[A]], 20 ; CHECK: %[[B:[^ ]*]] = lshr i64 %[[A]], 20
; CHECK: %[[BASE_TAG:[^ ]*]] = xor i64 %[[A]], %[[B]] ; CHECK: %[[BASE_TAG:[^ ]*]] = xor i64 %[[A]], %[[B]]
; CHECK: %[[X:[^ ]*]] = alloca { i32, [12 x i8] }, align 16 ; CHECK: %[[X:[^ ]*]] = alloca { i32, [12 x i8] }, align 16
; CHECK: %[[X_BC:[^ ]*]] = bitcast { i32, [12 x i8] }* %[[X]] to i32* ; CHECK: %[[X_BC:[^ ]*]] = bitcast { i32, [12 x i8] }* %[[X]] to i32*
; CHECK: %[[X_TAG:[^ ]*]] = xor i64 %[[BASE_TAG]], 0 ; CHECK: %[[X_TAG:[^ ]*]] = xor i64 %[[BASE_TAG]], 0
; CHECK: %[[X1:[^ ]*]] = ptrtoint i32* %[[X_BC]] to i64 ; CHECK: %[[X1:[^ ]*]] = ptrtoint i32* %[[X_BC]] to i64
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test/Instrumentation/HWAddressSanitizer/kernel-alloca.ll

; Test kernel hwasan instrumentation for alloca. ; Test kernel hwasan instrumentation for alloca.
; ;
; RUN: opt < %s -hwasan -hwasan-kernel=1 -S | FileCheck %s ; RUN: opt < %s -hwasan -hwasan-kernel=1 -S | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--linux-android" target triple = "aarch64--linux-android"
declare void @use32(i32*) declare void @use32(i32*)
define void @test_alloca() sanitize_hwaddress { define void @test_alloca() sanitize_hwaddress {
; CHECK-LABEL: @test_alloca( ; CHECK-LABEL: @test_alloca(
; CHECK: %[[FP:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) ; CHECK: %[[FP:[^ ]*]] = call i8* @llvm.frameaddress.p0i8(i32 0)
; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %[[FP]] to i64 ; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %[[FP]] to i64
; CHECK: %[[B:[^ ]*]] = lshr i64 %[[A]], 20 ; CHECK: %[[B:[^ ]*]] = lshr i64 %[[A]], 20
; CHECK: %[[BASE_TAG:[^ ]*]] = xor i64 %[[A]], %[[B]] ; CHECK: %[[BASE_TAG:[^ ]*]] = xor i64 %[[A]], %[[B]]
; CHECK: %[[X:[^ ]*]] = alloca { i32, [12 x i8] }, align 16 ; CHECK: %[[X:[^ ]*]] = alloca { i32, [12 x i8] }, align 16
; CHECK: %[[X_BC:[^ ]*]] = bitcast { i32, [12 x i8] }* %[[X]] to i32* ; CHECK: %[[X_BC:[^ ]*]] = bitcast { i32, [12 x i8] }* %[[X]] to i32*
; CHECK: %[[X_TAG:[^ ]*]] = xor i64 %[[BASE_TAG]], 0 ; CHECK: %[[X_TAG:[^ ]*]] = xor i64 %[[BASE_TAG]], 0
; CHECK: %[[X1:[^ ]*]] = ptrtoint i32* %[[X_BC]] to i64 ; CHECK: %[[X1:[^ ]*]] = ptrtoint i32* %[[X_BC]] to i64
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test/Instrumentation/SanitizerCoverage/stack-depth.ll

; This check verifies that stack depth instrumentation works correctly. ; This check verifies that stack depth instrumentation works correctly.
; RUN: opt < %s -sancov -sanitizer-coverage-level=1 \ ; RUN: opt < %s -sancov -sanitizer-coverage-level=1 \
; RUN: -sanitizer-coverage-stack-depth -S | FileCheck %s ; RUN: -sanitizer-coverage-stack-depth -S | FileCheck %s
; RUN: opt < %s -sancov -sanitizer-coverage-level=3 \ ; RUN: opt < %s -sancov -sanitizer-coverage-level=3 \
; RUN: -sanitizer-coverage-stack-depth -sanitizer-coverage-trace-pc-guard \ ; RUN: -sanitizer-coverage-stack-depth -sanitizer-coverage-trace-pc-guard \
; RUN: -S | FileCheck %s ; RUN: -S | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; CHECK: @__sancov_lowest_stack = thread_local(initialexec) global i64 -1 ; CHECK: @__sancov_lowest_stack = thread_local(initialexec) global i64 -1
@__sancov_lowest_stack = thread_local global i64 0, align 8 @__sancov_lowest_stack = thread_local global i64 0, align 8
define i32 @foo() { define i32 @foo() {
entry: entry:
; CHECK-LABEL: define i32 @foo ; CHECK-LABEL: define i32 @foo
; CHECK-NOT: call i8* @llvm.frameaddress(i32 0) ; CHECK-NOT: call i8* @llvm.frameaddress.p0i8(i32 0)
; CHECK-NOT: @__sancov_lowest_stack ; CHECK-NOT: @__sancov_lowest_stack
; CHECK: ret i32 7 ; CHECK: ret i32 7
ret i32 7 ret i32 7
} }
define i32 @bar() { define i32 @bar() {
entry: entry:
; CHECK-LABEL: define i32 @bar ; CHECK-LABEL: define i32 @bar
; CHECK: [[framePtr:%[^ \t]+]] = call i8* @llvm.frameaddress(i32 0) ; CHECK: [[framePtr:%[^ \t]+]] = call i8* @llvm.frameaddress.p0i8(i32 0)
; CHECK: [[frameInt:%[^ \t]+]] = ptrtoint i8* [[framePtr]] to [[intType:i[0-9]+]] ; CHECK: [[frameInt:%[^ \t]+]] = ptrtoint i8* [[framePtr]] to [[intType:i[0-9]+]]
; CHECK: [[lowest:%[^ \t]+]] = load [[intType]], [[intType]]* @__sancov_lowest_stack ; CHECK: [[lowest:%[^ \t]+]] = load [[intType]], [[intType]]* @__sancov_lowest_stack
; CHECK: [[cmp:%[^ \t]+]] = icmp ult [[intType]] [[frameInt]], [[lowest]] ; CHECK: [[cmp:%[^ \t]+]] = icmp ult [[intType]] [[frameInt]], [[lowest]]
; CHECK: br i1 [[cmp]], label %[[ifLabel:[^ \t]+]], label ; CHECK: br i1 [[cmp]], label %[[ifLabel:[^ \t]+]], label
; CHECK: [[ifLabel]]: ; CHECK: [[ifLabel]]:
; CHECK: store [[intType]] [[frameInt]], [[intType]]* @__sancov_lowest_stack ; CHECK: store [[intType]] [[frameInt]], [[intType]]* @__sancov_lowest_stack
; CHECK: %call = call i32 @foo() ; CHECK: %call = call i32 @foo()
; CHECK: ret i32 %call ; CHECK: ret i32 %call
%call = call i32 @foo() %call = call i32 @foo()
ret i32 %call ret i32 %call
} }
define weak_odr hidden i64* @_ZTW21__sancov_lowest_stack() { define weak_odr hidden i64* @_ZTW21__sancov_lowest_stack() {
ret i64* @__sancov_lowest_stack ret i64* @__sancov_lowest_stack
} }

test/Verifier/intrinsic-immarg.ll

; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s ; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
declare i8* @llvm.returnaddress(i32) declare i8* @llvm.returnaddress(i32)
define void @return_address(i32 %var) { define void @return_address(i32 %var) {
; CHECK: immarg operand has non-immediate parameter ; CHECK: immarg operand has non-immediate parameter
; CHECK-NEXT: i32 %var ; CHECK-NEXT: i32 %var
; CHECK-NEXT: %result = call i8* @llvm.returnaddress(i32 %var) ; CHECK-NEXT: %result = call i8* @llvm.returnaddress(i32 %var)
%result = call i8* @llvm.returnaddress(i32 %var) %result = call i8* @llvm.returnaddress(i32 %var)
ret void ret void
} }
declare i8* @llvm.frameaddress(i32) declare i8* @llvm.frameaddress(i32)
define void @frame_address(i32 %var) { define void @frame_address(i32 %var) {
; CHECK: immarg operand has non-immediate parameter ; CHECK: immarg operand has non-immediate parameter
; CHECK-NEXT: i32 %var ; CHECK-NEXT: i32 %var
; CHECK-NEXT: %result = call i8* @llvm.frameaddress(i32 %var) ; CHECK-NEXT: %result = call i8* @llvm.frameaddress.p0i8(i32 %var)
%result = call i8* @llvm.frameaddress(i32 %var) %result = call i8* @llvm.frameaddress(i32 %var)
ret void ret void
} }
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1)
define void @memcpy(i8* %dest, i8* %src, i1 %is.volatile) { define void @memcpy(i8* %dest, i8* %src, i1 %is.volatile) {
; CHECK: immarg operand has non-immediate parameter ; CHECK: immarg operand has non-immediate parameter
; CHECK-NEXT: i1 %is.volatile ; CHECK-NEXT: i1 %is.volatile
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