[AArch64] Don't combine "select (setcc i1 LHS, RHS), vL, vR".

[ab]

Summary

r208210 introduced an optimization that improves the vector select
codegen by doing the setcc on vectors directly.
This is a problem when the setcc operands are i1s, because the
optimization would create vectors of i1, which aren't legal.

Part of PR21549.

[ab]

Ping for a short patch!

-Ahmed

[t.p.northover]

Sorry Ahmed, I think this looks fine.

Tim.

[ab]

Closed by commit rL223075 (authored by @ab).

lib/Target/AArch64/AArch64ISelLowering.cpp

static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
 
   if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
     return SDValue();
 
   // If NumMaskElts == 0, the comparison is larger than select result. The
   // largest real NEON comparison is 64-bits per lane, which means the result is
   // at most 32-bits and an illegal vector. Just bail out for now.
   EVT SrcVT = N0.getOperand(0).getValueType();
+
+  // Don't try to do this optimization when the setcc itself has i1 operands.
+  // There are no legal vectors of i1, so this would be pointless.
+  if (SrcVT == MVT::i1)
+    return SDValue();
+
   int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
   if (!ResVT.isVector() || NumMaskElts == 0)
     return SDValue();
 
   SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
   EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
 
   // First perform a vector comparison, where lane 0 is the one we're interested

test/CodeGen/AArch64/arm64-neon-select_cc.ll

 ; CHECK-LABEL: test_select_cc_v2f64:
 ; CHECK: fcmeq [[MASK:v[0-9]+]].2d, v0.2d, v1.2d
 ; CHECK: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0]
 ; CHECK: bsl [[DUPMASK]].16b, v2.16b, v3.16b
   %cmp31 = fcmp oeq double %a, %b
   %e = select i1 %cmp31, <2 x double> %c, <2 x double> %d
   ret <2 x double> %e
 }
+
+; Special case: when the select condition is an icmp with i1 operands, don't
+; do the comparison on vectors.
+; Part of PR21549.
+define <2 x i32> @test_select_cc_v2i32_icmpi1(i1 %cc, <2 x i32> %a, <2 x i32> %b) {
+; CHECK-LABEL: test_select_cc_v2i32_icmpi1:
+; CHECK: tst   w0, #0x1
+; CHECK: csetm [[MASK:w[0-9]+]], ne
+; CHECK: dup   [[DUPMASK:v[0-9]+]].2s, [[MASK]]
+; CHECK: bsl   [[DUPMASK]].8b, v0.8b, v1.8b
+; CHECK: mov   v0.16b, [[DUPMASK]].16b
+  %cmp = icmp ne i1 %cc, 0
+  %e = select i1 %cmp, <2 x i32> %a, <2 x i32> %b
+  ret <2 x i32> %e
+}