AtomicExpand: Don't crash on non-0 alloca

[arsenm]

Summary

This now produces garbage on AMDGPU with a call to an nonexistent,
anonymous libcall but won't assert.

[arsenm]

ping

[reames]

LGTM for the AtomicExpand parts. I'm willing to assume you know what you're doing for the AMDGPU bit. :)

[arsenm]

r363022

lib/CodeGen/AtomicExpandPass.cpp

Value *PtrVal = Builder.CreateBitCast(PointerOperand,
                                         Type::getInt8PtrTy(Ctx, PtrTypeAS));
   PtrVal = Builder.CreateAddrSpaceCast(PtrVal, Type::getInt8PtrTy(Ctx));
   Args.push_back(PtrVal);
 
   // 'expected' argument, if present.
   if (CASExpected) {
     AllocaCASExpected = AllocaBuilder.CreateAlloca(CASExpected->getType());
     AllocaCASExpected->setAlignment(AllocaAlignment);
+    unsigned AllocaAS =  AllocaCASExpected->getType()->getPointerAddressSpace();
+
     AllocaCASExpected_i8 =
-        Builder.CreateBitCast(AllocaCASExpected, Type::getInt8PtrTy(Ctx));
+      Builder.CreateBitCast(AllocaCASExpected,
+                            Type::getInt8PtrTy(Ctx, AllocaAS));
     Builder.CreateLifetimeStart(AllocaCASExpected_i8, SizeVal64);
     Builder.CreateAlignedStore(CASExpected, AllocaCASExpected, AllocaAlignment);
     Args.push_back(AllocaCASExpected_i8);
   }
 
   // 'val' argument ('desired' for cas), if present.
   if (ValueOperand) {
     if (UseSizedLibcall) {
if (UseSizedLibcall) {
       Args.push_back(AllocaValue_i8);
     }
   }
 
   // 'ret' argument.
   if (!CASExpected && HasResult && !UseSizedLibcall) {
     AllocaResult = AllocaBuilder.CreateAlloca(I->getType());
     AllocaResult->setAlignment(AllocaAlignment);
+    unsigned AllocaAS =  AllocaResult->getType()->getPointerAddressSpace();
     AllocaResult_i8 =
-        Builder.CreateBitCast(AllocaResult, Type::getInt8PtrTy(Ctx));
+      Builder.CreateBitCast(AllocaResult, Type::getInt8PtrTy(Ctx, AllocaAS));
     Builder.CreateLifetimeStart(AllocaResult_i8, SizeVal64);
     Args.push_back(AllocaResult_i8);
   }
 
   // 'ordering' ('success_order' for cas) argument.
   Args.push_back(OrderingVal);
 
   // 'failure_order' argument, if present.

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
   // SGPR pair can be a condition register. If we have a uniform condition, we
   // are better off doing SALU operations, where there is only one SCC. For now,
   // we don't have a way of knowing during instruction selection if a condition
   // will be uniform and we always use vector compares. Assume we are using
   // vector compares until that is fixed.
   setHasMultipleConditionRegisters(true);
 
   setMinCmpXchgSizeInBits(32);
+  setSupportsUnalignedAtomics(false);
 
   PredictableSelectIsExpensive = false;
 
   // We want to find all load dependencies for long chains of stores to enable
   // merging into very wide vectors. The problem is with vectors with > 4
   // elements. MergeConsecutiveStores will attempt to merge these because x8/x16
   // vectors are a legal type, even though we have to split the loads
   // usually. When we can more precisely specify load legality per address

test/Transforms/AtomicExpand/AMDGPU/unaligned-atomic.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -atomic-expand %s | FileCheck -check-prefix=GCN %s
+
+; FIXME: This should not introduce a libcall, much less one to an
+; anonymous function.
+
+define i32 @atomic_load_global_align1(i32 addrspace(1)* %ptr) {
+; GCN-LABEL: @atomic_load_global_align1(
+; GCN-NEXT:    [[TMP1:%.*]] = bitcast i32 addrspace(1)* [[PTR:%.*]] to i8 addrspace(1)*
+; GCN-NEXT:    [[TMP2:%.*]] = addrspacecast i8 addrspace(1)* [[TMP1]] to i8*
+; GCN-NEXT:    [[TMP3:%.*]] = alloca i32, align 4
+; GCN-NEXT:    [[TMP4:%.*]] = bitcast i32* [[TMP3]] to i8*
+; GCN-NEXT:    call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]])
+; GCN-NEXT:    call void @0(i64 4, i8* [[TMP2]], i8* [[TMP4]], i32 5)
+; GCN-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 4
+; GCN-NEXT:    call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP4]])
+; GCN-NEXT:    ret i32 [[TMP5]]
+;
+  %val = load atomic i32, i32 addrspace(1)* %ptr  seq_cst, align 1
+  ret i32 %val
+}
+
+define void @atomic_store_global_align1(i32 addrspace(1)* %ptr, i32 %val) {
+; GCN-LABEL: @atomic_store_global_align1(
+; GCN-NEXT:    [[TMP1:%.*]] = bitcast i32 addrspace(1)* [[PTR:%.*]] to i8 addrspace(1)*
+; GCN-NEXT:    [[TMP2:%.*]] = addrspacecast i8 addrspace(1)* [[TMP1]] to i8*
+; GCN-NEXT:    [[TMP3:%.*]] = alloca i32, align 4
+; GCN-NEXT:    [[TMP4:%.*]] = bitcast i32* [[TMP3]] to i8*
+; GCN-NEXT:    call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]])
+; GCN-NEXT:    store i32 [[VAL:%.*]], i32* [[TMP3]], align 4
+; GCN-NEXT:    call void @1(i64 4, i8* [[TMP2]], i8* [[TMP4]], i32 0)
+; GCN-NEXT:    call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP4]])
+; GCN-NEXT:    ret void
+;
+  store atomic i32 %val, i32 addrspace(1)* %ptr monotonic, align 1
+  ret void
+}