[AVX512] Enable intrinsics for vexp2{ps/pd}

[AsafBadouh]

Summary

Enable intrinsics for vexp2{ps/pd}

[anemet]

Hi Asaf,

Please always use full context for the diffs (http://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface).

I know that you only followed rsqrt and rcp precedence but that is not how we add AVX512 intrinsic support these days. You probably want to look a few of my recent patches for details but this is the basic idea:

1. Lower the intrinsics to target-specific SDNodes in LowerINTRINSIC_WO_CHAIN
2. Add masking support to your instruction by deriving from AVX512_maskable

Also preferably:

3. Create a multiclass to hide the PS/PD duplication
4. Use X86VectorVTInfo to improve readability

Try to work with smaller patches and separate those that don't have functional changes in order to minimize the size of patches that do have functional changes.

Hopefully this is clear. Let me know if you need an sample patchset.

Thanks,
Adam

[delena]

Hi Adam,

Lower the intrinsics to target-specific SDNodes in LowerINTRINSIC_WO_CHAIN

We don't need LowerINTRINSIC_WO_CHAIN in this case, because we don't want to invent SDNode for something that reachable via intrinsics only and can't be optimized by LLVM on any stage.
So I suppose that direct mapping from intrinsic to instruction is the right way in this case.

Add masking support to your instruction by deriving from AVX512_maskable

Asaf is doing ramp-up now and we planned to start with a small simple patch and then extend it to masks and to SAE/CURRENT_DIRECTION forms.

Use X86VectorVTInfo to improve readability

Unlike other instructions, these 3 ERI instructions don't have 128 and 256 bit forms, so X86VectorVTInfo will not give too much, but we can check whether the code looks better with it.

Thank you.

• Elena

[anemet]

Very old review, requesting change to move it off my active queue.

include/llvm/IR/IntrinsicsX86.td

             Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,
                                         llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty],
                       [IntrNoMem]>;
+  def int_x86_avx512_exp2_ps : GCCBuiltin<"__builtin_ia32_exp2ps_mask">,
+            Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty, llvm_v16f32_ty,
+                                         llvm_i16_ty, llvm_i32_ty],
+                      [IntrNoMem]>;
+  def int_x86_avx512_exp2_pd : GCCBuiltin<"__builtin_ia32_exp2pd_mask">,
+            Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_v8f64_ty,
+                                        llvm_i8_ty, llvm_i32_ty],
+                      [IntrNoMem]>;
 }
 
 // Integer shift ops.

lib/Target/X86/X86InstrAVX512.td

            (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
                        (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
 
-/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
+/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd, exp2pd, exp2ps
 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
                          RegisterClass RC, X86MemOperand x86memop> {
   let hasSideEffects = 0, Predicates = [HasERI] in {

                         EVEX_V512, EVEX_CD8<32, CD8VF>;
 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
                         VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
+defm VEXP2PSZ : avx512_fp28_p<0xC8, "vexp2ps", VR512, f512mem>,
+                        EVEX_V512, EVEX_CD8<32, CD8VF>;
+defm VEXP2PDZ : avx512_fp28_p<0xC8, "vexp2pd", VR512, f512mem>,
+                        VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
 
 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
               (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),

               (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
            (VRCP28PDZrb VR512:$src)>;
 
+def : Pat <(v16f32 (int_x86_avx512_exp2_ps (v16f32 VR512:$src),
+              (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
+           (VEXP2PSZrb VR512:$src)>;
+def : Pat <(v16f32 (int_x86_avx512_exp2_ps (v16f32 VR512:$src),
+              (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
+           (VEXP2PSZr VR512:$src)>;
+def : Pat <(v8f64 (int_x86_avx512_exp2_pd (v8f64 VR512:$src),
+              (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
+           (VEXP2PDZrb VR512:$src)>;
+def : Pat <(v8f64 (int_x86_avx512_exp2_pd (v8f64 VR512:$src),
+              (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
+           (VEXP2PDZr VR512:$src)>;
+
 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
                               SDNode OpNode, X86VectorVTInfo _>{
   defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),

test/CodeGen/X86/avx512-intrinsics.ll

 }
 declare <16 x float> @llvm.x86.avx512.rsqrt28.ps(<16 x float>, <16 x float>, i16, i32) nounwind readnone
 
+define <16 x float> @test_exp2_ps_round_no_exc(<16 x float> %a0) {
+  ; CHECK: vexp2ps {sae}, {{.*}}encoding: [0x62,0xf2,0x7d,0x18,0xc8,0xc0]
+  %res = call <16 x float> @llvm.x86.avx512.exp2.ps(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1, i32 8) ; <<16 x float>> [#uses=1]
+  ret <16 x float> %res
+}
+define <16 x float> @test_exp2_ps_round_current(<16 x float> %a0) {
+  ; CHECK: vexp2ps {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0xc8,0xc0]
+  %res = call <16 x float> @llvm.x86.avx512.exp2.ps(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1, i32 4) ; <<16 x float>> [#uses=1]
+  ret <16 x float> %res
+}
+declare <16 x float> @llvm.x86.avx512.exp2.ps(<16 x float>, <16 x float>, i16, i32) nounwind readnone
+
+define <8 x double> @test_exp2_pd_round_no_exc(<8 x double> %a0) {
+  ; CHECK: vexp2pd {sae}, {{.*}}encoding: [0x62,0xf2,0xfd,0x18,0xc8,0xc0]
+  %res = call <8 x double> @llvm.x86.avx512.exp2.pd(<8 x double> %a0,  <8 x double> zeroinitializer, i8 -1, i32 8) ; <<8 x double>> [#uses=1]
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_exp2_pd_round_current(<8 x double> %a0) {
+  ; CHECK: vexp2pd {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0xc8,0xc0]
+  %res = call <8 x double> @llvm.x86.avx512.exp2.pd(<8 x double> %a0,  <8 x double> zeroinitializer, i8 -1, i32 4) ; <<8 x double>> [#uses=1]
+  ret <8 x double> %res
+}
+declare <8 x double> @llvm.x86.avx512.exp2.pd(<8 x double>, <8 x double>, i8, i32) nounwind readnone
+
 define <4 x float> @test_rsqrt14_ss(<4 x float> %a0) {
   ; CHECK: vrsqrt14ss {{.*}}encoding: [0x62,0xf2,0x7d,0x08,0x4f,0xc0]
   %res = call <4 x float> @llvm.x86.avx512.rsqrt14.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 -1) ; <<4 x float>> [#uses=1]