[DAGCombiner] Add missing flag to addressing mode check

[luismarques]

Summary

The DAGCombiner helper function canFoldInAddressingMode performs some checks for legal addressing modes, such as reg+imm. The TargetLowering::AddrMode struct used for that check should have the HasBaseReg field set to true to indicate the presence of a reg (other than the scale reg). The function did not set that field (and by default it's false). This patch corrects that oversight. No tests were impacted by the change, as the oversight did not seem to manifest as an actual problem at the moment.

[efriedma]

Probably better to put it inside the branches for ADD/SUB, to make it clear that it's those specific operations that have a base register?

Given the current places we call canFoldInAddressingMode, and that the relevant targets are missing HasBaseReg checks (in particular, I looked at ARM and AArch64), I imagine it would be very hard to reproduce any effective change, yes. (Maybe you could come up with something for 32-bit ARM if you tried hard enough, but it's probably not worth bothering.)

[asb]

With Eli's suggested change (sinking the assignment to the ADD/SUB branches), this seems good to me.

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
       return false;
     VT = ST->getMemoryVT();
     AS = ST->getAddressSpace();
   } else
     return false;
 
   TargetLowering::AddrMode AM;
   if (N->getOpcode() == ISD::ADD) {
+    AM.HasBaseReg = true;
     ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
     if (Offset)
       // [reg +/- imm]
       AM.BaseOffs = Offset->getSExtValue();
     else
       // [reg +/- reg]
       AM.Scale = 1;
   } else if (N->getOpcode() == ISD::SUB) {
+    AM.HasBaseReg = true;
     ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
     if (Offset)
       // [reg +/- imm]
       AM.BaseOffs = -Offset->getSExtValue();
     else
       // [reg +/- reg]
       AM.Scale = 1;
   } else